Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

value emitVerilog is not a member of circt.stage.ChiselStage #4603

Open
quantrpeter opened this issue Jan 9, 2025 · 1 comment
Open

value emitVerilog is not a member of circt.stage.ChiselStage #4603

quantrpeter opened this issue Jan 9, 2025 · 1 comment

Comments

@quantrpeter
Copy link

Hi
I got trouble to generate verilog, i got this error:

[info] welcome to sbt 1.10.1 (Oracle Corporation Java 23.0.1)
[info] loading project definition from /Users/peter/workspace/chisel-examples/hello-world/project

[info] loading settings for project hello-world from build.sbt ...
[info] set current project to hello-world (in build file:/Users/peter/workspace/chisel-examples/hello-world/)
[info] compiling 1 Scala source to /Users/peter/workspace/chisel-examples/hello-world/target/scala-2.13/classes ...
[error] /Users/peter/workspace/chisel-examples/hello-world/src/main/scala/Hello.scala:35:20: value emitVerilog is not a member of circt.stage.ChiselStage
[error]         new ChiselStage().emitVerilog(new Hello);
[error]                           ^
[error] one error found
[error] (Compile / compileIncremental) Compilation failed
new ChiselStage().emitVerilog(new Hello);
scalaVersion := "2.13.12"

scalacOptions ++= Seq(
  "-feature",
  "-language:reflectiveCalls",
)

// Chisel 3.5
// addCompilerPlugin("edu.berkeley.cs" % "chisel3-plugin" % "6.0.0" cross CrossVersion.full)
// libraryDependencies += "edu.berkeley.cs" %% "chisel3" % "6.0.0"
// libraryDependencies += "edu.berkeley.cs" %% "chiseltest" % "0.6.0"

val chiselVersion = "6.0.0"
addCompilerPlugin("org.chipsalliance" % "chisel-plugin" % chiselVersion cross CrossVersion.full)
libraryDependencies += "org.chipsalliance" %% "chisel" % chiselVersion
libraryDependencies += "edu.berkeley.cs" %% "chiseltest" % "0.6.0" % "test"

thanks

@seldridge
Copy link
Member

The class ChiselStage is a lower-level API that you probably don't want to use directly. You likely want to use the object ChiselStage and do something like:

// To return a string:
val verilog: String = ChiselStage.emitSystemVerilog(new Hello)
// To write to a file:
ChiselStage.emitSystemVerilogFile(new Hello)

The Scaladoc for this may help you navigate available methods: https://javadoc.io/doc/org.chipsalliance/chisel_2.13/6.0.0/circt/stage/ChiselStage$.html

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
None yet
Projects
None yet
Development

No branches or pull requests

2 participants