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IN the link https://github.com/board707/DMD_STM32/wiki/Connections---Monochrome#connecting-more-than-one-panel
I found that the lattice screen can be Parrallel connection, but in the sample file, I found that the code only declares the following pins.
But part of the actual HUB75 pin is not used, how should I match the IO of the MCU with the lattice screen? Can you give me a wiring diagram?
In addition, I found definitions of SCLK and CLK in the code. Is SCLK corresponding to LAT in HUB75E and CLK in HUB75 interface?
In addition the code uint8_t pins[] = {PA5, PA7, PA6}; // In CLK, row1, row 2
Pin PA7 which Note row1 ,what pin should I connect to the first dot screen in the first row
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IN the link https://github.com/board707/DMD_STM32/wiki/Connections---Monochrome#connecting-more-than-one-panel
I found that the lattice screen can be Parrallel connection, but in the sample file, I found that the code only declares the following pins.
But part of the actual HUB75 pin is not used, how should I match the IO of the MCU with the lattice screen? Can you give me a wiring diagram?
In addition, I found definitions of SCLK and CLK in the code. Is SCLK corresponding to LAT in HUB75E and CLK in HUB75 interface?
In addition the code uint8_t pins[] = {PA5, PA7, PA6}; // In CLK, row1, row 2
Pin PA7 which Note row1 ,what pin should I connect to the first dot screen in the first row
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