Improvement Scopes

[Mr-AniP]

Currently only two SIMD Instructions are supported (add and sub (in SIMD architecture)).

Also, currently we have implemented only execute stage level SIMD bypassing.

One more thing not all instructions provided by RISC-V architecture were implemented. (very few were left but they mostly they seem to be of significance for our project)

Last but not least for SIMD there is no special unit to compute stuff. But we propose a better model which segregates them, and stalls execute unit when working on SIMD instructions.

Much more could be added in this direction to improve the Project.

Anyway, we hope that this project will help your research/project.

Thank You.