From f9286ce0426212619b5e2524d0e7325cd977eac1 Mon Sep 17 00:00:00 2001
From: Tobias Senti <git@tsenti.li>
Date: Wed, 8 May 2024 20:18:25 +0200
Subject: [PATCH] ci: markdownlint

---
 .github/workflows/ci.yml |  8 ++++++++
 Makefile                 | 10 ++++++++--
 Readme.md                |  2 ++
 3 files changed, 18 insertions(+), 2 deletions(-)

diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml
index 4850c9a..9d068ba 100644
--- a/.github/workflows/ci.yml
+++ b/.github/workflows/ci.yml
@@ -50,6 +50,14 @@ jobs:
       - name: Run veriloglint
         run: make veriloglint
 
+  markdownlint:
+    runs-on: self-hosted
+    needs: setup
+    steps:
+      - uses: actions/checkout@v4
+      - name: Run markdownlint
+        run: make markdownlint
+
   basic_tests:
     runs-on: self-hosted
     needs: setup
diff --git a/Makefile b/Makefile
index 6d083dc..4992027 100644
--- a/Makefile
+++ b/Makefile
@@ -20,6 +20,7 @@ YAML_FILES := $(shell find ./ -name '*.yml')
 JSON_FILES := $(shell find ./ -name '*.json')
 VERILOG_FILES := $(shell find ./ -name '*.v')
 SVERILOG_FILES := $(shell find ./ -name '*.sv')
+MARKDOWN_FILES := $(shell find ./ -name '*.md')
 
 # Get File Names
 TCL_FILE_NAME := $(basename $(TCL_FILES))
@@ -28,8 +29,9 @@ YAML_FILE_NAME := $(basename $(YAML_FILES))
 JSON_FILE_NAME := $(basename $(JSON_FILES))
 VERILOG_FILE_NAME := $(basename $(VERILOG_FILES))
 SVERILOG_FILE_NAME := $(basename $(SVERILOG_FILES))
+MARKDOWN_FILE_NAME := $(basename $(MARKDOWN_FILES))
 
-.PHONY: all clean lint yamllint tclint pylint jsonlint veriloglint
+.PHONY: all clean lint yamllint tclint pylint jsonlint veriloglint markdownlint
 
 all: gen_pdk
 
@@ -96,13 +98,14 @@ pcb: gen_pdk
 open_pcb:
 	pcbnew out/${PROJECT}.final.kicad_pcb
 
-lint: yamllint tclint jsonlint veriloglint pylint
+lint: yamllint tclint jsonlint veriloglint pylint markdownlint
 
 yamllint: $(YAML_FILE_NAME)
 tclint: $(TCL_FILE_NAME)
 pylint: $(PY_FILE_NAME)
 jsonlint: $(JSON_FILE_NAME)
 veriloglint: $(VERILOG_FILE_NAME) $(SVERILOG_FILE_NAME)
+markdownlint: $(MARKDOWN_FILE_NAME)
 
 $(YAML_FILE_NAME): $(YAML_FILES)
 	yamllint --no-warnings $@.yml
@@ -122,6 +125,9 @@ $(VERILOG_FILE_NAME): $(VERILOG_FILES)
 $(SVERILOG_FILE_NAME): $(SVERILOG_FILES)
 	verible-verilog-lint $(VERIBLE_FLAGS) $@.sv
 
+$(MARKDOWN_FILE_NAME): $(MARKDOWN_FILES)
+	mdl $@.md
+
 clean:
 	rm -rf .setup
 	rm -rf out
diff --git a/Readme.md b/Readme.md
index a94cab8..d0bb31a 100644
--- a/Readme.md
+++ b/Readme.md
@@ -3,3 +3,5 @@
 [![CI status](https://github.com/TheMightyDuckOfDoom/liberty74/actions/workflows/ci.yml/badge.svg?branch=master)](https://github.com/TheMightyDuckOfDoom/liberty74/actions)
 
 Liberty74 is a fully open-source Verilog-to-PCB Flow.
+
+TODO: Documentation