Bender.yml

# Copyright 2024 Tobias Senti
# Solderpad Hardware License, Version 0.51, see LICENSE for details.
# SPDX-License-Identifier: SHL-0.51

package:
  name: liberty74
  authors:
    - "Tobias Senti"

sources:
  # Merge Cells
  - config/merge_cells/a22o.v
  - config/merge_cells/clkdiv.v
  - config/merge_cells/dff_dis_led.v
  - config/merge_cells/dff_en_led.v
  - config/merge_cells/dff_led.v
  - config/merge_cells/dffr_dis_led.v
  - config/merge_cells/dffr_en_led.v
  - config/merge_cells/dffr_led.v
  - config/merge_cells/mux2_and.v
  - config/merge_cells/mux2_ands.v
  - config/merge_cells/mux3.v
  - config/merge_cells/mux3s.v
  - config/merge_cells/mux4.v
  - config/merge_cells/reset_gen.v
  - config/merge_cells/sdff_dis_led.v
  - config/merge_cells/sdff_en_led.v
  - config/merge_cells/sdff_led.v
  - config/merge_cells/sdffr_dis_led.v
  - config/merge_cells/sdffr_en_led.v
  - config/merge_cells/sdffr_led.v

  # Simulation Models
  - target: not(SYNTH)
    files:
      - verilog_models/DS9808.sv
      - verilog_models/single_port_async_sram.sv
      - pdk/verilog/74avc.v
      - pdk/verilog/74hc.v
      - pdk/verilog/74lvc1g.v
      - pdk/verilog/74vhc.v
      - pdk/verilog/AM29.v
      - pdk/verilog/Analog.v
      - pdk/verilog/AS6C.v
      - pdk/verilog/DS9808.v
      - pdk/verilog/LCD.v
      - pdk/verilog/SST39SF.v
      - pdk/verilog/W24129A.v