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Schematic interchange format #284
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The history of EDIF is not so bright. Edif 2 0 0 had a very loose semantic, so it was possible to describe the same data in different ways (It's like a piece of LISP). Many EDA vendors provided at the time EDIF readers, almost none provided EDIF writers (they essentially wanted to lock -in their user base). My thougths on EDIF:
My thoughts for tool interoperability:
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Thanks for your perspective on EDIF. So let's forget it then. Maybe tool-to-tool conversions could be good enough for quite a while. So far, I think it would be sufficient to have |
So let's close this issue on EDIF. |
I am open to do something to interchange circuits with any other tool. May be we can have a discussion about the best approach to follow. I am almost sure we don't need EDIF. There is no "real" open source interchange format to date as open source EDA tools are very new, and proprietary EDA vendors are not interested to do anything on this. They'll do some marketing by flaunting interoperability, but in reality it's just fluff So we can as open source come up with a simple and documented format for this task. Perhaps we can fit the doc in 4/5 pages and not in 4 volumes!. I think it is a good time to consider this, as new (m) tools are coming into the arena and we probably want to avoid the (m - 1) x (m - 1) translators. |
That would be really great to have! For layout, we have GDS/OASIS/LEF/DEF (not perfect but existing), for netlists we have SPICE and Verilog (not perfect either, but existing), but for schematics and symbols there is a gap. |
Exactly. there are perfect interchange formats for layout and simulation , yet there is a gap for schematics. It is not easy, as in general to read a schematic you need to read and translate also the used components. |
I pretty well agree with what Stefan is saying; especially regarding not using EDIF. I am in the latter phases of debugging the port of my libraries from Viewdraw to xschem, so I am somewhat familiar with xschem schematic and symbol semantics (ditto for Viewdraw). As part of this port, I have a personal standard for describing hierarchical structures and connectivity that is yaml based. It somewhat follows the verilog standard for structural blocks. It basically allows for input, output, and ioports ports that are buses, sub-components, and concatenating sub-nets at circuit bus inputs. I'm also hoping to use it for some (for fun) simulators I am playing with (one in julia, one in C). I have iterated on the standard a few times, and it seems to be standing up and is relatively clean and simple (at least in my biased opinion?). This could be a reasonable starting point. If there is any interest, Steffan, could you suggest where to put it (I'm not familiar with Sourceforge, but could become so). I could put together an initial spec document (in markup?). A moderately complicated block that is part of a complex direct frequency synthesizer can be down-loaded from sine.yml. Ignore the functionality, but it has enough to give an idea of the current syntax (it doesn't have sub-circuit parameters in this example; I have other examples that do). I have used it as input for my toy simulators, so it has been exercised at least a little. |
@kwmartin I think github is the best choice. Create a project repository on github. This is what most of the people use I think. The example |
The google drive link to sine.yml is supposed to be accessible to everyone for download unless I got the permissions incorrect. I actually asked perplexity what was the preferred location to put a file for downloading and perplexity said google drive was preferred as github is primarily for project management not for general download. |
I understand, but this is what I get when I click he link to sine.yml. If the file is small you can simply put it here as text using the |
I think currently there is little need, but: if Xschem could read and write the
EDIF
format (https://en.wikipedia.org/wiki/EDIF) and other open-source tools (I am thinking of Qucs-S) could read and write this format too, then we could nicely bring schematics from one tool into the other, w/o the need to resort to SPICE-netlist only.@StefanSchippers What do you think? Is this something that you would eventually want to support? (Given that other tools also support this?)
I have to admit I have not looked into
EDIF
much, so I don't know if there would be any technical drawbacks when using this format to transfer schematics between tools.The text was updated successfully, but these errors were encountered: