CC1101 raspberry and arduino #23
Comments
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Hi, thank you to play around with my code, but may you please give me some more detailed information, how did you used it. Did you play with the examples, and which command did you use? Thx, |
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hello
here is a screen shot of my two codes running on both arduino and raspberry
also u can find attached my code
[cid:0a346bf7-6eb3-4129-9716-21ed1ffbde66]
…________________________________
De : SpaceTeddy <[email protected]>
Envoyé : mardi 14 août 2018 16:54:04
À : SpaceTeddy/CC1101
Cc : Ahmed BEN SOLTANE; Author
Objet : Re: [SpaceTeddy/CC1101] CC1101 raspberry and arduino (#23)
Hi, thank you to play around with my code, but may you please give me some more detailed information, how did you used it. Did you play with the examples, and which command did you use?
Any logs or screenshots would be helpful to analyse your issue.
Thx,
Chris
—
You are receiving this because you authored the thread.
Reply to this email directly, view it on GitHub<#23 (comment)>, or mute the thread<https://github.com/notifications/unsubscribe-auth/Am2z39UB9VlrUJw48np5JHjwISMSYyRqks5uQuSMgaJpZM4V8eyg>.
/*-------------------------------------------------------------------------------
' CC1100 Raspberry Pi Library
' ---------------------------
'
'
'
'
'
' module contains helper code from other people. Thx for that
'-----------------------------------------------------------------------------*/
#include "cc1100_raspi.h"
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <wiringPi.h>
#include <wiringPiSPI.h>
extern uint8_t cc1100_debug;
//-------------------[global default settings 868 Mhz]---------------------------------
static uint8_t cc1100_GFSK_1_2_kb[CFG_REGISTER] = {
0x07, // IOCFG2 GDO2 Output Pin Configuration
0x2E, // IOCFG1 GDO1 Output Pin Configuration
0x80, // IOCFG0 GDO0 Output Pin Configuration
0x07, // FIFOTHR RX FIFO and TX FIFO Thresholds
0x57, // SYNC1 Sync Word, High Byte
0x43, // SYNC0 Sync Word, Low Byte
0x3E, // PKTLEN Packet Length
0x0E, // PKTCTRL1 Packet Automation Control
0x45, // PKTCTRL0 Packet Automation Control
0xFF, // ADDR Device Address
0x00, // CHANNR Channel Number
0x08, // FSCTRL1 Frequency Synthesizer Control
0x00, // FSCTRL0 Frequency Synthesizer Control
0x21, // FREQ2 Frequency Control Word, High Byte
0x65, // FREQ1 Frequency Control Word, Middle Byte
0x6A, // FREQ0 Frequency Control Word, Low Byte
0xF5, // MDMCFG4 Modem Configuration
0x83, // MDMCFG3 Modem Configuration
0x13, // MDMCFG2 Modem Configuration
0xA0, // MDMCFG1 Modem Configuration
0xF8, // MDMCFG0 Modem Configuration
0x15, // DEVIATN Modem Deviation Setting
0x07, // MCSM2 Main Radio Control State Machine Configuration
0x0C, // MCSM1 Main Radio Control State Machine Configuration
0x18, // MCSM0 Main Radio Control State Machine Configuration
0x16, // FOCCFG Frequency Offset Compensation Configuration
0x6C, // BSCFG Bit Synchronization Configuration
0x03, // AGCCTRL2 AGC Control
0x40, // AGCCTRL1 AGC Control
0x91, // AGCCTRL0 AGC Control
0x02, // WOREVT1 High Byte Event0 Timeout
0x26, // WOREVT0 Low Byte Event0 Timeout
0x09, // WORCTRL Wake On Radio Control
0x56, // FREND1 Front End RX Configuration
0x17, // FREND0 Front End TX Configuration
0xA9, // FSCAL3 Frequency Synthesizer Calibration
0x0A, // FSCAL2 Frequency Synthesizer Calibration
0x00, // FSCAL1 Frequency Synthesizer Calibration
0x11, // FSCAL0 Frequency Synthesizer Calibration
0x41, // RCCTRL1 RC Oscillator Configuration
0x00, // RCCTRL0 RC Oscillator Configuration
0x59, // FSTEST Frequency Synthesizer Calibration Control,
0x7F, // PTEST Production Test
0x3F, // AGCTEST AGC Test
0x81, // TEST2 Various Test Settings
0x3F, // TEST1 Various Test Settings
0x0B // TEST0 Various Test Settings
};
static uint8_t cc1100_GFSK_38_4_kb[CFG_REGISTER] = {
0x07, // IOCFG2 GDO2 Output Pin Configuration
0x2E, // IOCFG1 GDO1 Output Pin Configuration
0x80, // IOCFG0 GDO0 Output Pin Configuration
0x07, // FIFOTHR RX FIFO and TX FIFO Thresholds
0x57, // SYNC1 Sync Word, High Byte
0x43, // SYNC0 Sync Word, Low Byte
0x3E, // PKTLEN Packet Length
0x0E, // PKTCTRL1 Packet Automation Control
0x45, // PKTCTRL0 Packet Automation Control
0xFF, // ADDR Device Address
0x00, // CHANNR Channel Number
0x06, // FSCTRL1 Frequency Synthesizer Control
0x00, // FSCTRL0 Frequency Synthesizer Control
0x21, // FREQ2 Frequency Control Word, High Byte
0x65, // FREQ1 Frequency Control Word, Middle Byte
0x6A, // FREQ0 Frequency Control Word, Low Byte
0xCA, // MDMCFG4 Modem Configuration
0x83, // MDMCFG3 Modem Configuration
0x13, // MDMCFG2 Modem Configuration
0xA0, // MDMCFG1 Modem Configuration
0xF8, // MDMCFG0 Modem Configuration
0x34, // DEVIATN Modem Deviation Setting
0x07, // MCSM2 Main Radio Control State Machine Configuration
0x0C, // MCSM1 Main Radio Control State Machine Configuration
0x18, // MCSM0 Main Radio Control State Machine Configuration
0x16, // FOCCFG Frequency Offset Compensation Configuration
0x6C, // BSCFG Bit Synchronization Configuration
0x43, // AGCCTRL2 AGC Control
0x40, // AGCCTRL1 AGC Control
0x91, // AGCCTRL0 AGC Control
0x02, // WOREVT1 High Byte Event0 Timeout
0x26, // WOREVT0 Low Byte Event0 Timeout
0x09, // WORCTRL Wake On Radio Control
0x56, // FREND1 Front End RX Configuration
0x17, // FREND0 Front End TX Configuration
0xA9, // FSCAL3 Frequency Synthesizer Calibration
0x0A, // FSCAL2 Frequency Synthesizer Calibration
0x00, // FSCAL1 Frequency Synthesizer Calibration
0x11, // FSCAL0 Frequency Synthesizer Calibration
0x41, // RCCTRL1 RC Oscillator Configuration
0x00, // RCCTRL0 RC Oscillator Configuration
0x59, // FSTEST Frequency Synthesizer Calibration Control,
0x7F, // PTEST Production Test
0x3F, // AGCTEST AGC Test
0x81, // TEST2 Various Test Settings
0x3F, // TEST1 Various Test Settings
0x0B // TEST0 Various Test Settings
};
static uint8_t cc1100_GFSK_100_kb[CFG_REGISTER] = {
0x07, // IOCFG2 GDO2 Output Pin Configuration
0x2E, // IOCFG1 GDO1 Output Pin Configuration
0x80, // IOCFG0 GDO0 Output Pin Configuration
0x07, // FIFOTHR RX FIFO and TX FIFO Thresholds
0x57, // SYNC1 Sync Word, High Byte
0x43, // SYNC0 Sync Word, Low Byte
0x3E, // PKTLEN Packet Length
0x0E, // PKTCTRL1 Packet Automation Control
0x45, // PKTCTRL0 Packet Automation Control
0xFF, // ADDR Device Address
0x00, // CHANNR Channel Number
0x08, // FSCTRL1 Frequency Synthesizer Control
0x00, // FSCTRL0 Frequency Synthesizer Control
0x21, // FREQ2 Frequency Control Word, High Byte
0x65, // FREQ1 Frequency Control Word, Middle Byte
0x6A, // FREQ0 Frequency Control Word, Low Byte
0x5B, // MDMCFG4 Modem Configuration
0xF8, // MDMCFG3 Modem Configuration
0x13, // MDMCFG2 Modem Configuration
0xA0, // MDMCFG1 Modem Configuration
0xF8, // MDMCFG0 Modem Configuration
0x47, // DEVIATN Modem Deviation Setting
0x07, // MCSM2 Main Radio Control State Machine Configuration
0x0C, // MCSM1 Main Radio Control State Machine Configuration
0x18, // MCSM0 Main Radio Control State Machine Configuration
0x1D, // FOCCFG Frequency Offset Compensation Configuration
0x1C, // BSCFG Bit Synchronization Configuration
0xC7, // AGCCTRL2 AGC Control
0x00, // AGCCTRL1 AGC Control
0xB2, // AGCCTRL0 AGC Control
0x02, // WOREVT1 High Byte Event0 Timeout
0x26, // WOREVT0 Low Byte Event0 Timeout
0x09, // WORCTRL Wake On Radio Control
0xB6, // FREND1 Front End RX Configuration
0x17, // FREND0 Front End TX Configuration
0xEA, // FSCAL3 Frequency Synthesizer Calibration
0x0A, // FSCAL2 Frequency Synthesizer Calibration
0x00, // FSCAL1 Frequency Synthesizer Calibration
0x11, // FSCAL0 Frequency Synthesizer Calibration
0x41, // RCCTRL1 RC Oscillator Configuration
0x00, // RCCTRL0 RC Oscillator Configuration
0x59, // FSTEST Frequency Synthesizer Calibration Control,
0x7F, // PTEST Production Test
0x3F, // AGCTEST AGC Test
0x81, // TEST2 Various Test Settings
0x3F, // TEST1 Various Test Settings
0x0B // TEST0 Various Test Settings
};
static uint8_t cc1100_MSK_250_kb[CFG_REGISTER] = {
0x07, // IOCFG2 GDO2 Output Pin Configuration
0x2E, // IOCFG1 GDO1 Output Pin Configuration
0x80, // IOCFG0 GDO0 Output Pin Configuration
0x07, // FIFOTHR RX FIFO and TX FIFO Thresholds
0x57, // SYNC1 Sync Word, High Byte
0x43, // SYNC0 Sync Word, Low Byte
0x3E, // PKTLEN Packet Length
0x0E, // PKTCTRL1 Packet Automation Control
0x45, // PKTCTRL0 Packet Automation Control
0xFF, // ADDR Device Address
0x00, // CHANNR Channel Number
0x0B, // FSCTRL1 Frequency Synthesizer Control
0x00, // FSCTRL0 Frequency Synthesizer Control
0x21, // FREQ2 Frequency Control Word, High Byte
0x65, // FREQ1 Frequency Control Word, Middle Byte
0x6A, // FREQ0 Frequency Control Word, Low Byte
0x2D, // MDMCFG4 Modem Configuration
0x3B, // MDMCFG3 Modem Configuration
0x73, // MDMCFG2 Modem Configuration
0xA0, // MDMCFG1 Modem Configuration
0xF8, // MDMCFG0 Modem Configuration
0x00, // DEVIATN Modem Deviation Setting
0x07, // MCSM2 Main Radio Control State Machine Configuration
0x0C, // MCSM1 Main Radio Control State Machine Configuration
0x18, // MCSM0 Main Radio Control State Machine Configuration
0x1D, // FOCCFG Frequency Offset Compensation Configuration
0x1C, // BSCFG Bit Synchronization Configuration
0xC7, // AGCCTRL2 AGC Control
0x00, // AGCCTRL1 AGC Control
0xB2, // AGCCTRL0 AGC Control
0x02, // WOREVT1 High Byte Event0 Timeout
0x26, // WOREVT0 Low Byte Event0 Timeout
0x09, // WORCTRL Wake On Radio Control
0xB6, // FREND1 Front End RX Configuration
0x17, // FREND0 Front End TX Configuration
0xEA, // FSCAL3 Frequency Synthesizer Calibration
0x0A, // FSCAL2 Frequency Synthesizer Calibration
0x00, // FSCAL1 Frequency Synthesizer Calibration
0x11, // FSCAL0 Frequency Synthesizer Calibration
0x41, // RCCTRL1 RC Oscillator Configuration
0x00, // RCCTRL0 RC Oscillator Configuration
0x59, // FSTEST Frequency Synthesizer Calibration Control,
0x7F, // PTEST Production Test
0x3F, // AGCTEST AGC Test
0x81, // TEST2 Various Test Settings
0x3F, // TEST1 Various Test Settings
0x0B // TEST0 Various Test Settings
};
static uint8_t cc1100_MSK_500_kb[CFG_REGISTER] = {
0x07, // IOCFG2 GDO2 Output Pin Configuration
0x2E, // IOCFG1 GDO1 Output Pin Configuration
0x80, // IOCFG0 GDO0 Output Pin Configuration
0x07, // FIFOTHR RX FIFO and TX FIFO Thresholds
0x57, // SYNC1 Sync Word, High Byte
0x43, // SYNC0 Sync Word, Low Byte
0x3E, // PKTLEN Packet Length
0x0E, // PKTCTRL1 Packet Automation Control
0x45, // PKTCTRL0 Packet Automation Control
0xFF, // ADDR Device Address
0x00, // CHANNR Channel Number
0x0C, // FSCTRL1 Frequency Synthesizer Control
0x00, // FSCTRL0 Frequency Synthesizer Control
0x21, // FREQ2 Frequency Control Word, High Byte
0x65, // FREQ1 Frequency Control Word, Middle Byte
0x6A, // FREQ0 Frequency Control Word, Low Byte
0x0E, // MDMCFG4 Modem Configuration
0x3B, // MDMCFG3 Modem Configuration
0x73, // MDMCFG2 Modem Configuration
0xA0, // MDMCFG1 Modem Configuration
0xF8, // MDMCFG0 Modem Configuration
0x00, // DEVIATN Modem Deviation Setting
0x07, // MCSM2 Main Radio Control State Machine Configuration
0x0C, // MCSM1 Main Radio Control State Machine Configuration
0x18, // MCSM0 Main Radio Control State Machine Configuration
0x1D, // FOCCFG Frequency Offset Compensation Configuration
0x1C, // BSCFG Bit Synchronization Configuration
0xC7, // AGCCTRL2 AGC Control
0x40, // AGCCTRL1 AGC Control
0xB2, // AGCCTRL0 AGC Control
0x02, // WOREVT1 High Byte Event0 Timeout
0x26, // WOREVT0 Low Byte Event0 Timeout
0x09, // WORCTRL Wake On Radio Control
0xB6, // FREND1 Front End RX Configuration
0x17, // FREND0 Front End TX Configuration
0xEA, // FSCAL3 Frequency Synthesizer Calibration
0x0A, // FSCAL2 Frequency Synthesizer Calibration
0x00, // FSCAL1 Frequency Synthesizer Calibration
0x19, // FSCAL0 Frequency Synthesizer Calibration
0x41, // RCCTRL1 RC Oscillator Configuration
0x00, // RCCTRL0 RC Oscillator Configuration
0x59, // FSTEST Frequency Synthesizer Calibration Control,
0x7F, // PTEST Production Test
0x3F, // AGCTEST AGC Test
0x81, // TEST2 Various Test Settings
0x3F, // TEST1 Various Test Settings
0x0B // TEST0 Various Test Settings
};
static uint8_t cc1100_OOK_4_8_kb[CFG_REGISTER] = {
0x06, // IOCFG2 GDO2 Output Pin Configuration
0x2E, // IOCFG1 GDO1 Output Pin Configuration
0x06, // IOCFG0 GDO0 Output Pin Configuration
0x47, // FIFOTHR RX FIFO and TX FIFO Thresholds
0x57, // SYNC1 Sync Word, High Byte
0x43, // SYNC0 Sync Word, Low Byte
0xFF, // PKTLEN Packet Length
0x04, // PKTCTRL1 Packet Automation Control
0x05, // PKTCTRL0 Packet Automation Control
0x00, // ADDR Device Address
0x00, // CHANNR Channel Number
0x06, // FSCTRL1 Frequency Synthesizer Control
0x00, // FSCTRL0 Frequency Synthesizer Control
0x21, // FREQ2 Frequency Control Word, High Byte
0x65, // FREQ1 Frequency Control Word, Middle Byte
0x6A, // FREQ0 Frequency Control Word, Low Byte
0x87, // MDMCFG4 Modem Configuration
0x83, // MDMCFG3 Modem Configuration
0x3B, // MDMCFG2 Modem Configuration
0x22, // MDMCFG1 Modem Configuration
0xF8, // MDMCFG0 Modem Configuration
0x15, // DEVIATN Modem Deviation Setting
0x07, // MCSM2 Main Radio Control State Machine Configuration
0x30, // MCSM1 Main Radio Control State Machine Configuration
0x18, // MCSM0 Main Radio Control State Machine Configuration
0x14, // FOCCFG Frequency Offset Compensation Configuration
0x6C, // BSCFG Bit Synchronization Configuration
0x07, // AGCCTRL2 AGC Control
0x00, // AGCCTRL1 AGC Control
0x92, // AGCCTRL0 AGC Control
0x87, // WOREVT1 High Byte Event0 Timeout
0x6B, // WOREVT0 Low Byte Event0 Timeout
0xFB, // WORCTRL Wake On Radio Control
0x56, // FREND1 Front End RX Configuration
0x17, // FREND0 Front End TX Configuration
0xE9, // FSCAL3 Frequency Synthesizer Calibration
0x2A, // FSCAL2 Frequency Synthesizer Calibration
0x00, // FSCAL1 Frequency Synthesizer Calibration
0x1F, // FSCAL0 Frequency Synthesizer Calibration
0x41, // RCCTRL1 RC Oscillator Configuration
0x00, // RCCTRL0 RC Oscillator Configuration
0x59, // FSTEST Frequency Synthesizer Calibration Control
0x7F, // PTEST Production Test
0x3F, // AGCTEST AGC Test
0x81, // TEST2 Various Test Settings
0x35, // TEST1 Various Test Settings
0x09, // TEST0 Various Test Settings
};
//Patable index: -30 -20- -15 -10 0 5 7 10 dBm
static uint8_t patable_power_315[8] = {0x17,0x1D,0x26,0x69,0x51,0x86,0xCC,0xC3};
static uint8_t patable_power_433[8] = {0x6C,0x1C,0x06,0x3A,0x51,0x85,0xC8,0xC0};
static uint8_t patable_power_868[8] = {0x03,0x17,0x1D,0x26,0x50,0x86,0xCD,0xC0};
static uint8_t patable_power_915[8] = {0x0B,0x1B,0x6D,0x67,0x50,0x85,0xC9,0xC1};
//static uint8_t patable_power_2430[8] = {0x44,0x84,0x46,0x55,0xC6,0x6E,0x9A,0xFE};
//----------------------------------[END]---------------------------------------
//-------------------------[CC1100 reset function]------------------------------
void CC1100::reset(void) // reset defined in cc1100 datasheet
{
digitalWrite(SS_PIN, LOW);
delayMicroseconds(10);
digitalWrite(SS_PIN, HIGH);
delayMicroseconds(40);
spi_write_strobe(SRES);
delay(1);
}
//-----------------------------[END]--------------------------------------------
//------------------------[set Power Down]--------------------------------------
void CC1100::powerdown(void)
{
sidle();
spi_write_strobe(SPWD); // CC1100 Power Down
}
//-----------------------------[end]--------------------------------------------
//---------------------------[WakeUp]-------------------------------------------
void CC1100::wakeup(void)
{
digitalWrite(SS_PIN, LOW);
delayMicroseconds(10);
digitalWrite(SS_PIN, HIGH);
delayMicroseconds(10);
receive(); // go to RX Mode
}
//-----------------------------[end]--------------------------------------------
//---------------------[CC1100 set debug level]---------------------------------
uint8_t CC1100::set_debug_level(uint8_t set_debug_level = 1) //default ON
{
debug_level = set_debug_level; //set debug level of CC1101 outputs
return debug_level;
}
//-----------------------------[end]--------------------------------------------
//---------------------[CC1100 get debug level]---------------------------------
uint8_t CC1100::get_debug_level(void)
{
return debug_level;
}
//-----------------------------[end]--------------------------------------------
//----------------------[CC1100 init functions]---------------------------------
uint8_t CC1100::begin(volatile uint8_t &My_addr)
{
uint8_t partnum, version;
extern int cc1100_freq_select, cc1100_mode_select, cc1100_channel_select;
pinMode(GDO0, INPUT); //setup AVR GPIO ports
pinMode(GDO2, INPUT);
set_debug_level(set_debug_level()); //set debug level of CC1101 outputs
if(debug_level > 0){
printf("Init CC1100...\r\n");
}
spi_begin(); //inits SPI Interface
reset(); //CC1100 init reset
spi_write_strobe(SFTX);delayMicroseconds(100);//flush the TX_fifo content
spi_write_strobe(SFRX);delayMicroseconds(100);//flush the RX_fifo content
partnum = spi_read_register(PARTNUM); //reads CC1100 partnumber
version = spi_read_register(VERSION); //reads CC1100 version number
//checks if valid Chip ID is found. Usualy 0x03 or 0x14. if not -> abort
if(version == 0x00 || version == 0xFF){
if(debug_level > 0){
printf("no CC11xx found!\r\n");
}
end(); //CC1100 Powerdown and disable SPI bus
return FALSE;
}
if(debug_level > 0){
printf("Partnumber: 0x%02X\r\n", partnum);
printf("Version : 0x%02X\r\n", version);
}
//set modulation mode
set_mode(cc1100_mode_select);
//set ISM band
set_ISM(cc1100_freq_select);
//set channel
set_channel(cc1100_channel_select);
//set output power amplifier
set_output_power_level(0); //set PA to 0dBm as default
//set my receiver address
set_myaddr(My_addr); //My_Addr from EEPROM to global variable
if(debug_level > 0){
printf("...done!\r\n");
}
receive(); //set CC1100 in receive mode
return TRUE;
}
//-------------------------------[end]------------------------------------------
//-----------------[finish's the CC1100 operation]------------------------------
void CC1100::end(void)
{
powerdown(); //power down CC1100
}
//-------------------------------[end]------------------------------------------
//-----------------------[show all CC1100 registers]----------------------------
void CC1100::show_register_settings(void)
{
if(debug_level > 0){
uint8_t config_reg_verify[CFG_REGISTER],Patable_verify[CFG_REGISTER];
spi_read_burst(READ_BURST,config_reg_verify,CFG_REGISTER); //reads all 47 config register from cc1100
spi_read_burst(PATABLE_BURST,Patable_verify,8); //reads output power settings from cc1100
//show_main_settings();
printf("Config Register:\r\n");
for(uint8_t i = 0 ; i < CFG_REGISTER; i++) //showes rx_buffer for debug
{
printf("0x%02X ", config_reg_verify[i]);
if(i==9 || i==19 || i==29 || i==39) //just for beautiful output style
{
printf("\r\n");
}
}
printf("\r\n");
printf("PaTable:\r\n");
for(uint8_t i = 0 ; i < 8; i++) //showes rx_buffer for debug
{
printf("0x%02X ", Patable_verify[i]);
}
printf("\r\n");
}
}
//-------------------------------[end]------------------------------------------
//--------------------------[show settings]-------------------------------------
void CC1100::show_main_settings(void)
{
extern volatile uint8_t My_addr;
extern int cc1100_mode_select, cc1100_freq_select, cc1100_channel_select;
printf("Mode: %d\r\n", cc1100_mode_select);
printf("Frequency: %d\r\n", cc1100_freq_select);
printf("Channel: %d\r\n", cc1100_channel_select);
printf("My_Addr: %d\r\n", My_addr);
}
//-------------------------------[end]------------------------------------------
//----------------------------[idle mode]---------------------------------------
uint8_t CC1100::sidle(void)
{
uint8_t marcstate;
spi_write_strobe(SIDLE); //sets to idle first. must be in
marcstate = 0xFF; //set unknown/dummy state value
while(marcstate != 0x01) //0x01 = sidle
{
marcstate = (spi_read_register(MARCSTATE) & 0x1F); //read out state of cc1100 to be sure in RX
//printf("marcstate_rx: 0x%02X\r", marcstate);
}
//Serial.println();
delayMicroseconds(100);
return TRUE;
}
//-------------------------------[end]------------------------------------------
//---------------------------[transmit mode]------------------------------------
uint8_t CC1100::transmit(void)
{
uint8_t marcstate;
sidle(); //sets to idle first.
spi_write_strobe(STX); //sends the data over air
marcstate = 0xFF; //set unknown/dummy state value
while(marcstate != 0x01) //0x01 = ILDE after sending data
{
marcstate = (spi_read_register(MARCSTATE) & 0x1F); //read out state of cc1100 to be sure in IDLE and TX is finished
//printf("marcstate_tx: 0x%02X ",marcstate);
}
//printf("\r\n");
delayMicroseconds(100);
return TRUE;
}
///-------------------------------[end]------------------------------------------
//---------------------------[receive mode]-------------------------------------
uint8_t CC1100::receive(void)
{
uint8_t marcstate;
sidle(); //sets to idle first.
spi_write_strobe(SRX); //writes receive strobe (receive mode)
marcstate = 0xFF; //set unknown/dummy state value
while(marcstate != 0x0D) //0x0D = RX
{
marcstate = (spi_read_register(MARCSTATE) & 0x1F); //read out state of cc1100 to be sure in RX
//printf("marcstate_rx: 0x%02X\r", marcstate);
}
//printf("\r\n");
delayMicroseconds(100);
return TRUE;
}
//-------------------------------[end]------------------------------------------
//------------[enables WOR Mode EVENT0 ~1890ms; rx_timeout ~235ms]--------------------
void CC1100::wor_enable()
{
/*
EVENT1 = WORCTRL[6:4] -> Datasheet page 88
EVENT0 = (750/Xtal)*(WOREVT1<<8+WOREVT0)*2^(5*WOR_RES) = (750/26Meg)*65407*2^(5*0) = 1.89s
(WOR_RES=0;RX_TIME=0) -> Datasheet page 80
i.E RX_TIMEOUT = EVENT0* (3.6038) *26/26Meg = 235.8ms
(WOR_RES=0;RX_TIME=1) -> Datasheet page 80
i.E.RX_TIMEOUT = EVENT0* (1.8029) *26/26Meg = 117.9ms
*/
sidle();
spi_write_register(MCSM0, 0x18); //FS Autocalibration
spi_write_register(MCSM2, 0x01); //MCSM2.RX_TIME = 1b
// configure EVENT0 time
spi_write_register(WOREVT1, 0xFF); //High byte Event0 timeout
spi_write_register(WOREVT0, 0x7F); //Low byte Event0 timeout
// configure EVENT1 time
spi_write_register(WORCTRL, 0x78); //WOR_RES=0b; tEVENT1=0111b=48d -> 48*(750/26MHz)= 1.385ms
spi_write_strobe(SFRX); //flush RX buffer
spi_write_strobe(SWORRST); //resets the WOR timer to the programmed Event 1
spi_write_strobe(SWOR); //put the radio in WOR mode when CSn is released
delayMicroseconds(100);
}
//-------------------------------[end]------------------------------------------
//------------------------[disable WOR Mode]-------------------------------------
void CC1100::wor_disable()
{
sidle(); //exit WOR Mode
spi_write_register(MCSM2, 0x07); //stay in RX. No RX timeout
}
//-------------------------------[end]------------------------------------------
//------------------------[resets WOR Timer]------------------------------------
void CC1100::wor_reset()
{
sidle(); //go to IDLE
spi_write_register(MCSM2, 0x01); //MCSM2.RX_TIME = 1b
spi_write_strobe(SFRX); //flush RX buffer
spi_write_strobe(SWORRST); //resets the WOR timer to the programmed Event 1
spi_write_strobe(SWOR); //put the radio in WOR mode when CSn is released
delayMicroseconds(100);
}
//-------------------------------[end]------------------------------------------
//-------------------------[tx_payload_burst]-----------------------------------
uint8_t CC1100::tx_payload_burst(uint8_t my_addr, uint8_t rx_addr,
uint8_t *txbuffer, uint8_t length)
{
txbuffer[0] = length-1;
txbuffer[1] = rx_addr;
txbuffer[2] = my_addr;
spi_write_burst(TXFIFO_BURST,txbuffer,length); //writes TX_Buffer +1 because of pktlen must be also transfered
if(debug_level > 0){
printf("TX_FIFO: ");
for(uint8_t i = 0 ; i < length; i++) //TX_fifo debug out
{
printf("0x%02X ", txbuffer[i]);
}
printf("\r\n");
}
return TRUE;
}
//-------------------------------[end]------------------------------------------
//------------------[rx_payload_burst - package received]-----------------------
uint8_t CC1100::rx_payload_burst(uint8_t rxbuffer[], uint8_t &pktlen)
{
uint8_t bytes_in_RXFIFO = 0;
uint8_t res = 0;
bytes_in_RXFIFO = spi_read_register(RXBYTES); //reads the number of bytes in RXFIFO
if((bytes_in_RXFIFO & 0x7F) && !(bytes_in_RXFIFO & 0x80)) //if bytes in buffer and no RX Overflow
{
spi_read_burst(RXFIFO_BURST, rxbuffer, bytes_in_RXFIFO);
pktlen = rxbuffer[0];
res = TRUE;
}
else
{
if(debug_level > 0){
printf("no bytes in RX buffer or RX Overflow!: ");printf("0x%02X \r\n", bytes_in_RXFIFO);
}
sidle(); //set to IDLE
spi_write_strobe(SFRX);delayMicroseconds(100); //flush RX Buffer
receive(); //set to receive mode
res = FALSE;
}
return res;
}
//-------------------------------[end]------------------------------------------
//---------------------------[sent packet]--------------------------------------
uint8_t CC1100::sent_packet(uint8_t my_addr, uint8_t rx_addr, uint8_t *txbuffer,
uint8_t pktlen, uint8_t tx_retries)
{
uint8_t pktlen_ack, rssi, lqi; //default package len for ACK
uint8_t rxbuffer[FIFOBUFFER];
uint8_t tx_retries_count = 0;
uint8_t from_sender;
uint16_t ackWaitCounter = 0;
if(pktlen > (FIFOBUFFER - 1))
{
printf("ERROR: package size overflow\r\n");
return FALSE;
}
do //sent package out with retries
{
tx_payload_burst(my_addr, rx_addr, txbuffer, pktlen); //loads the data in cc1100 buffer
transmit(); //sents data over air
receive(); //receive mode
if(rx_addr == BROADCAST_ADDRESS){ //no wait acknowledge if sent to broadcast address or tx_retries = 0
return TRUE; //successful sent to BROADCAST_ADDRESS
}
while (ackWaitCounter < ACK_TIMEOUT ) //wait for an acknowledge
{
if (packet_available() == TRUE) //if RF package received check package acknowge
{
from_sender = rx_addr; //the original message sender address
rx_fifo_erase(rxbuffer); //erase RX software buffer
rx_payload_burst(rxbuffer, pktlen_ack); //reads package in buffer
check_acknolage(rxbuffer, pktlen_ack, from_sender, my_addr); //check if received message is an acknowledge from client
return TRUE; //package successfully sent
}
else{
ackWaitCounter++; //increment ACK wait counter
delay(1); //delay to give receiver time
}
}
ackWaitCounter = 0; //resets the ACK_Timeout
tx_retries_count++; //increase tx retry counter
if(debug_level > 0){ //debug output messages
printf(" #:");
printf("0x%02X \r\n", tx_retries_count);
}
}while(tx_retries_count <= tx_retries); //while count of retries is reaches
return FALSE; //sent failed. too many retries
}
//-------------------------------[end]------------------------------------------
//--------------------------[sent ACKNOLAGE]------------------------------------
void CC1100::sent_acknolage(uint8_t my_addr, uint8_t tx_addr)
{
uint8_t pktlen = 0x06; //complete Pktlen for ACK packet
uint8_t tx_buffer[0x06]; //tx buffer array init
tx_buffer[3] = 'A'; tx_buffer[4] = 'c'; tx_buffer[5] = 'k'; //fill buffer with ACK Payload
tx_payload_burst(my_addr, tx_addr, tx_buffer, pktlen); //load payload to CC1100
transmit(); //sent package over the air
receive(); //set CC1100 in receive mode
if(debug_level > 0){ //debut output
printf("Ack_sent!\r\n");
}
}
//-------------------------------[end]------------------------------------------
//----------------------[check if Packet is received]---------------------------
uint8_t CC1100::packet_available()
{
if(digitalRead(GDO2) == TRUE) //if RF package received
{
if(spi_read_register(IOCFG2) == 0x06) //if sync word detect mode is used
{
while(digitalRead(GDO2) == TRUE){ //wait till sync word is fully received
printf("!\r\n");
} //for sync word receive
}
if(debug_level > 0){
//printf("Pkt->:\r\n");
}
return TRUE;
}
return FALSE;
}
//-------------------------------[end]------------------------------------------
//------------------[check Payload for ACK or Data]-----------------------------
uint8_t CC1100::get_payload(uint8_t rxbuffer[], uint8_t &pktlen, uint8_t &my_addr,
uint8_t &sender, int8_t &rssi_dbm, uint8_t &lqi)
{
uint8_t crc;
rx_fifo_erase(rxbuffer); //delete rx_fifo bufffer
if(rx_payload_burst(rxbuffer, pktlen) == FALSE) //read package in buffer
{
rx_fifo_erase(rxbuffer); //delete rx_fifo bufffer
return FALSE; //exit
}
else
{
my_addr = rxbuffer[1]; //set receiver address to my_addr
sender = rxbuffer[2];
if(check_acknolage(rxbuffer, pktlen, sender, my_addr) == TRUE) //acknowlage received?
{
rx_fifo_erase(rxbuffer); //delete rx_fifo bufffer
return FALSE; //Ack received -> finished
}
else //real data, and sent acknowladge
{
rssi_dbm = rssi_convert(rxbuffer[pktlen + 1]); //converts receiver strength to dBm
lqi = lqi_convert(rxbuffer[pktlen + 2]); //get rf quialtiy indicator
crc = check_crc(lqi); //get packet CRC
if(debug_level > 0){ //debug output messages
if(rxbuffer[1] == BROADCAST_ADDRESS) //if my receiver address is BROADCAST_ADDRESS
{
printf("BROADCAST message\r\n");
}
printf("RX_FIFO:");
for(uint8_t i = 0 ; i < pktlen + 1; i++) //showes rx_buffer for debug
{
printf("0x%02X ", rxbuffer[i]);
}
printf("| 0x%02X 0x%02X |", rxbuffer[pktlen+1], rxbuffer[pktlen+2]);
printf("\r\n");
printf("RSSI:%d ", rssi_dbm);
printf("LQI:");printf("0x%02X ", lqi);
printf("CRC:");printf("0x%02X ", crc);
printf("\r\n");
}
my_addr = rxbuffer[1]; //set receiver address to my_addr
sender = rxbuffer[2]; //set from_sender address
if(my_addr != BROADCAST_ADDRESS) //send only ack if no BROADCAST_ADDRESS
{
sent_acknolage(my_addr, sender); //sending acknolage to sender!
}
return TRUE;
}
return FALSE;
}
}
//-------------------------------[end]------------------------------------------
//-------------------------[check ACKNOLAGE]------------------------------------
uint8_t CC1100::check_acknolage(uint8_t *rxbuffer, uint8_t pktlen, uint8_t sender, uint8_t my_addr)
{
int8_t rssi_dbm;
uint8_t crc, lqi;
if((pktlen == 0x05 && \
rxbuffer[1] == my_addr || rxbuffer[1] == BROADCAST_ADDRESS) && \
rxbuffer[2] == sender && \
rxbuffer[3] == 'A' && rxbuffer[4] == 'c' && rxbuffer[5] == 'k') //acknolage received!
{
if(rxbuffer[1] == BROADCAST_ADDRESS){ //if receiver address BROADCAST_ADDRESS skip acknolage
if(debug_level > 0){
printf("BROADCAST ACK\r\n");
}
return FALSE;
}
rssi_dbm = rssi_convert(rxbuffer[pktlen + 1]);
lqi = lqi_convert(rxbuffer[pktlen + 2]);
crc = check_crc(lqi);
if(debug_level > 0){
printf("ACK! ");
printf("RSSI:%i ",rssi_dbm);
printf("LQI:0x%02X ",lqi);
printf("CRC:0x%02X\r\n",crc);
}
return TRUE;
}
return FALSE;
}
//-------------------------------[end]------------------------------------------
//------------[check if Packet is received within defined time in ms]-----------
uint8_t CC1100::wait_for_packet(uint8_t milliseconds)
{
for(uint8_t i = 0; i < milliseconds; i++)
{
delay(1); //delay till system has data available
if (packet_available())
{
return TRUE;
}
}
return FALSE;
}
//-------------------------------[end]------------------------------------------
//--------------------------[tx_fifo_erase]-------------------------------------
void CC1100::tx_fifo_erase(uint8_t *txbuffer)
{
memset(txbuffer, 0, sizeof(FIFOBUFFER)); //erased the TX_fifo array content to "0"
}
//-------------------------------[end]------------------------------------------
//--------------------------[rx_fifo_erase]-------------------------------------
void CC1100::rx_fifo_erase(uint8_t *rxbuffer)
{
memset(rxbuffer, 0, sizeof(FIFOBUFFER)); //erased the RX_fifo array content to "0"
}
//-------------------------------[end]------------------------------------------
//------------------------[set CC1100 address]----------------------------------
void CC1100::set_myaddr(uint8_t addr)
{
spi_write_register(ADDR,addr); //stores MyAddr in the CC1100
}
//-------------------------------[end]------------------------------------------
//---------------------------[set channel]--------------------------------------
void CC1100::set_channel(uint8_t channel)
{
spi_write_register(CHANNR,channel); //stores the new channel # in the CC1100
return;
}
//-------------------------------[end]------------------------------------------
//-[set modulation mode 1 = GFSK_1_2_kb; 2 = GFSK_38_4_kb; 3 = GFSK_100_kb; 4 = MSK_250_kb; 5 = MSK_500_kb; 6 = OOK_4_8_kb]-
void CC1100::set_mode(uint8_t mode)
{
switch (mode)
{
case 0x01:
spi_write_burst(WRITE_BURST,cc1100_GFSK_1_2_kb,CFG_REGISTER);
break;
case 0x02:
spi_write_burst(WRITE_BURST,cc1100_GFSK_38_4_kb,CFG_REGISTER);
break;
case 0x03:
spi_write_burst(WRITE_BURST,cc1100_GFSK_100_kb,CFG_REGISTER);
break;
case 0x04:
spi_write_burst(WRITE_BURST,cc1100_MSK_250_kb,CFG_REGISTER);
break;
case 0x05:
spi_write_burst(WRITE_BURST,cc1100_MSK_500_kb,CFG_REGISTER);
break;
case 0x06:
spi_write_burst(WRITE_BURST,cc1100_OOK_4_8_kb,CFG_REGISTER);
break;
default:
spi_write_burst(WRITE_BURST,cc1100_GFSK_100_kb,CFG_REGISTER);
break;
}
return;
}
//------------------------------------------end]-----------------------------------
//---------[set ISM Band 1=315MHz; 2=433MHz; 3=868MHz; 4=915MHz]----------------
void CC1100::set_ISM(uint8_t ism_freq)
{
uint8_t freq2, freq1, freq0;
switch (ism_freq) //loads the RF freq which is defined in cc1100_freq_select
{
case 0x01: //315MHz
freq2=0x0C;
freq1=0x1D;
freq0=0x89;
spi_write_burst(PATABLE_BURST,patable_power_315,8);
break;
case 0x02: //433.92MHz
freq2=0x10;
freq1=0xB0;
freq0=0x71;
spi_write_burst(PATABLE_BURST,patable_power_433,8);
break;
case 0x03: //868.3MHz
freq2=0x21;
freq1=0x65;
freq0=0x6A;
spi_write_burst(PATABLE_BURST,patable_power_868,8);
break;
case 0x04: //915MHz
freq2=0x23;
freq1=0x31;
freq0=0x3B;
spi_write_burst(PATABLE_BURST,patable_power_915,8);
break;
/*
case 0x05: //2430MHz
freq2=0x5D;
freq1=0x76;
freq0=0x27;
spi_write_burst(PATABLE_BURST,patable_power_2430,8);
break;
*/
default: //default is 868.3MHz
freq2=0x21;
freq1=0x65;
freq0=0x6A;
spi_write_burst(PATABLE_BURST,patable_power_868,8); //sets up output power ramp register
break;
}
spi_write_register(FREQ2,freq2); //stores the new freq setting for defined ISM band
spi_write_register(FREQ1,freq1);
spi_write_register(FREQ0,freq0);
return;
}
//-------------------------------[end]------------------------------------------
//--------------------------[set frequency]-------------------------------------
void CC1100::set_patable(uint8_t *patable_arr)
{
spi_write_burst(PATABLE_BURST,patable_arr,8); //writes output power settings to cc1100 "104us"
}
//-------------------------------[end]------------------------------------------
//-------------------------[set output power]-----------------------------------
void CC1100::set_output_power_level(int8_t dBm)
{
uint8_t pa = 0xC0;
if (dBm <= -30) pa = 0x00;
else if (dBm <= -20) pa = 0x01;
else if (dBm <= -15) pa = 0x02;
else if (dBm <= -10) pa = 0x03;
else if (dBm <= 0) pa = 0x04;
else if (dBm <= 5) pa = 0x05;
else if (dBm <= 7) pa = 0x06;
else if (dBm <= 10) pa = 0x07;
spi_write_register(FREND0,pa);
}
//-------------------------------[end]------------------------------------------
//-------[set Modulation type 2-FSK=0; GFSK=1; ASK/OOK=3; 4-FSK=4; MSK=7]------
void CC1100::set_modulation_type(uint8_t cfg)
{
uint8_t data;
data = spi_read_register(MDMCFG2);
data = (data & 0x8F) | (((cfg) << 4) & 0x70);
spi_write_register(MDMCFG2, data);
//printf("MDMCFG2: 0x%02X\n", data);
}
//-------------------------------[end]-----------------------------------------
//------------------------[set preamble Len]-----------------------------------
void CC1100::set_preamble_len(uint8_t cfg)
{
uint8_t data;
data = spi_read_register(MDMCFG1);
data = (data & 0x8F) | (((cfg) << 4) & 0x70);
spi_write_register(MDMCFG1, data);
//printf("MDMCFG2: 0x%02X\n", data);
}
//-------------------------------[end]-----------------------------------------
//-------------------[set modem datarate and deviant]--------------------------
void CC1100::set_datarate(uint8_t mdmcfg4, uint8_t mdmcfg3, uint8_t deviant)
{
spi_write_register(MDMCFG4, mdmcfg4);
spi_write_register(MDMCFG3, mdmcfg3);
spi_write_register(DEVIATN, deviant);
}
//-------------------------------[end]-----------------------------------------
//----------------------[set sync mode no sync=0;]-----------------------------
void CC1100::set_sync_mode(uint8_t cfg) // 0=no sync word; 1,2 = 16bit sync word, 3= 32bit sync word
{
uint8_t data;
data = spi_read_register(MDMCFG2);
data = (data & 0xF8) | (cfg & 0x07);
spi_write_register(MDMCFG2, data);
//printf("MDMCFG2: 0x%02X\n", data);
}
//-------------------------------[end]-----------------------------------------
//---------------[set FEC ON=TRUE; OFF=FALSE]----------------------------------
void CC1100::set_fec(uint8_t cfg)
{
uint8_t data;
data = spi_read_register(MDMCFG1);
data = (data & 0x7F) | (((cfg) << 7) & 0x80);
spi_write_register(MDMCFG1, data);
printf("MDMCFG1: 0x%02X\n", data);
}
//-------------------------------[end]------------------------------------------
//---------------[set data_whitening ON=TRUE; OFF=FALSE]------------------------
void CC1100::set_data_whitening(uint8_t cfg)
{
uint8_t data;
data = spi_read_register(PKTCTRL0);
data = (data & 0xBF) | (((cfg) << 6) & 0x40);
spi_write_register(PKTCTRL0, data);
//printf("PKTCTRL0: 0x%02X\n", data);
}
//-------------------------------[end]-----------------------------------------
//------------[set manchester encoding ON=TRUE; OFF=FALSE]---------------------
void CC1100::set_manchaster_encoding(uint8_t cfg)
{
uint8_t data;
data = spi_read_register(MDMCFG2);
data = (data & 0xF7) | (((cfg) << 3) & 0x08);
spi_write_register(MDMCFG2, data);
//printf("MDMCFG2: 0x%02X\n", data);
}
//-------------------------------[end]------------------------------------------
//--------------------------[rssi_convert]--------------------------------------
int8_t CC1100::rssi_convert(uint8_t Rssi_hex)
{
int8_t rssi_dbm;
int16_t Rssi_dec;
Rssi_dec = Rssi_hex; //convert unsigned to signed
if(Rssi_dec >= 128){
rssi_dbm=((Rssi_dec-256)/2)-RSSI_OFFSET_868MHZ;
}
else{
if(Rssi_dec<128){
rssi_dbm=((Rssi_dec)/2)-RSSI_OFFSET_868MHZ;
}
}
return rssi_dbm;
}
//-------------------------------[end]------------------------------------------
//----------------------------[lqi convert]-------------------------------------
uint8_t CC1100::lqi_convert(uint8_t lqi)
{
return (lqi & 0x7F);
}
//-------------------------------[end]------------------------------------------
//----------------------------[check crc]---------------------------------------
uint8_t CC1100::check_crc(uint8_t lqi)
{
return (lqi & 0x80);
}
//-------------------------------[end]------------------------------------------
/*
//----------------------------[get temp]----------------------------------------
uint8_t CC1100::get_temp(uint8_t *ptemp_Arr)
{
const uint8_t num_samples = 8;
uint16_t adc_result = 0;
uint32_t temperature = 0;
sidle(); //sets CC1100 into IDLE
spi_write_register(PTEST,0xBF); //enable temp sensor
delay(50); //wait a bit
for(uint8_t i=0;i<num_samples;i++) //sampling analog temperature value
{
adc_result += analogRead(GDO0);
delay(1);
}
adc_result = adc_result / num_samples;
//Serial.println(adc_result);
temperature = (adc_result * CC1100_TEMP_ADC_MV) / CC1100_TEMP_CELS_CO;
ptemp_Arr[0] = temperature / 10; //cut last digit
ptemp_Arr[1] = temperature % 10; //isolate last digit
if(debug_level > 0){
Serial.print(F("Temp:"));Serial.print(ptemp_Arr[0]);Serial.print(F("."));Serial.println(ptemp_Arr[1]);
}
spi_write_register(PTEST,0x7F); //writes 0x7F back to PTest (app. note)
receive();
return (*ptemp_Arr);
}
*/
//-------------------------------[end]------------------------------------------
//|==================== SPI Initialisation for CC1100 =========================|
void CC1100::spi_begin(void)
{
int x = 0;
//printf ("init SPI bus... ");
if ((x = wiringPiSPISetup (0, 8000000)) < 0) //4MHz SPI speed
{
if(debug_level > 0){
printf ("ERROR: wiringPiSPISetup failed!\r\n");
}
}
else{
//printf ("wiringSPI is up\r\n");
}
}
//------------------[write register]--------------------------------
void CC1100::spi_write_register(uint8_t spi_instr, uint8_t value)
{
uint8_t tbuf[2] = {0};
tbuf[0] = spi_instr | WRITE_SINGLE_BYTE;
tbuf[1] = value;
uint8_t len = 2;
wiringPiSPIDataRW (0, tbuf, len) ;
return;
}
//|============================ Ein Register lesen ============================|
uint8_t CC1100::spi_read_register(uint8_t spi_instr)
{
uint8_t value;
uint8_t rbuf[2] = {0};
rbuf[0] = spi_instr | READ_SINGLE_BYTE;
uint8_t len = 2;
wiringPiSPIDataRW (0, rbuf, len) ;
value = rbuf[1];
//printf("SPI_arr_0: 0x%02X\n", rbuf[0]);
//printf("SPI_arr_1: 0x%02X\n", rbuf[1]);
return value;
}
//|========================= ein Kommando schreiben ========================|
void CC1100::spi_write_strobe(uint8_t spi_instr)
{
uint8_t tbuf[1] = {0};
tbuf[0] = spi_instr;
//printf("SPI_data: 0x%02X\n", tbuf[0]);
wiringPiSPIDataRW (0, tbuf, 1) ;
}
//|======= Mehrere hintereinanderliegende Register auf einmal lesen =======|
void CC1100::spi_read_burst(uint8_t spi_instr, uint8_t *pArr, uint8_t len)
{
uint8_t rbuf[len + 1];
rbuf[0] = spi_instr | READ_BURST;
wiringPiSPIDataRW (0, rbuf, len + 1) ;
for (uint8_t i=0; i<len ;i++ )
{
pArr[i] = rbuf[i+1];
//printf("SPI_arr_read: 0x%02X\n", pArr[i]);
}
}
//|======= Mehrere hintereinanderliegende Register auf einmal schreiben =======|
void CC1100::spi_write_burst(uint8_t spi_instr, uint8_t *pArr, uint8_t len)
{
uint8_t tbuf[len + 1];
tbuf[0] = spi_instr | WRITE_BURST;
for (uint8_t i=0; i<len ;i++ )
{
tbuf[i+1] = pArr[i];
//printf("SPI_arr_write: 0x%02X\n", tbuf[i+1]);
}
wiringPiSPIDataRW (0, tbuf, len + 1) ;
}
//|================================= END =======================================|
#ifndef cc1100_H
#define cc1100_H
#include <stdint.h>
/*----------------------------------[standard]--------------------------------*/
#define TRUE 1
#define FALSE 0
//**************************** pins ******************************************//
#define SS_PIN 10
#define GDO2 6
#define GDO0 99
/*----------------------[CC1100 - misc]---------------------------------------*/
#define CRYSTAL_FREQUENCY 26000000
#define CFG_REGISTER 0x2F //47 registers
#define FIFOBUFFER 0x42 //size of Fifo Buffer +2 for rssi and lqi
#define RSSI_OFFSET_868MHZ 0x4E //dec = 74
#define TX_RETRIES_MAX 0x05 //tx_retries_max
#define ACK_TIMEOUT 250 //ACK timeout in ms
#define CC1100_COMPARE_REGISTER 0x00 //register compare 0=no compare 1=compare
#define BROADCAST_ADDRESS 0x00 //broadcast address
#define CC1100_FREQ_315MHZ 0x01
#define CC1100_FREQ_434MHZ 0x02
#define CC1100_FREQ_868MHZ 0x03
#define CC1100_FREQ_915MHZ 0x04
//#define CC1100_FREQ_2430MHZ 0x05
#define CC1100_TEMP_ADC_MV 3.225 //3.3V/1023 . mV pro digit
#define CC1100_TEMP_CELS_CO 2.47 //Temperature coefficient 2.47mV per Grad Celsius
/*---------------------------[CC1100 - R/W offsets]---------------------------*/
#define WRITE_SINGLE_BYTE 0x00
#define WRITE_BURST 0x40
#define READ_SINGLE_BYTE 0x80
#define READ_BURST 0xC0
/*---------------------------[END R/W offsets]--------------------------------*/
/*------------------------[CC1100 - FIFO commands]----------------------------*/
#define TXFIFO_BURST 0x7F //write burst only
#define TXFIFO_SINGLE_BYTE 0x3F //write single only
#define RXFIFO_BURST 0xFF //read burst only
#define RXFIFO_SINGLE_BYTE 0xBF //read single only
#define PATABLE_BURST 0x7E //power control read/write
#define PATABLE_SINGLE_BYTE 0xFE //power control read/write
/*---------------------------[END FIFO commands]------------------------------*/
/*----------------------[CC1100 - config register]----------------------------*/
#define IOCFG2 0x00 // GDO2 output pin configuration
#define IOCFG1 0x01 // GDO1 output pin configuration
#define IOCFG0 0x02 // GDO0 output pin configuration
#define FIFOTHR 0x03 // RX FIFO and TX FIFO thresholds
#define SYNC1 0x04 // Sync word, high byte
#define SYNC0 0x05 // Sync word, low byte
#define PKTLEN 0x06 // Packet length
#define PKTCTRL1 0x07 // Packet automation control
#define PKTCTRL0 0x08 // Packet automation control
#define ADDR 0x09 // Device address
#define CHANNR 0x0A // Channel number
#define FSCTRL1 0x0B // Frequency synthesizer control
#define FSCTRL0 0x0C // Frequency synthesizer control
#define FREQ2 0x0D // Frequency control word, high byte
#define FREQ1 0x0E // Frequency control word, middle byte
#define FREQ0 0x0F // Frequency control word, low byte
#define MDMCFG4 0x10 // Modem configuration
#define MDMCFG3 0x11 // Modem configuration
#define MDMCFG2 0x12 // Modem configuration
#define MDMCFG1 0x13 // Modem configuration
#define MDMCFG0 0x14 // Modem configuration
#define DEVIATN 0x15 // Modem deviation setting
#define MCSM2 0x16 // Main Radio Cntrl State Machine config
#define MCSM1 0x17 // Main Radio Cntrl State Machine config
#define MCSM0 0x18 // Main Radio Cntrl State Machine config
#define FOCCFG 0x19 // Frequency Offset Compensation config
#define BSCFG 0x1A // Bit Synchronization configuration
#define AGCCTRL2 0x1B // AGC control
#define AGCCTRL1 0x1C // AGC control
#define AGCCTRL0 0x1D // AGC control
#define WOREVT1 0x1E // High byte Event 0 timeout
#define WOREVT0 0x1F // Low byte Event 0 timeout
#define WORCTRL 0x20 // Wake On Radio control
#define FREND1 0x21 // Front end RX configuration
#define FREND0 0x22 // Front end TX configuration
#define FSCAL3 0x23 // Frequency synthesizer calibration
#define FSCAL2 0x24 // Frequency synthesizer calibration
#define FSCAL1 0x25 // Frequency synthesizer calibration
#define FSCAL0 0x26 // Frequency synthesizer calibration
#define RCCTRL1 0x27 // RC oscillator configuration
#define RCCTRL0 0x28 // RC oscillator configuration
#define FSTEST 0x29 // Frequency synthesizer cal control
#define PTEST 0x2A // Production test
#define AGCTEST 0x2B // AGC test
#define TEST2 0x2C // Various test settings
#define TEST1 0x2D // Various test settings
#define TEST0 0x2E // Various test settings
/*-------------------------[END config register]------------------------------*/
/*------------------------[CC1100-command strobes]----------------------------*/
#define SRES 0x30 // Reset chip
#define SFSTXON 0x31 // Enable/calibrate freq synthesizer
#define SXOFF 0x32 // Turn off crystal oscillator.
#define SCAL 0x33 // Calibrate freq synthesizer & disable
#define SRX 0x34 // Enable RX.
#define STX 0x35 // Enable TX.
#define SIDLE 0x36 // Exit RX / TX
#define SAFC 0x37 // AFC adjustment of freq synthesizer
#define SWOR 0x38 // Start automatic RX polling sequence
#define SPWD 0x39 // Enter pwr down mode when CSn goes hi
#define SFRX 0x3A // Flush the RX FIFO buffer.
#define SFTX 0x3B // Flush the TX FIFO buffer.
#define SWORRST 0x3C // Reset real time clock.
#define SNOP 0x3D // No operation.
/*-------------------------[END command strobes]------------------------------*/
/*----------------------[CC1100 - status register]----------------------------*/
#define PARTNUM 0xF0 // Part number
#define VERSION 0xF1 // Current version number
#define FREQEST 0xF2 // Frequency offset estimate
#define LQI 0xF3 // Demodulator estimate for link quality
#define RSSI 0xF4 // Received signal strength indication
#define MARCSTATE 0xF5 // Control state machine state
#define WORTIME1 0xF6 // High byte of WOR timer
#define WORTIME0 0xF7 // Low byte of WOR timer
#define PKTSTATUS 0xF8 // Current GDOx status and packet status
#define VCO_VC_DAC 0xF9 // Current setting from PLL cal module
#define TXBYTES 0xFA // Underflow and # of bytes in TXFIFO
#define RXBYTES 0xFB // Overflow and # of bytes in RXFIFO
#define RCCTRL1_STATUS 0xFC //Last RC Oscillator Calibration Result
#define RCCTRL0_STATUS 0xFD //Last RC Oscillator Calibration Result
//--------------------------[END status register]-------------------------------
class CC1100
{
private:
void spi_begin(void);
void spi_end(void);
uint8_t spi_putc(uint8_t data);
public:
uint8_t debug_level;
uint8_t set_debug_level(uint8_t set_debug_level);
uint8_t get_debug_level(void);
uint8_t begin(volatile uint8_t &My_addr);
void end(void);
void spi_write_strobe(uint8_t spi_instr);
void spi_write_register(uint8_t spi_instr, uint8_t value);
void spi_write_burst(uint8_t spi_instr, uint8_t *pArr, uint8_t length);
void spi_read_burst(uint8_t spi_instr, uint8_t *pArr, uint8_t length);
uint8_t spi_read_register(uint8_t spi_instr);
uint8_t spi_read_status(uint8_t spi_instr);
void reset(void);
void wakeup(void);
void powerdown(void);
void wor_enable(void);
void wor_disable(void);
void wor_reset(void);
uint8_t sidle(void);
uint8_t transmit(void);
uint8_t receive(void);
void show_register_settings(void);
void show_main_settings(void);
uint8_t packet_available();
uint8_t wait_for_packet(uint8_t milliseconds);
uint8_t get_payload(uint8_t rxbuffer[], uint8_t &pktlen_rx,uint8_t &my_addr,
uint8_t &sender, int8_t &rssi_dbm, uint8_t &lqi);
uint8_t tx_payload_burst(uint8_t my_addr, uint8_t rx_addr, uint8_t *txbuffer, uint8_t length);
uint8_t rx_payload_burst(uint8_t rxbuffer[], uint8_t &pktlen);
void rx_fifo_erase(uint8_t *rxbuffer);
void tx_fifo_erase(uint8_t *txbuffer);
uint8_t sent_packet(uint8_t my_addr, uint8_t rx_addr, uint8_t *txbuffer, uint8_t pktlen, uint8_t tx_retries);
void sent_acknolage(uint8_t my_addr, uint8_t tx_addr);
uint8_t check_acknolage(uint8_t *rxbuffer, uint8_t pktlen, uint8_t sender, uint8_t my_addr);
int8_t rssi_convert(uint8_t Rssi);
uint8_t check_crc(uint8_t lqi);
uint8_t lqi_convert(uint8_t lqi);
uint8_t get_temp(uint8_t *ptemp_Arr);
void set_myaddr(uint8_t addr);
void set_channel(uint8_t channel);
void set_ISM(uint8_t ism_freq);
void set_mode(uint8_t mode);
void set_output_power_level(int8_t dbm);
void set_patable(uint8_t *patable_arr);
void set_fec(uint8_t cfg);
void set_data_whitening(uint8_t cfg);
void set_modulation_type(uint8_t cfg);
void set_preamble_len(uint8_t cfg);
void set_manchaster_encoding(u
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Hi, sry I can not see the screenshots. |
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sorry for that,is this better ?
…________________________________
De : SpaceTeddy <[email protected]>
Envoyé : mardi 14 août 2018 18:06:28
À : SpaceTeddy/CC1101
Cc : Ahmed BEN SOLTANE; Author
Objet : Re: [SpaceTeddy/CC1101] CC1101 raspberry and arduino (#23)
Hi, sry I can not see the screenshots.
May you please copy/ Paste the output of the serial monitor of your Arduino and the output of you raspi terminal?! Thx
—
You are receiving this because you authored the thread.
Reply to this email directly, view it on GitHub<#23 (comment)>, or mute the thread<https://github.com/notifications/unsubscribe-auth/Am2z38XvMHovfvRfoeXGyTESR5PJK-Faks5uQvWEgaJpZM4V8eyg>.
|
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no, sry. copy paste the output as text, not as screenshot. thx |
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arduino outpu :
********************************
Init CC1100...
Partnumber:00
Version:14
3318...done
8
Mode:3
Frequency:3
Channel:1
My_Addr:8
Cfg_reg:
07 2E 80 07 57 43 3E 0E 45 08
01 08 00 21 65 6A 5B F8 13 A0
F8 47 07 0C 18 1D 1C C7 00 B2
02 26 09 B6 04 EA 0A 00 11 41
00 59 7F 3C 81 3F 0B
PaTable:
03 17 1D 26 50 86 CD C0
CC1101 TX Demo
packet sent :
TX_FIFO:060308E0100804
raspberry output :
***********************************
pi@raspberrypi:/home/cc1101 $ ./RX_Demo -v -a3 -c1 -f868 -m100
CC1100 SW: Verbose option is set `'
Raspberry CC1101 SPI Library test
Init CC1100...
Partnumber: 0x00
Version : 0x14
...done!
Mode: 3
Frequency: 3
Channel: 1
My_Addr: 3
Config Register:
0x07 0x2E 0x80 0x07 0x57 0x43 0x3E 0x0E 0x45 0x03
0x01 0x08 0x00 0x21 0x65 0x6A 0x5B 0xF8 0x13 0xA0
0xF8 0x47 0x07 0x0C 0x18 0x1D 0x1C 0xC7 0x00 0xB2
0x02 0x26 0x09 0xB6 0x04 0xEC 0x29 0x1B 0x11 0x51
0x00 0x59 0x7F 0x3C 0x81 0x3F 0x0B
PaTable:
0x03 0x17 0x1D 0x26 0x50 0x86 0xCD 0xC0
…________________________________
De : Ahmed BEN SOLTANE
Envoyé : mardi 14 août 2018 18:10:56
À : SpaceTeddy/CC1101; SpaceTeddy/CC1101
Cc : Author
Objet : RE: [SpaceTeddy/CC1101] CC1101 raspberry and arduino (#23)
sorry for that,is this better ?
________________________________
De : SpaceTeddy <[email protected]>
Envoyé : mardi 14 août 2018 18:06:28
À : SpaceTeddy/CC1101
Cc : Ahmed BEN SOLTANE; Author
Objet : Re: [SpaceTeddy/CC1101] CC1101 raspberry and arduino (#23)
Hi, sry I can not see the screenshots.
May you please copy/ Paste the output of the serial monitor of your Arduino and the output of you raspi terminal?! Thx
—
You are receiving this because you authored the thread.
Reply to this email directly, view it on GitHub<#23 (comment)>, or mute the thread<https://github.com/notifications/unsubscribe-auth/Am2z38XvMHovfvRfoeXGyTESR5PJK-Faks5uQvWEgaJpZM4V8eyg>.
|
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ok, which cc1101 modules did you use? are they made for 868MHz? or did you use modules for 434MHz? |
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My modules are 868 mhz
Télécharger Outlook pour Android<https://aka.ms/ghei36>
…________________________________
From: SpaceTeddy <[email protected]>
Sent: Tuesday, August 14, 2018 5:22:05 PM
To: SpaceTeddy/CC1101
Cc: Ahmed BEN SOLTANE; Author
Subject: Re: [SpaceTeddy/CC1101] CC1101 raspberry and arduino (#23)
ok, which cc1101 modules did you use? are they made for 868MHz? or did you use modules for 434MHz?
—
You are receiving this because you authored the thread.
Reply to this email directly, view it on GitHub<#23 (comment)>, or mute the thread<https://github.com/notifications/unsubscribe-auth/Am2z37JFt7DuuapqnntXDjZastM0vh-eks5uQvktgaJpZM4V8eyg>.
|
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well, which example do you use for the tests? The standard RX_demo, TX_demo version, or the more sensitive WOR version? Have you done any modification to the code (instead of setting the modes)? Did you connect the interrupt signal (GDO2) to the correct port? |
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I used both rx_demo and tx _demo
Télécharger Outlook pour Android<https://aka.ms/ghei36>
…________________________________
From: SpaceTeddy <[email protected]>
Sent: Wednesday, August 15, 2018 6:38:23 AM
To: SpaceTeddy/CC1101
Cc: Ahmed BEN SOLTANE; Author
Subject: Re: [SpaceTeddy/CC1101] CC1101 raspberry and arduino (#23)
well, which example do you use for the tests? The standard RX_demo, TX_demo version, or the more sensitive WOR version? Have you done any modification to the code (instead of setting the modes)?
—
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Reply to this email directly, view it on GitHub<#23 (comment)>, or mute the thread<https://github.com/notifications/unsubscribe-auth/Am2z31ydhl4e5bYktAQa6IQ7ehhQVpLGks5uQ7PPgaJpZM4V8eyg>.
|
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send a picture of your test setup, please! |
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./RX_Demo -v -a3 -c1 -f868 -m100
Télécharger Outlook pour Android<https://aka.ms/ghei36>
…________________________________
From: SpaceTeddy <[email protected]>
Sent: Wednesday, August 15, 2018 7:22:57 PM
To: SpaceTeddy/CC1101
Cc: Ahmed BEN SOLTANE; Author
Subject: Re: [SpaceTeddy/CC1101] CC1101 raspberry and arduino (#23)
send a picture of your test setup, please!
—
You are receiving this because you authored the thread.
Reply to this email directly, view it on GitHub<#23 (comment)>, or mute the thread<https://github.com/notifications/unsubscribe-auth/Am2z336VGmGW-EZaZvg6GuHDbZkfrpizks5uRGcBgaJpZM4V8eyg>.
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i wanted to run ur code on an arduino as a sender and a raspberry as a reciever but althought both code seems to be working just fine ,there is no paquet recieved in the raspberry .
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