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benchmarks/74series.v doesn't exists on main #26

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misterjdrg opened this issue Nov 15, 2024 · 0 comments
Open

benchmarks/74series.v doesn't exists on main #26

misterjdrg opened this issue Nov 15, 2024 · 0 comments

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@misterjdrg
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Command:

cd sim
make

Output

yosys -q -s ../synth_74.ys -p "write_verilog 74series.v" ../benchmarks/74series.v
ERROR: Can't open input file `../benchmarks/74series.v' for reading: No such file or directory
make: *** [Makefile:12: 74series.v] Error 1
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