From e52ceb97bd2ed5f39dc8cc1a44bc854121ef6024 Mon Sep 17 00:00:00 2001 From: yufeng <321353225@qq.com> Date: Sat, 14 Sep 2024 12:13:09 +0800 Subject: [PATCH] fmt: Format code and fix some clippy --- src/addr.rs | 2 +- src/components/arch/aarch64.rs | 4 +-- src/components/arch/aarch64/psci.rs | 8 ++--- src/components/arch/loongarch64.rs | 11 ++++--- src/components/arch/riscv64.rs | 4 +-- src/components/boot/loongarch64.rs | 40 ++++++++++++++++++------- src/components/boot/riscv64.rs | 2 +- src/components/consts/mod.rs | 2 +- src/components/debug_console/mod.rs | 2 +- src/components/irq/aarch64.rs | 2 +- src/components/macros.rs | 39 ++++++++++++++++++++++++ src/components/mod.rs | 3 +- src/components/multicore/aarch64.rs | 5 ++++ src/components/multicore/loongarch64.rs | 13 ++++++-- src/components/multicore/mod.rs | 13 ++++++++ src/components/multicore/riscv64.rs | 33 +++++++++++++++----- src/components/multicore/x86_64.rs | 5 ++++ src/components/pagetable/loongarch64.rs | 14 ++++----- src/components/timer/aarch64.rs | 2 +- src/components/timer/riscv64.rs | 2 +- src/components/timer/x86_64.rs | 2 +- src/components/trap/aarch64.rs | 6 ++-- src/components/trap/loongarch64.rs | 2 +- src/components/trap/riscv64.rs | 9 +----- src/components/trap/x86_64.rs | 2 +- src/components/trapframe/x86_64.rs | 2 +- src/lib.rs | 1 - src/time.rs | 4 +-- src/utils/mutex_no_irq.rs | 8 ++--- 29 files changed, 171 insertions(+), 71 deletions(-) create mode 100644 src/components/macros.rs diff --git a/src/addr.rs b/src/addr.rs index 744c871..6c64f33 100644 --- a/src/addr.rs +++ b/src/addr.rs @@ -215,7 +215,7 @@ impl PhysPage { #[inline] pub fn copy_value_from_another(&self, ppn: PhysPage) { - self.get_buffer().copy_from_slice(&ppn.get_buffer()); + self.get_buffer().copy_from_slice(ppn.get_buffer()); #[cfg(c906)] unsafe { asm!(".long 0x0010000b"); // dcache.all diff --git a/src/components/arch/aarch64.rs b/src/components/arch/aarch64.rs index 3fbf699..5f91af6 100644 --- a/src/components/arch/aarch64.rs +++ b/src/components/arch/aarch64.rs @@ -26,10 +26,10 @@ pub(crate) fn arch_init() { } DTB_BIN.init_by(buffer); if let Ok(fdt) = Fdt::new(&DTB_BIN) { - info!("There has {} CPU(s)", fdt.cpus().count()); + log::info!("There has {} CPU(s)", fdt.cpus().count()); let mut mem_area = Vec::new(); fdt.memory().regions().for_each(|x| { - info!( + log::info!( "memory region {:#X} - {:#X}", x.starting_address as usize, x.starting_address as usize + x.size.unwrap() diff --git a/src/components/arch/aarch64/psci.rs b/src/components/arch/aarch64/psci.rs index 8bd0b67..877f3b0 100644 --- a/src/components/arch/aarch64/psci.rs +++ b/src/components/arch/aarch64/psci.rs @@ -94,9 +94,9 @@ fn psci_call(func: u32, arg0: usize, arg1: usize, arg2: usize) -> Result<(), Psc /// Shutdown the whole system, including all CPUs. pub fn system_off() -> ! { - info!("Shutting down..."); + log::info!("Shutting down..."); psci_call(PSCI_0_2_FN_SYSTEM_OFF, 0, 0, 0).ok(); - warn!("It should shutdown!"); + log::warn!("It should shutdown!"); loop { // crate::arch::halt(); } @@ -111,10 +111,10 @@ pub fn system_off() -> ! { /// `entry_point` is the physical address of the secondary CPU's entry point. /// `arg` will be passed to the `X0` register of the secondary CPU. pub fn cpu_on(target_cpu: usize, entry_point: usize, arg: usize) { - info!("Starting CPU {:x} ON ...", target_cpu); + log::info!("Starting CPU {:x} ON ...", target_cpu); let res = psci_call(PSCI_0_2_FN64_CPU_ON, target_cpu, entry_point, arg); if let Err(e) = res { - error!("failed to boot CPU {:x} ({:?})", target_cpu, e); + log::error!("failed to boot CPU {:x} ({:?})", target_cpu, e); } } diff --git a/src/components/arch/loongarch64.rs b/src/components/arch/loongarch64.rs index 162d1ab..edb34ba 100644 --- a/src/components/arch/loongarch64.rs +++ b/src/components/arch/loongarch64.rs @@ -1,3 +1,4 @@ +use alloc::vec; use alloc::vec::Vec; use crate::components::{common::{DTB_BIN, MEM_AREA}, consts::VIRT_ADDR_START}; @@ -5,14 +6,12 @@ use crate::components::{common::{DTB_BIN, MEM_AREA}, consts::VIRT_ADDR_START}; pub(crate) fn arch_init() { DTB_BIN.init_by(Vec::new()); - MEM_AREA.init_by({ - let mut mem_area = Vec::new(); - // This is just temporary solution until we find a better way to detect memory areas. - mem_area.push((VIRT_ADDR_START | 0x9000_0000, 0x2000_0000)); - mem_area - }); + MEM_AREA.init_by(vec![ + (VIRT_ADDR_START | 0x9000_0000, 0x2000_0000) + ]); } +#[inline] pub fn hart_id() -> usize { loongArch64::register::cpuid::read().core_id() } diff --git a/src/components/arch/riscv64.rs b/src/components/arch/riscv64.rs index fd0dc4b..1d3469f 100644 --- a/src/components/arch/riscv64.rs +++ b/src/components/arch/riscv64.rs @@ -32,9 +32,9 @@ pub fn arch_init() { DTB_BIN.init_by(buffer); let mut mem_area = Vec::new(); if let Ok(fdt) = Fdt::new(&DTB_BIN) { - info!("There has {} CPU(s)", fdt.cpus().count()); + log::info!("There has {} CPU(s)", fdt.cpus().count()); fdt.memory().regions().for_each(|x| { - info!( + log::info!( "memory region {:#X} - {:#X}", x.starting_address as usize, x.starting_address as usize + x.size.unwrap() diff --git a/src/components/boot/loongarch64.rs b/src/components/boot/loongarch64.rs index c18b47e..0b41606 100644 --- a/src/components/boot/loongarch64.rs +++ b/src/components/boot/loongarch64.rs @@ -1,6 +1,11 @@ -use loongArch64::register::euen; +use loongArch64::{ + consts::{LOONGARCH_CSR_MAIL_BUF0, LOONGARCH_CSR_MAIL_BUF1}, + iocsr::iocsr_read_d, + register::euen, +}; use crate::{ + arch::hart_id, clear_bss, components::{ common::CPU_NUM, @@ -27,6 +32,10 @@ unsafe extern "C" fn _start() -> ! { lu52i.d $t0, $t0, -1792 # CA, PLV0, 0x9000 xxxx xxxx xxxx csrwr $t0, 0x181 # LOONGARCH_CSR_DMWIN1 + # Goto 1 if hart is not 0 + csrrd $t1, 0x20 # read cpu from csr + bnez $t1, 1f + # Enable PG li.w $t0, 0xb0 # PLV=0, IE=0, PG=1 csrwr $t0, 0x0 # LOONGARCH_CSR_CRMD @@ -42,10 +51,19 @@ unsafe extern "C" fn _start() -> ! { csrrd $a0, 0x20 # cpuid la.global $t0, {entry} jirl $zero,$t0,0 + + 1: + li.w $s0, {MBUF0} + iocsrrd.d $t0, $s0 + la.global $t1, {sec_entry} + bne $t0, $t1, 1b + jirl $zero, $t1, 0 ", boot_stack_size = const crate::components::boot::STACK_SIZE, boot_stack = sym crate::components::boot::BOOT_STACK, + MBUF0 = const loongArch64::consts::LOONGARCH_CSR_MAIL_BUF0, entry = sym rust_tmp_main, + sec_entry = sym _start_secondary, options(noreturn), ) } @@ -67,18 +85,16 @@ pub(crate) unsafe extern "C" fn _start_secondary() -> ! { lu52i.d $t0, $t0, -1792 # CA, PLV0, 0x9000 xxxx xxxx xxxx csrwr $t0, 0x181 # LOONGARCH_CSR_DMWIN1 - la.abs $sp, {sec_boot_stack_top} - li.d $t0, {boot_stack_size} - add.d $sp, $sp, $t0 # setup boot stack + li.w $t0, {MBUF1} + iocsrrd.d $sp, $t0 - csrrd $a0, 0x20 # cpuid - la.global $t0, {entry} + csrrd $a0, 0x20 # cpuid + la.global $t0, {entry} jirl $zero,$t0,0 ", options(noreturn), - sec_boot_stack_top = sym crate::components::boot::BOOT_STACK, - boot_stack_size = const crate::components::boot::STACK_SIZE, + MBUF1 = const loongArch64::consts::LOONGARCH_CSR_MAIL_BUF1, entry = sym _rust_secondary_main, ) } @@ -124,9 +140,13 @@ fn init_cpu() { } /// The entry point for the second core. -pub(crate) extern "C" fn _rust_secondary_main(hart_id: usize) { +pub(crate) extern "C" fn _rust_secondary_main() { + let hart_id = hart_id(); percpu_area_init(hart_id); + log::info!("mailbox: {:#x}", iocsr_read_d(LOONGARCH_CSR_MAIL_BUF0)); + log::info!("mailbox: {:#x}", iocsr_read_d(LOONGARCH_CSR_MAIL_BUF1)); + #[cfg(feature = "trap")] crate::components::trap::set_trap_vector_base(); // Initialize CPU Configuration. @@ -134,7 +154,7 @@ pub(crate) extern "C" fn _rust_secondary_main(hart_id: usize) { crate::components::timer::init_timer(); #[cfg(feature = "trap")] crate::components::trap::tlb_init(crate::components::trap::tlb_fill as _); - + unsafe { crate::components::boot::_main_for_arch(hart_id) }; } diff --git a/src/components/boot/riscv64.rs b/src/components/boot/riscv64.rs index 4c2aa0e..eb19afd 100644 --- a/src/components/boot/riscv64.rs +++ b/src/components/boot/riscv64.rs @@ -174,7 +174,7 @@ pub(crate) extern "C" fn rust_secondary_main(hartid: usize) { // Initialize CPU Configuration. init_cpu(); - info!("secondary hart {} started", hartid); + log::info!("secondary hart {} started", hartid); unsafe { crate::components::boot::_main_for_arch(hartid) }; Instruction::shutdown(); } diff --git a/src/components/consts/mod.rs b/src/components/consts/mod.rs index 15a352e..45a0c53 100644 --- a/src/components/consts/mod.rs +++ b/src/components/consts/mod.rs @@ -11,6 +11,6 @@ pub const VIRT_ADDR_START: usize = GenericConfig::VIRT_ADDR; struct GenericConfig; /// Configuration Trait, Bound for configs -pub(self) trait ConfigTrait { +trait ConfigTrait { const VIRT_ADDR: usize; } diff --git a/src/components/debug_console/mod.rs b/src/components/debug_console/mod.rs index 5e6362c..645dedc 100644 --- a/src/components/debug_console/mod.rs +++ b/src/components/debug_console/mod.rs @@ -50,7 +50,7 @@ pub struct DebugConsole; // Write string through DebugConsole impl Write for DebugConsole { fn write_str(&mut self, s: &str) -> core::fmt::Result { - s.as_bytes().into_iter().for_each(|x| Self::putchar(*x)); + s.as_bytes().iter().for_each(|x| Self::putchar(*x)); Ok(()) } } diff --git a/src/components/irq/aarch64.rs b/src/components/irq/aarch64.rs index 50e9e74..6492c0c 100644 --- a/src/components/irq/aarch64.rs +++ b/src/components/irq/aarch64.rs @@ -28,7 +28,7 @@ static GICC: GicCpuInterface = GicCpuInterface::new(GICC_BASE.get_mut_ptr()); /// Initializes GICD, GICC on the primary CPU. pub(crate) fn init() { - info!("Initialize GICv2..."); + log::info!("Initialize GICv2..."); GICD.lock().init(); GICC.init(); } diff --git a/src/components/macros.rs b/src/components/macros.rs new file mode 100644 index 0000000..f155bcc --- /dev/null +++ b/src/components/macros.rs @@ -0,0 +1,39 @@ +#[cfg(target_arch = "loongarch64")] +#[macro_export] +macro_rules! pub_use_arch { + ($($name:ident),*) => { + $( + pub use self::loongarch64::$name; + )* + }; +} + +#[cfg(target_arch = "x86_64")] +#[macro_export] +macro_rules! pub_use_arch { + ($($name:ident),*) => { + $( + pub use self::x86_64::$name; + )* + }; +} + +#[cfg(target_arch = "riscv64")] +#[macro_export] +macro_rules! pub_use_arch { + ($($name:ident),*) => { + $( + pub use self::riscv64::$name; + )* + }; +} + +#[cfg(target_arch = "aarch64")] +#[macro_export] +macro_rules! pub_use_arch { + ($($name:ident),*) => { + $( + pub use self::aarch64::$name; + )* + }; +} diff --git a/src/components/mod.rs b/src/components/mod.rs index 73bd9cd..df5e39a 100644 --- a/src/components/mod.rs +++ b/src/components/mod.rs @@ -10,6 +10,7 @@ pub mod debug_console; pub mod instruction; pub mod irq; pub mod kcontext; +pub mod macros; pub mod mem; #[cfg(feature = "multicore")] pub mod multicore; @@ -20,4 +21,4 @@ pub mod timer; pub mod trap; pub mod trapframe; -pub(self) use polyhal_macro::define_arch_mods; +use polyhal_macro::define_arch_mods; diff --git a/src/components/multicore/aarch64.rs b/src/components/multicore/aarch64.rs index 7534c5a..661d421 100644 --- a/src/components/multicore/aarch64.rs +++ b/src/components/multicore/aarch64.rs @@ -1,5 +1,10 @@ use crate::components::multicore::MultiCore; +// TODO: Boot a core with top pointer of the stack +pub fn boot_core(_hart_id: usize, _sp_top: usize) { + log::error!("Boot Core is not implemented yet for aarch64"); +} + impl MultiCore { /// Boot application cores pub fn boot_all() {} diff --git a/src/components/multicore/loongarch64.rs b/src/components/multicore/loongarch64.rs index e9b6763..663d322 100644 --- a/src/components/multicore/loongarch64.rs +++ b/src/components/multicore/loongarch64.rs @@ -1,11 +1,20 @@ use loongArch64::ipi::{csr_mail_send, send_ipi_single}; -use crate::components::multicore::MultiCore; +use crate::{boot::BOOT_STACK, components::multicore::MultiCore}; + +// TODO: Boot a core with top pointer of the stack +pub fn boot_core(hart_id: usize, sp_top: usize) { + csr_mail_send(crate::components::boot::_start_secondary as _, hart_id, 0); + csr_mail_send(sp_top as _, hart_id, 1); + send_ipi_single(1, 1); +} impl MultiCore { pub fn boot_all() { + // Stack Pointer. + let stack_ptr = unsafe { BOOT_STACK.as_ptr() as u64 + BOOT_STACK.len() as u64 }; csr_mail_send(crate::components::boot::_start_secondary as _, 1, 0); + csr_mail_send(stack_ptr, 1, 1); send_ipi_single(1, 1); - loop {} } } diff --git a/src/components/multicore/mod.rs b/src/components/multicore/mod.rs index 19d0f8a..a2ea835 100644 --- a/src/components/multicore/mod.rs +++ b/src/components/multicore/mod.rs @@ -15,6 +15,19 @@ //! Here will have more functionality about multicore in the future. //! +use crate::{pub_use_arch, utils::MutexNoIrq}; + pub struct MultiCore; +static CORE_SET: MutexNoIrq = MutexNoIrq::new(0); + +pub struct CpuCore; + +/// Initialize the core with boot_hart_id +pub(crate) fn init(boot_hart_id: usize) { + let mut set = CORE_SET.lock(); + *set |= 1 << boot_hart_id; +} + super::define_arch_mods!(); +pub_use_arch!(boot_core); diff --git a/src/components/multicore/riscv64.rs b/src/components/multicore/riscv64.rs index 53fc96b..e723509 100644 --- a/src/components/multicore/riscv64.rs +++ b/src/components/multicore/riscv64.rs @@ -1,12 +1,29 @@ use crate::{ - components::{ - common::{frame_alloc, CPU_ID, CPU_NUM}, - consts::{MULTI_CORE_AREA, MULTI_CORE_AREA_SIZE, VIRT_ADDR_START}, - multicore::MultiCore, - }, + boot::secondary_start, + common::{frame_alloc, CPU_ID, CPU_NUM}, + consts::{MULTI_CORE_AREA, MULTI_CORE_AREA_SIZE, VIRT_ADDR_START}, + multicore::MultiCore, MappingFlags, MappingSize, PageTable, }; +// TODO: Boot a core with top pointer of the stack +pub fn boot_core(cpu: usize, sp_top: usize) { + if cpu == CPU_ID.read_current() { + return; + }; + + // PERCPU DATA ADDRESS RANGE END + let aux_core_func = (secondary_start as usize) & (!VIRT_ADDR_START); + + log::info!("secondary addr: {:#x}", secondary_start as usize); + let ret = sbi_rt::hart_start(cpu, aux_core_func, sp_top); + if ret.is_ok() { + log::info!("hart {} Startting successfully", cpu); + } else { + log::warn!("hart {} Startting failed", cpu) + } +} + /// Implement the function for multicore impl MultiCore { /// Boot all application cores. @@ -36,12 +53,12 @@ impl MultiCore { ) } - info!("secondary addr: {:#x}", secondary_start as usize); + log::info!("secondary addr: {:#x}", secondary_start as usize); let ret = sbi_rt::hart_start(cpu, aux_core_func, cpu_addr_end); if ret.is_ok() { - info!("hart {} Startting successfully", cpu); + log::info!("hart {} Startting successfully", cpu); } else { - warn!("hart {} Startting failed", cpu) + log::warn!("hart {} Startting failed", cpu) } }); } diff --git a/src/components/multicore/x86_64.rs b/src/components/multicore/x86_64.rs index d25f99a..3e99aa3 100644 --- a/src/components/multicore/x86_64.rs +++ b/src/components/multicore/x86_64.rs @@ -1,5 +1,10 @@ use crate::components::multicore::MultiCore; +// TODO: Boot a core with top pointer of the stack +pub fn boot_core(_hart_id: usize, _sp_top: usize) { + log::error!("Boot Core is not implemented yet for aarch64"); +} + impl MultiCore { pub fn boot_all() {} } diff --git a/src/components/pagetable/loongarch64.rs b/src/components/pagetable/loongarch64.rs index ee7da5e..dfc955d 100644 --- a/src/components/pagetable/loongarch64.rs +++ b/src/components/pagetable/loongarch64.rs @@ -33,7 +33,7 @@ impl PTE { #[inline] pub(crate) fn new_page(ppn: PhysPage, flags: PTEFlags) -> Self { - Self(ppn.to_addr() | flags.bits() as usize) + Self(ppn.to_addr() | flags.bits()) } } @@ -55,14 +55,14 @@ impl From for PTEFlags { } } -impl Into for PTEFlags { - fn into(self) -> MappingFlags { +impl From for MappingFlags { + fn from(val: PTEFlags) -> Self { let mut flags = MappingFlags::empty(); - if self.contains(PTEFlags::W) { + if val.contains(PTEFlags::W) { flags |= MappingFlags::W; } - if self.contains(PTEFlags::D) { + if val.contains(PTEFlags::D) { flags |= MappingFlags::D; } @@ -70,7 +70,7 @@ impl Into for PTEFlags { // flags |= MappingFlags::X; // } - if self.contains(PTEFlags::PLV_USER) { + if val.contains(PTEFlags::PLV_USER) { flags |= MappingFlags::U; } flags @@ -175,7 +175,7 @@ impl VirtPage { /// Get n level page table index of the given virtual address #[inline] pub fn pn_index(&self, n: usize) -> usize { - (self.0 >> 9 * n) & 0x1ff + (self.0 >> (9 * n)) & 0x1ff } } diff --git a/src/components/timer/aarch64.rs b/src/components/timer/aarch64.rs index 312a4a5..66e34aa 100644 --- a/src/components/timer/aarch64.rs +++ b/src/components/timer/aarch64.rs @@ -24,7 +24,7 @@ pub fn set_next_timer() { pub fn init() { let freq = CNTFRQ_EL0.get(); - debug!("freq: {}", freq); + log::debug!("freq: {}", freq); CNTP_CTL_EL0.write(CNTP_CTL_EL0::ENABLE::SET); CNTP_TVAL_EL0.set(0); // Enable the timer irq. diff --git a/src/components/timer/riscv64.rs b/src/components/timer/riscv64.rs index d75424a..cb88308 100644 --- a/src/components/timer/riscv64.rs +++ b/src/components/timer/riscv64.rs @@ -29,5 +29,5 @@ pub fn init() { sie::set_stimer(); } set_next_timeout(); - info!("initialize timer interrupt"); + log::info!("initialize timer interrupt"); } diff --git a/src/components/timer/x86_64.rs b/src/components/timer/x86_64.rs index 60f242f..92f0895 100644 --- a/src/components/timer/x86_64.rs +++ b/src/components/timer/x86_64.rs @@ -23,7 +23,7 @@ pub(crate) fn init_early() { .map(|info| info.processor_base_frequency()) { if freq > 0 { - info!("Got TSC frequency by CPUID: {} MHz", freq); + log::info!("Got TSC frequency by CPUID: {} MHz", freq); unsafe { CPU_FREQ_MHZ = freq as _ } } } diff --git a/src/components/trap/aarch64.rs b/src/components/trap/aarch64.rs index 43b396c..22fb79e 100644 --- a/src/components/trap/aarch64.rs +++ b/src/components/trap/aarch64.rs @@ -57,7 +57,7 @@ fn handle_exception(tf: &mut TrapFrame, kind: TrapKind, source: TrapSource) -> T let trap_type = match esr.read_as_enum(ESR_EL1::EC) { Some(ESR_EL1::EC::Value::Brk64) => { let iss = esr.read(ESR_EL1::ISS); - debug!("BRK #{:#x} @ {:#x} ", iss, tf.elr); + log::debug!("BRK #{:#x} @ {:#x} ", iss, tf.elr); tf.elr += 4; TrapType::Breakpoint } @@ -65,7 +65,7 @@ fn handle_exception(tf: &mut TrapFrame, kind: TrapKind, source: TrapSource) -> T Some(ESR_EL1::EC::Value::DataAbortLowerEL) | Some(ESR_EL1::EC::Value::InstrAbortLowerEL) => { let iss = esr.read(ESR_EL1::ISS); - warn!( + log::warn!( "EL0 Page Fault @ {:#x}, FAR={:#x}, ISS={:#x}", tf.elr, FAR_EL1.get(), @@ -76,7 +76,7 @@ fn handle_exception(tf: &mut TrapFrame, kind: TrapKind, source: TrapSource) -> T Some(ESR_EL1::EC::Value::DataAbortCurrentEL) | Some(ESR_EL1::EC::Value::InstrAbortCurrentEL) => { let iss = esr.read(ESR_EL1::ISS); - warn!( + log::warn!( "EL1 Page Fault @ {:#x}, FAR={:#x}, ISS={:#x}:\n{:#x?}", tf.elr, FAR_EL1.get(), diff --git a/src/components/trap/loongarch64.rs b/src/components/trap/loongarch64.rs index 45e1e7e..4991670 100644 --- a/src/components/trap/loongarch64.rs +++ b/src/components/trap/loongarch64.rs @@ -305,7 +305,7 @@ fn loongarch64_trap_handler(tf: &mut TrapFrame) -> TrapType { let estat = estat::read(); let trap_type = match estat.cause() { Trap::Exception(Exception::Breakpoint) => { - debug!("Exception(Breakpoint) @ {:#x} ", tf.era); + log::debug!("Exception(Breakpoint) @ {:#x} ", tf.era); tf.era += 4; TrapType::Breakpoint } diff --git a/src/components/trap/riscv64.rs b/src/components/trap/riscv64.rs index 3d0fa3b..10d9ca4 100644 --- a/src/components/trap/riscv64.rs +++ b/src/components/trap/riscv64.rs @@ -95,13 +95,6 @@ pub(crate) fn init() { fn kernel_callback(context: &mut TrapFrame) -> TrapType { let scause = scause::read(); let stval = stval::read(); - // debug!( - // "int occurs: {:#x} {:?} stval {:#x} sepc: {:#x}", - // scause.bits(), - // scause.cause(), - // stval, - // context.sepc - // ); let trap_type = match scause.cause() { // 中断异常 Trap::Exception(Exception::Breakpoint) => { @@ -127,7 +120,7 @@ fn kernel_callback(context: &mut TrapFrame) -> TrapType { Trap::Exception(Exception::LoadPageFault) => TrapType::LoadPageFault(stval), Trap::Interrupt(Interrupt::SupervisorExternal) => TrapType::SupervisorExternal, _ => { - error!( + log::error!( "内核态中断发生: {:#x} {:?} stval {:#x} sepc: {:#x}", scause.bits(), scause.cause(), diff --git a/src/components/trap/x86_64.rs b/src/components/trap/x86_64.rs index 8a733f8..43f33be 100644 --- a/src/components/trap/x86_64.rs +++ b/src/components/trap/x86_64.rs @@ -75,7 +75,7 @@ fn kernel_callback(context: &mut TrapFrame) { } } BREAKPOINT_VECTOR => { - debug!("#BP @ {:#x} ", context.rip); + log::debug!("#BP @ {:#x} ", context.rip); TrapType::Breakpoint } GENERAL_PROTECTION_FAULT_VECTOR => { diff --git a/src/components/trapframe/x86_64.rs b/src/components/trapframe/x86_64.rs index e509086..001e68b 100644 --- a/src/components/trapframe/x86_64.rs +++ b/src/components/trapframe/x86_64.rs @@ -146,7 +146,7 @@ impl IndexMut for TrapFrame { TrapFrameArgs::SEPC => &mut self.rip, TrapFrameArgs::RA => { // set return address, at x86_64 is push return address to rsp, shoule be execute at end. - warn!("set_ra in x86_64 is push return address to rsp, shoule be execute at end"); + log::warn!("set_ra in x86_64 is push return address to rsp, shoule be execute at end"); self.rsp -= 8; unsafe { (self.rsp as *mut usize).as_mut().unwrap() } } diff --git a/src/lib.rs b/src/lib.rs index 4795db2..3eee953 100644 --- a/src/lib.rs +++ b/src/lib.rs @@ -145,7 +145,6 @@ extern crate alloc; -#[macro_use] extern crate log; pub mod addr; diff --git a/src/time.rs b/src/time.rs index ec6aa69..984f38f 100644 --- a/src/time.rs +++ b/src/time.rs @@ -49,13 +49,13 @@ impl Time { #[inline] pub fn to_usec(&self) -> usize { - self.0 * 1000_000 / Self::get_freq() + self.0 * 1_000_000 / Self::get_freq() } /// Converts hardware ticks to nanoseconds. #[inline] pub fn to_nsec(&self) -> usize { - self.0 * 1000_000_000 / Self::get_freq() + self.0 * 1_000_000_000 / Self::get_freq() } #[inline] diff --git a/src/utils/mutex_no_irq.rs b/src/utils/mutex_no_irq.rs index 90cc548..7779d82 100644 --- a/src/utils/mutex_no_irq.rs +++ b/src/utils/mutex_no_irq.rs @@ -84,13 +84,13 @@ pub struct MutexNoIrqGuard<'a, T: ?Sized + 'a> { impl<'a, T: ?Sized> Deref for MutexNoIrqGuard<'a, T> { type Target = T; - fn deref<'b>(&'b self) -> &'b T { - &*(self.guard) + fn deref(&self) -> &T { + &(self.guard) } } impl<'a, T: ?Sized> DerefMut for MutexNoIrqGuard<'a, T> { - fn deref_mut<'b>(&'b mut self) -> &'b mut T { - &mut *(self.guard) + fn deref_mut(&mut self) -> &mut T { + &mut (self.guard) } }