diff --git a/CircuitsDatabase/Sized netlists/Low frequency analog/README.md b/CircuitsDatabase/Sized netlists/Low frequency analog/README.md index eeaea54665..54fc36513b 100644 --- a/CircuitsDatabase/Sized netlists/Low frequency analog/README.md +++ b/CircuitsDatabase/Sized netlists/Low frequency analog/README.md @@ -9,9 +9,9 @@ Current mirror OTA - single ended | 7 nm | :heavy_check_mark: | :heavy_check_mar Five transistor OTA - single ended | 12 nm | :heavy_check_mark: | :heavy_check_mark: | | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | Five transistor OTA - single ended stacked | 7 nm | :heavy_check_mark: | :heavy_check_mark: | | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | Fully differential current mirror OTA | 65 nm | :heavy_check_mark: | | | | | | -Fully differential telescopic OTA | 7 nm | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | | :heavy_check_mark: | :heavy_check_mark: | +Telescopic OTA - fully differential| 7 nm | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | | :heavy_check_mark: | :heavy_check_mark: | Switched capacitor filter | 7 nm | :heavy_check_mark: | :heavy_check_mark: | | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | -Telescopic OTA - fully differential | 7 nm | :heavy_check_mark: | | | | | | +Fully differential telescopic OTA | 7 nm | :heavy_check_mark: | | | | | | Telescopic OTA - fully differential SC CMFB | 7 nm | :heavy_check_mark: | :heavy_check_mark: | | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | Telescopic OTA - single ended, stacked | 7 nm | :heavy_check_mark: | :heavy_check_mark: | | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | Non-overlapping clock generator | 65 nm | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | | | diff --git a/CircuitsDatabase/Sized netlists/Low frequency analog/Single_ended_OTA_Testbench/README.md b/CircuitsDatabase/Sized netlists/Low frequency analog/Single_ended_OTA_Testbench/README.md index 44aafed7c4..326263f50a 100644 --- a/CircuitsDatabase/Sized netlists/Low frequency analog/Single_ended_OTA_Testbench/README.md +++ b/CircuitsDatabase/Sized netlists/Low frequency analog/Single_ended_OTA_Testbench/README.md @@ -1,49 +1,13 @@ -## Gate driver circuit for a DLDO +## Single-ended OTA testbench -### Circuit Description +The table below contains all the important OTA performance metrics and the corresponding simulation used to evaluate. -This circuit is a part of the gate driver circuitry in a digital low voltage dropout regulator [1]. This circuit drives PMOS power transistors that supply a load current to the output at a given voltage. +

+ +

-The block diagram of the system is shown in the figure below. +The figure below contains a brief summary of the setup used for each of the testbenches listed above. -![Block diagram](Block_diagram_DLDO.PNG) - -The diagram of the circuit is as follows. - -![Circuit diagram](Circuit_diagram_gate_driver.PNG) - -### Pin description - -* Din - input pulse waveform -* Dout - inverted output pulse waveform -* Vb - gate voltage of transistor in triode that changes the on resistance -* SS - steady state detection signal switch -* SS bar - inverted steady state detection signal switch - -The operation of the circuit is highlighted below. - -![Working](Concept_gate_driver_DLDO.PNG) - -When the steady state detection is low, gate driver is a combination of an inverter with a voltage divider. Dout is at a voltage (eg. 250 mV) depending on the ratio of the resistors. When the steady state detection signal is high, the input is maintained constant, the voltage divider also incorporates the resistance contributed by the switch controlled by Vb. As Vb changes, Dout changes. - -### Netlist description - -* Din - input -* Dout - output -* Vb - control (similar to diagram) -* ss - steady state detection signal -* ss_bar_nmos - nmos switch controlled by ss_bar -* ss_bar_pmos - pmos switch controlled by ss_bar -* Lres_nmos - on voltage of large nmos resistor -* Lres_pmos - on voltage of large pmos resistor -* Sres_nmos - on voltage of small nmos resistor -* Sres_pmos - on voltage of small pmos resistor - -### Initial setup + Testbench - -To test this circuit, give a clock waveform at Din and observe Dout in steady state and not in steady state. In steady state, Vb can be changed to observe a change in Dout. - -### Constraints - -* In steady state there is power dissipation through the voltage divider and any added parasitic routing -* The capacitance at the output will lower the speed of switching when not in steady state +

+ +

\ No newline at end of file diff --git a/CircuitsDatabase/Sized netlists/Low frequency analog/Single_ended_OTA_Testbench/Summary.png b/CircuitsDatabase/Sized netlists/Low frequency analog/Single_ended_OTA_Testbench/Summary.png new file mode 100644 index 0000000000..5d1cbbc68e Binary files /dev/null and b/CircuitsDatabase/Sized netlists/Low frequency analog/Single_ended_OTA_Testbench/Summary.png differ diff --git a/CircuitsDatabase/Sized netlists/Low frequency analog/Single_ended_OTA_Testbench/single_ended_OTA_testbench_documentation.pdf b/CircuitsDatabase/Sized netlists/Low frequency analog/Single_ended_OTA_Testbench/single_ended_OTA_testbench_documentation.pdf new file mode 100644 index 0000000000..43fadddbed Binary files /dev/null and b/CircuitsDatabase/Sized netlists/Low frequency analog/Single_ended_OTA_Testbench/single_ended_OTA_testbench_documentation.pdf differ diff --git a/CircuitsDatabase/Sized netlists/Low frequency analog/Single_ended_OTA_Testbench/table.png b/CircuitsDatabase/Sized netlists/Low frequency analog/Single_ended_OTA_Testbench/table.png new file mode 100644 index 0000000000..445f8cc364 Binary files /dev/null and b/CircuitsDatabase/Sized netlists/Low frequency analog/Single_ended_OTA_Testbench/table.png differ diff --git a/CircuitsDatabase/Sized netlists/Wireless-Radio_frequency/Bandpass_filter/README.md b/CircuitsDatabase/Sized netlists/Wireless-Radio_frequency/Bandpass_filter/README.md index ae14884a1c..c4869e14b2 100644 --- a/CircuitsDatabase/Sized netlists/Wireless-Radio_frequency/Bandpass_filter/README.md +++ b/CircuitsDatabase/Sized netlists/Wireless-Radio_frequency/Bandpass_filter/README.md @@ -1,9 +1,20 @@ ## Bandpass filter circuit +A bandpass filter circuit is used for filtering band of signal frequencies at a center frequency (fc). ### Circuit description +The circuit requires inductors and capacitors for tuning the center frequency. As inductors are huge in size as compared to capacitors, +capacitors are used for tuning the center frequencies. To remove the parallel resistance in the LC circuit, a cross-coupled transistors +are used which add negative resistance. ### Testbench/Simulations +An AC and transient simulation is required to measure the perfomance of bandpass filter. An AC simulation will measure the quality factor +(Q) of the filter. ### Performance metrics +* Quality Factor (Q) +* Center frequency (fc) +* Bandwidth + ### Constraints +The parasitics around output node must be minimized to reduce variations of center frequency. diff --git a/CircuitsDatabase/Sized netlists/Wireless-Radio_frequency/LNA/README.md b/CircuitsDatabase/Sized netlists/Wireless-Radio_frequency/LNA/README.md index 110cf37139..673b37bf2d 100644 --- a/CircuitsDatabase/Sized netlists/Wireless-Radio_frequency/LNA/README.md +++ b/CircuitsDatabase/Sized netlists/Wireless-Radio_frequency/LNA/README.md @@ -1,9 +1,16 @@ ## LNA ### Circuit description +LNA are used at RF front end of receiver to set Noise floor of the system. ### Testbench/Simulations +AC simulation is used to check the gain. A noise simulation is required to check noise figure (NF) of LNA. +Transient simulation is used for checking IIP3 of LNA. ### Performance metrics +* Gain +* Noise figure +* IIP3 ### Constraints +A guard ring must be covering all transistors in LNA. Wide metal lines to reduce resistance over lines. \ No newline at end of file diff --git a/CircuitsDatabase/Sized netlists/Wireless-Radio_frequency/Mixer/README.md b/CircuitsDatabase/Sized netlists/Wireless-Radio_frequency/Mixer/README.md index 8d05d43dde..4357bcb4b9 100644 --- a/CircuitsDatabase/Sized netlists/Wireless-Radio_frequency/Mixer/README.md +++ b/CircuitsDatabase/Sized netlists/Wireless-Radio_frequency/Mixer/README.md @@ -1,9 +1,14 @@ ## Mixer ### Circuit description - +Mixers are used for translating RF signals to IF signals or IF signals to RF signals using local oscillator frequency. + ### Testbench/Simulations +Transient simulation is used for checking the output spectrum. PSP simulation is used to calculate the conversion gain. ### Performance metrics +* IIP3 +* Conversion Gain ### Constraints +Symmetric routing is critical for correct IF/RF output generation. Shielding the nets is recommended. \ No newline at end of file diff --git a/CircuitsDatabase/Sized netlists/Wireless-Radio_frequency/Oscillator/README.md b/CircuitsDatabase/Sized netlists/Wireless-Radio_frequency/Oscillator/README.md index e5c01dc495..3d6f712915 100644 --- a/CircuitsDatabase/Sized netlists/Wireless-Radio_frequency/Oscillator/README.md +++ b/CircuitsDatabase/Sized netlists/Wireless-Radio_frequency/Oscillator/README.md @@ -1,9 +1,14 @@ ## Oscillator ### Circuit description +For a oscillator circuit, a LC tank circuit is required. To cancel the parallel resistance in LC circuit, a cross coupled transistor pair +cancels the positive resistance by adding a negative resistance. ### Testbench/Simulations +Transient simulation is required to check lock range. ### Performance metrics +* Lock Range ### Constraints +Symmetric routes are required for differential output nets. Minimum parasitic for each net is critical for performance. diff --git a/CircuitsDatabase/Sized netlists/Wireline/README.md b/CircuitsDatabase/Sized netlists/Wireline/README.md index 889fdb9f0b..29ee6e443e 100644 --- a/CircuitsDatabase/Sized netlists/Wireline/README.md +++ b/CircuitsDatabase/Sized netlists/Wireline/README.md @@ -1,7 +1,14 @@ -**Wireline** +## **Wireline** Circuit | Technology | Netlist | Schematic | Layout | Testbench | Constraints | ALIGN | :------ | :--------- | :---- | :------ | :-------- | :----- | :-------- | :---------- | Single to differential converter | 12 nm | :heavy_check_mark: | | | | | | Adder | 12 nm | :heavy_check_mark: | | | | | | -Variable gain amplifier | 12 nm | :heavy_check_mark: | | | | | | +Variable gain amplifier (VGA) | 12 nm | :heavy_check_mark: | | | | | | +Adder unit | 12 nm | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | | :heavy_check_mark: | +Double tail sense amplifier | 12 nm | :heavy_check_mark: | :heavy_check_mark: | | | | :heavy_check_mark: | +Linear Equalizer 2 level| 12 nm | :heavy_check_mark: | :heavy_check_mark: | | | | :heavy_check_mark: | +Linear Equalizer 4 level | 12 nm | :heavy_check_mark: | :heavy_check_mark: | | :heavy_check_mark: | | :heavy_check_mark: | +Transimpedance amplifier | 12 nm | :heavy_check_mark: | :heavy_check_mark: | | | | :heavy_check_mark: | +Variable gain amplifier | 12 nm | :heavy_check_mark: | :heavy_check_mark: | | :heavy_check_mark: | | :heavy_check_mark: | +Variable gain amplifier 3 stage | 12 nm | :heavy_check_mark: | :heavy_check_mark: | | | | :heavy_check_mark: | diff --git a/CircuitsDatabase/Sized netlists/Wireline/adder_unit/Adder_schematic_top.sp b/CircuitsDatabase/Sized netlists/Wireline/adder_unit/Adder_schematic_top.sp new file mode 100644 index 0000000000..5eeafe8b8f --- /dev/null +++ b/CircuitsDatabase/Sized netlists/Wireline/adder_unit/Adder_schematic_top.sp @@ -0,0 +1,43 @@ +// Generated for: spectre +// Generated on: Jan 1 23:12:07 2020 +// Design library name: EQ_01012020 +// Design cell name: Adder_top +// Design view name: schematic +simulator lang=spectre global 0 vdd! + + +// Library name: EQ_01012020 +// Cell name: Adder_top +// View name: schematic +R2 (vout vdd!) metalres w=32n l=19.944u metLayer=15 +R1 (vb1 net2) metalres w=32n l=684.384u metLayer=15 +R0 (net3 vb2) metalres w=32n l=684.384u metLayer=15 +N0 (vout net2 net010 0) nfet m=1 l=14n nfin=12 nf=3 +N2 (net010 net2 0 0) nfet m=1 l=14n nfin=12 nf=3 +C2 (vout 0) capacitor c=cload_adder +C1 (vin net2) apmom1v2 m=1 w=1.724u l=8.6u +C0 (vin net3) apmom1v2 m=1 w=1.724u l=8.6u +V3 (vdd! 0) vsource dc=vps type=dc +V1 (vb2 0) vsource dc=vbias_pfet_adder type=dc +V0 (vb1 0) vsource dc=vbias_nfet_adder type=dc +V2 (vin 0) vsource mag=1 type=sine ampl=100m freq=1G +P0 (vout net3 net011 vdd!) pfet m=1 l=14n nfin=12 nf=3 +P1 (net011 net3 vdd! vdd!) pfet m=1 l=14n nfin=12 nf=3 +simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=27 \ + tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \ + digits=5 cols=80 pivrel=1e-3 sensfile="../psf/sens.output" \ + checklimitdest=psf +dcOp dc write="spectre.dc" maxiters=150 maxsteps=10000 annotate=status +dcOpInfo info what=oppoint where=rawfile +ac ac start=10000 stop=100G dec=10 annotate=status +tran tran stop=10n errpreset=conservative write="spectre.ic" \ + writefinal="spectre.fc" annotate=status maxiters=5 +finalTimeOP info what=oppoint where=rawfile +modelParameter info what=models where=rawfile +element info what=inst where=rawfile +outputParameter info what=output where=rawfile +designParamVals info what=parameters where=rawfile +primitives info what=primitives where=rawfile +subckts info what=subckts where=rawfile +saveOptions options save=allpub + diff --git a/CircuitsDatabase/Sized netlists/Wireline/adder_unit/adder_layout.tiff b/CircuitsDatabase/Sized netlists/Wireline/adder_unit/adder_layout.tiff new file mode 100644 index 0000000000..bc77c03444 Binary files /dev/null and b/CircuitsDatabase/Sized netlists/Wireline/adder_unit/adder_layout.tiff differ diff --git a/CircuitsDatabase/Sized netlists/Wireline/adder_unit/adder_schematic.tiff b/CircuitsDatabase/Sized netlists/Wireline/adder_unit/adder_schematic.tiff new file mode 100644 index 0000000000..c5734b898c Binary files /dev/null and b/CircuitsDatabase/Sized netlists/Wireline/adder_unit/adder_schematic.tiff differ diff --git a/CircuitsDatabase/Sized netlists/Wireline/adder_unit/adder_unit.sp b/CircuitsDatabase/Sized netlists/Wireline/adder_unit/adder_unit.sp new file mode 100644 index 0000000000..0c7808ebbe --- /dev/null +++ b/CircuitsDatabase/Sized netlists/Wireline/adder_unit/adder_unit.sp @@ -0,0 +1,10 @@ + +.subckt adder_align vb1 vb2 vin vout vps vgnd + MN0 vout n1 vgnd vgnd nfet l=0.014u nfin=36 + MP0 vout n2 vps vps pfet l=0.014u nfin=36 + R0 n1 vb1 resistor r=15000 + Rph0 n1 vin resistor r=15000 + R1 n2 vb2 resistor r=15000 + Rph1 n2 vin resistor r=15000 + R2 vps vout resistor r=500 +.ends adder_align diff --git a/CircuitsDatabase/Sized netlists/Wireline/double_tail_sense_amplifier/.double_tail_sense_amplifier.const.swp b/CircuitsDatabase/Sized netlists/Wireline/double_tail_sense_amplifier/.double_tail_sense_amplifier.const.swp new file mode 100644 index 0000000000..e5ee63a58d Binary files /dev/null and b/CircuitsDatabase/Sized netlists/Wireline/double_tail_sense_amplifier/.double_tail_sense_amplifier.const.swp differ diff --git a/CircuitsDatabase/Sized netlists/Wireline/double_tail_sense_amplifier/DTSA_layout.tiff b/CircuitsDatabase/Sized netlists/Wireline/double_tail_sense_amplifier/DTSA_layout.tiff new file mode 100644 index 0000000000..cc6ea58e03 Binary files /dev/null and b/CircuitsDatabase/Sized netlists/Wireline/double_tail_sense_amplifier/DTSA_layout.tiff differ diff --git a/CircuitsDatabase/Sized netlists/Wireline/double_tail_sense_amplifier/DTSA_schematic.tiff b/CircuitsDatabase/Sized netlists/Wireline/double_tail_sense_amplifier/DTSA_schematic.tiff new file mode 100644 index 0000000000..9bdacced0e Binary files /dev/null and b/CircuitsDatabase/Sized netlists/Wireline/double_tail_sense_amplifier/DTSA_schematic.tiff differ diff --git a/CircuitsDatabase/Sized netlists/Wireline/double_tail_sense_amplifier/double_tail_sense_amplifier.sp b/CircuitsDatabase/Sized netlists/Wireline/double_tail_sense_amplifier/double_tail_sense_amplifier.sp new file mode 100644 index 0000000000..45172f426d --- /dev/null +++ b/CircuitsDatabase/Sized netlists/Wireline/double_tail_sense_amplifier/double_tail_sense_amplifier.sp @@ -0,0 +1,31 @@ + +.subckt common_centroid_n d1 d2 s +MN1 d1 d2 s s nfet l=14e-9 nfin=12 +MN0 d2 d1 s s nfet l=14e-9 nfin=12 +.ends common_centroid_n + +.subckt common_centroid_p d1 d2 s +MP1 d1 d2 s s pfet l=14e-9 nfin=12 +MP0 d2 d1 s s pfet l=14e-9 nfin=12 +.ends common_centroid_p + +.subckt common_centroid_np d1 d2 vps vgnd +xI0 d1 d2 vgnd common_centroid_n +xI1 d1 d2 vps common_centroid_p +.ends + +.subckt double_tail_sense_amplifier clk clkb in1 in2 out1 out2 vps vgnd + +MN1 out1 n1 vgnd vgnd nfet l=14e-9 nfin=12 +MN2 out2 n2 vgnd vgnd nfet l=14e-9 nfin=12 +MP1 net8 clkb vps vps pfet l=14e-9 nfin=12 +xI2 out1 out2 net8 vgnd common_centroid_np + +MN3 n1 in1 net6 net6 nfet l=14e-9 nfin=12 +MN4 n2 in2 net6 net6 nfet l=14e-9 nfin=12 +MN5 net6 clk vgnd vgnd nfet l=14e-9 nfin=12 +MP2 n1 clk vps vps pfet l=14e-9 nfin=12 +MP3 n2 clk vps vps pfet l=14e-9 nfin=12 +.ends + + diff --git a/CircuitsDatabase/Sized netlists/Wireline/linear_equalizer_2_level/LE_layout.tiff b/CircuitsDatabase/Sized netlists/Wireline/linear_equalizer_2_level/LE_layout.tiff new file mode 100644 index 0000000000..e275d6c96c Binary files /dev/null and b/CircuitsDatabase/Sized netlists/Wireline/linear_equalizer_2_level/LE_layout.tiff differ diff --git a/CircuitsDatabase/Sized netlists/Wireline/linear_equalizer_2_level/LE_schematic.tiff b/CircuitsDatabase/Sized netlists/Wireline/linear_equalizer_2_level/LE_schematic.tiff new file mode 100644 index 0000000000..065f82a177 Binary files /dev/null and b/CircuitsDatabase/Sized netlists/Wireline/linear_equalizer_2_level/LE_schematic.tiff differ diff --git a/CircuitsDatabase/Sized netlists/Wireline/linear_equalizer_2_level/linear_equalizer.sp b/CircuitsDatabase/Sized netlists/Wireline/linear_equalizer_2_level/linear_equalizer.sp new file mode 100644 index 0000000000..cf8f92b955 --- /dev/null +++ b/CircuitsDatabase/Sized netlists/Wireline/linear_equalizer_2_level/linear_equalizer.sp @@ -0,0 +1,13 @@ + +.subckt linear_equalizer_or vmirror vin1 vin2 vout1 vout2 vps vgnd +MN0 vmirror vmirror vgnd vgnd nfet l=14e-9 nfin=12 +MN1 n1 vmirror vgnd vgnd nfet l=14e-9 nfin=12 +MN2 n2 vmirror vgnd vgnd nfet l=14e-9 nfin=12 +MN3 vout1 vin1 n1 vgnd nfet l=14e-9 nfin=12 +MN4 vout2 vin2 n2 vgnd nfet l=14e-9 nfin=12 +R0 vps vout1 resistor r=100 +R1 vps vout2 resistor r=100 +R2 n1 n2 resistor r=100 +R3 n1 n2 resistor r=2000 +.ends linear_equalizer_or + diff --git a/CircuitsDatabase/Sized netlists/Wireline/linear_equalizer_4_level/CTLE_schematic_top.sp b/CircuitsDatabase/Sized netlists/Wireline/linear_equalizer_4_level/CTLE_schematic_top.sp new file mode 100644 index 0000000000..5243aa349c --- /dev/null +++ b/CircuitsDatabase/Sized netlists/Wireline/linear_equalizer_4_level/CTLE_schematic_top.sp @@ -0,0 +1,293 @@ +// Generated for: spectre +// Generated on: Jan 5 09:35:33 2020 +// Design library name: EQ_01032020 +// Design cell name: CTLE_top +// Design view name: schematic +simulator lang=spectre +global 0 vdd! +//include "$SPECTRE_MODEL_PATH/12LP_Spectre.lib" section=tt +include "/project/design-kits/GF_PDKs/12nm/PDK/GF-12LP/12LP/V1.0_1.4/Models/Spectre/models/12LP_Spectre.lib" section=tt +parameters vs3=0.85 vs4=0 vs5=0 vs2=0.85 vs1=0.85 nfpf_ctle_sw0=40 ngf_ctle_sw0=1 \ + vs0=0.85 Cs=25f Rs=100 cload=10f ib_ctle=180u nfpf_ctle_cm=80 \ + nfpf_ctle_dp=50 ngf_ctle_cm=1 ngf_ctle_dp=1 rload_ctle=800 vbias=594m \ + vps=0.85 wireopt=9 + +// Library name: EQ_01032020 +// Cell name: CTLE_top +// View name: schematic +V6 (s3_ctle 0) vsource dc=vs3 type=dc +V5 (s2_ctle 0) vsource dc=vs2 type=dc +V4 (s1_ctle 0) vsource dc=vs1 type=dc +V3 (s0_ctle 0) vsource dc=vs0 type=dc +V1 (vdd! 0) vsource dc=vps type=dc +V0 (vcm_ctle 0) vsource dc=vbias type=dc +C2 (vout2_ctle 0) capacitor c=cload +C1 (vout1_ctle 0) capacitor c=cload +V2 (vac 0) vsource dc=0 mag=2 type=sine ampl=200m freq=1G +I25 (vdd! net048) isource dc=ib_ctle type=dc +E2 (vin2 vcm_ctle vac 0) vcvs gain=-0.5 +E0 (vin1 vcm_ctle vac 0) vcvs gain=0.5 +N33 (net066 vin2 net055 0) nfet m=1 l=14n nfin=12 nf=4 par=(1) \ + par_nf=(1)*(4) asej=((54n)+(54n))*(11n)*12 + 12*1*(((78n)-(14n)-(10n)-(0))*(11n)) \ + adej=12*2*(((78n)-(14n)-(10n)-(0))*(11n)) psej=(1)*12*((54n)*2+(11n)+(54n)*2+(11n)) + 12*1*(1)*2*((78n)-(14n)-(10n)-(0)) \ + pdej=12*2*(1)*2*((78n)-(14n)-(10n)-(0)) pdevdops=1 pdevlgeos=1 \ + pdevwgeos=1 psw_acv_sign=1 plnest=1 pldist=1 plorient=0 cpp=78n \ + fpitch=48n xpos=-99 ypos=-99 ptwell=0 sca=0 scb=0 scc=0 \ + pre_layout_local=1 ngcon=1 p_vta=0 p_la=0 u0mult_fet=1 lle_sa=71n \ + lle_sb=71n lle_rxrxa=78n lle_rxrxb=78n lle_rxrxn=192n \ + lle_rxrxs=192n lle_pcrxn=55n lle_pcrxs=55n lle_nwa=2u lle_nwb=2u \ + lle_nwn=192n lle_nws=192n lle_ctne=0 lle_ctnw=0 lle_ctse=0 \ + lle_ctsw=0 lle_sctne=0 lle_sctnw=0 lle_sctse=0 lle_sctsw=0 \ + lrsd=27n dtemp=0 l_shape=0 l_shape_s=0 nsig_dop1=0 nsig_dop2=0 \ + nsig_dibl=0 nsig_pc=0 nsig_rx=0 fc_index=0 fc_sigma=3 +N32 (vout2_ctle vin2 net066 0) nfet m=1 l=14n nfin=12 nf=4 par=(1) \ + par_nf=(1)*(4) asej=((54n)+(54n))*(11n)*12 + 12*1*(((78n)-(14n)-(10n)-(0))*(11n)) \ + adej=12*2*(((78n)-(14n)-(10n)-(0))*(11n)) psej=(1)*12*((54n)*2+(11n)+(54n)*2+(11n)) + 12*1*(1)*2*((78n)-(14n)-(10n)-(0)) \ + pdej=12*2*(1)*2*((78n)-(14n)-(10n)-(0)) pdevdops=1 pdevlgeos=1 \ + pdevwgeos=1 psw_acv_sign=1 plnest=1 pldist=1 plorient=0 cpp=78n \ + fpitch=48n xpos=-99 ypos=-99 ptwell=0 sca=0 scb=0 scc=0 \ + pre_layout_local=1 ngcon=1 p_vta=0 p_la=0 u0mult_fet=1 lle_sa=71n \ + lle_sb=71n lle_rxrxa=78n lle_rxrxb=78n lle_rxrxn=192n \ + lle_rxrxs=192n lle_pcrxn=55n lle_pcrxs=55n lle_nwa=2u lle_nwb=2u \ + lle_nwn=192n lle_nws=192n lle_ctne=0 lle_ctnw=0 lle_ctse=0 \ + lle_ctsw=0 lle_sctne=0 lle_sctnw=0 lle_sctse=0 lle_sctsw=0 \ + lrsd=27n dtemp=0 l_shape=0 l_shape_s=0 nsig_dop1=0 nsig_dop2=0 \ + nsig_dibl=0 nsig_pc=0 nsig_rx=0 fc_index=0 fc_sigma=3 +N31 (net055 net048 net065 0) nfet m=1 l=14n nfin=12 nf=7 par=(1) \ + par_nf=(1)*(7) asej=(54n)*(11n)*12 + 12*3*(((78n)-(14n)-(10n)-(0))*(11n)) \ + adej=(54n)*(11n)*12+3*(((78n)-(14n)-(10n)-(0))*(11n))*12 psej=(1)*12*(2*(54n)+(11n)) + 12*3*(1)*2*((78n)-(14n)-(10n)-(0)) \ + pdej=(1)*12*(2*(54n)+(11n)) + 12*3*(1)*2*((78n)-(14n)-(10n)-(0)) pdevdops=1 \ + pdevlgeos=1 pdevwgeos=1 psw_acv_sign=1 plnest=1 pldist=1 \ + plorient=0 cpp=78n fpitch=48n xpos=-99 ypos=-99 ptwell=0 sca=0 \ + scb=0 scc=0 pre_layout_local=1 ngcon=1 p_vta=0 p_la=0 \ + u0mult_fet=1 lle_sa=71n lle_sb=71n lle_rxrxa=78n lle_rxrxb=78n \ + lle_rxrxn=192n lle_rxrxs=192n lle_pcrxn=55n lle_pcrxs=55n \ + lle_nwa=2u lle_nwb=2u lle_nwn=192n lle_nws=192n lle_ctne=0 \ + lle_ctnw=0 lle_ctse=0 lle_ctsw=0 lle_sctne=0 lle_sctnw=0 \ + lle_sctse=0 lle_sctsw=0 lrsd=27n dtemp=0 l_shape=0 l_shape_s=0 \ + nsig_dop1=0 nsig_dop2=0 nsig_dibl=0 nsig_pc=0 nsig_rx=0 fc_index=0 \ + fc_sigma=3 +N30 (net065 net048 0 0) nfet m=1 l=14n nfin=12 nf=7 par=(1) par_nf=(1)*(7) \ + asej=(54n)*(11n)*12 + 12*3*(((78n)-(14n)-(10n)-(0))*(11n)) adej=(54n)*(11n)*12+3*(((78n)-(14n)-(10n)-(0))*(11n))*12 \ + psej=(1)*12*(2*(54n)+(11n)) + 12*3*(1)*2*((78n)-(14n)-(10n)-(0)) pdej=(1)*12*(2*(54n)+(11n)) + 12*3*(1)*2*((78n)-(14n)-(10n)-(0)) \ + pdevdops=1 pdevlgeos=1 pdevwgeos=1 psw_acv_sign=1 plnest=1 \ + pldist=1 plorient=0 cpp=78n fpitch=48n xpos=-99 ypos=-99 ptwell=0 \ + sca=0 scb=0 scc=0 pre_layout_local=1 ngcon=1 p_vta=0 p_la=0 \ + u0mult_fet=1 lle_sa=71n lle_sb=71n lle_rxrxa=78n lle_rxrxb=78n \ + lle_rxrxn=192n lle_rxrxs=192n lle_pcrxn=55n lle_pcrxs=55n \ + lle_nwa=2u lle_nwb=2u lle_nwn=192n lle_nws=192n lle_ctne=0 \ + lle_ctnw=0 lle_ctse=0 lle_ctsw=0 lle_sctne=0 lle_sctnw=0 \ + lle_sctse=0 lle_sctsw=0 lrsd=27n dtemp=0 l_shape=0 l_shape_s=0 \ + nsig_dop1=0 nsig_dop2=0 nsig_dibl=0 nsig_pc=0 nsig_rx=0 fc_index=0 \ + fc_sigma=3 +N29 (net074 s2_ctle net068 0) nfet m=1 l=14n nfin=12 nf=4 par=(1) \ + par_nf=(1)*(4) asej=((54n)+(54n))*(11n)*12 + 12*1*(((78n)-(14n)-(10n)-(0))*(11n)) \ + adej=12*2*(((78n)-(14n)-(10n)-(0))*(11n)) psej=(1)*12*((54n)*2+(11n)+(54n)*2+(11n)) + 12*1*(1)*2*((78n)-(14n)-(10n)-(0)) \ + pdej=12*2*(1)*2*((78n)-(14n)-(10n)-(0)) pdevdops=1 pdevlgeos=1 \ + pdevwgeos=1 psw_acv_sign=1 plnest=1 pldist=1 plorient=0 cpp=78n \ + fpitch=48n xpos=-99 ypos=-99 ptwell=0 sca=0 scb=0 scc=0 \ + pre_layout_local=1 ngcon=1 p_vta=0 p_la=0 u0mult_fet=1 lle_sa=71n \ + lle_sb=71n lle_rxrxa=78n lle_rxrxb=78n lle_rxrxn=192n \ + lle_rxrxs=192n lle_pcrxn=55n lle_pcrxs=55n lle_nwa=2u lle_nwb=2u \ + lle_nwn=192n lle_nws=192n lle_ctne=0 lle_ctnw=0 lle_ctse=0 \ + lle_ctsw=0 lle_sctne=0 lle_sctnw=0 lle_sctse=0 lle_sctsw=0 \ + lrsd=27n dtemp=0 l_shape=0 l_shape_s=0 nsig_dop1=0 nsig_dop2=0 \ + nsig_dibl=0 nsig_pc=0 nsig_rx=0 fc_index=0 fc_sigma=3 +N28 (net073 s1_ctle net067 0) nfet m=1 l=14n nfin=12 nf=4 par=(1) \ + par_nf=(1)*(4) asej=((54n)+(54n))*(11n)*12 + 12*1*(((78n)-(14n)-(10n)-(0))*(11n)) \ + adej=12*2*(((78n)-(14n)-(10n)-(0))*(11n)) psej=(1)*12*((54n)*2+(11n)+(54n)*2+(11n)) + 12*1*(1)*2*((78n)-(14n)-(10n)-(0)) \ + pdej=12*2*(1)*2*((78n)-(14n)-(10n)-(0)) pdevdops=1 pdevlgeos=1 \ + pdevwgeos=1 psw_acv_sign=1 plnest=1 pldist=1 plorient=0 cpp=78n \ + fpitch=48n xpos=-99 ypos=-99 ptwell=0 sca=0 scb=0 scc=0 \ + pre_layout_local=1 ngcon=1 p_vta=0 p_la=0 u0mult_fet=1 lle_sa=71n \ + lle_sb=71n lle_rxrxa=78n lle_rxrxb=78n lle_rxrxn=192n \ + lle_rxrxs=192n lle_pcrxn=55n lle_pcrxs=55n lle_nwa=2u lle_nwb=2u \ + lle_nwn=192n lle_nws=192n lle_ctne=0 lle_ctnw=0 lle_ctse=0 \ + lle_ctsw=0 lle_sctne=0 lle_sctnw=0 lle_sctse=0 lle_sctsw=0 \ + lrsd=27n dtemp=0 l_shape=0 l_shape_s=0 nsig_dop1=0 nsig_dop2=0 \ + nsig_dibl=0 nsig_pc=0 nsig_rx=0 fc_index=0 fc_sigma=3 +N27 (net072 s3_ctle net070 0) nfet m=1 l=14n nfin=12 nf=4 par=(1) \ + par_nf=(1)*(4) asej=((54n)+(54n))*(11n)*12 + 12*1*(((78n)-(14n)-(10n)-(0))*(11n)) \ + adej=12*2*(((78n)-(14n)-(10n)-(0))*(11n)) psej=(1)*12*((54n)*2+(11n)+(54n)*2+(11n)) + 12*1*(1)*2*((78n)-(14n)-(10n)-(0)) \ + pdej=12*2*(1)*2*((78n)-(14n)-(10n)-(0)) pdevdops=1 pdevlgeos=1 \ + pdevwgeos=1 psw_acv_sign=1 plnest=1 pldist=1 plorient=0 cpp=78n \ + fpitch=48n xpos=-99 ypos=-99 ptwell=0 sca=0 scb=0 scc=0 \ + pre_layout_local=1 ngcon=1 p_vta=0 p_la=0 u0mult_fet=1 lle_sa=71n \ + lle_sb=71n lle_rxrxa=78n lle_rxrxb=78n lle_rxrxn=192n \ + lle_rxrxs=192n lle_pcrxn=55n lle_pcrxs=55n lle_nwa=2u lle_nwb=2u \ + lle_nwn=192n lle_nws=192n lle_ctne=0 lle_ctnw=0 lle_ctse=0 \ + lle_ctsw=0 lle_sctne=0 lle_sctnw=0 lle_sctse=0 lle_sctsw=0 \ + lrsd=27n dtemp=0 l_shape=0 l_shape_s=0 nsig_dop1=0 nsig_dop2=0 \ + nsig_dibl=0 nsig_pc=0 nsig_rx=0 fc_index=0 fc_sigma=3 +N26 (net071 s0_ctle net069 0) nfet m=1 l=14n nfin=12 nf=4 par=(1) \ + par_nf=(1)*(4) asej=((54n)+(54n))*(11n)*12 + 12*1*(((78n)-(14n)-(10n)-(0))*(11n)) \ + adej=12*2*(((78n)-(14n)-(10n)-(0))*(11n)) psej=(1)*12*((54n)*2+(11n)+(54n)*2+(11n)) + 12*1*(1)*2*((78n)-(14n)-(10n)-(0)) \ + pdej=12*2*(1)*2*((78n)-(14n)-(10n)-(0)) pdevdops=1 pdevlgeos=1 \ + pdevwgeos=1 psw_acv_sign=1 plnest=1 pldist=1 plorient=0 cpp=78n \ + fpitch=48n xpos=-99 ypos=-99 ptwell=0 sca=0 scb=0 scc=0 \ + pre_layout_local=1 ngcon=1 p_vta=0 p_la=0 u0mult_fet=1 lle_sa=71n \ + lle_sb=71n lle_rxrxa=78n lle_rxrxb=78n lle_rxrxn=192n \ + lle_rxrxs=192n lle_pcrxn=55n lle_pcrxs=55n lle_nwa=2u lle_nwb=2u \ + lle_nwn=192n lle_nws=192n lle_ctne=0 lle_ctnw=0 lle_ctse=0 \ + lle_ctsw=0 lle_sctne=0 lle_sctnw=0 lle_sctse=0 lle_sctsw=0 \ + lrsd=27n dtemp=0 l_shape=0 l_shape_s=0 nsig_dop1=0 nsig_dop2=0 \ + nsig_dibl=0 nsig_pc=0 nsig_rx=0 fc_index=0 fc_sigma=3 +N25 (net075 s0_ctle net071 0) nfet m=1 l=14n nfin=12 nf=4 par=(1) \ + par_nf=(1)*(4) asej=((54n)+(54n))*(11n)*12 + 12*1*(((78n)-(14n)-(10n)-(0))*(11n)) \ + adej=12*2*(((78n)-(14n)-(10n)-(0))*(11n)) psej=(1)*12*((54n)*2+(11n)+(54n)*2+(11n)) + 12*1*(1)*2*((78n)-(14n)-(10n)-(0)) \ + pdej=12*2*(1)*2*((78n)-(14n)-(10n)-(0)) pdevdops=1 pdevlgeos=1 \ + pdevwgeos=1 psw_acv_sign=1 plnest=1 pldist=1 plorient=0 cpp=78n \ + fpitch=48n xpos=-99 ypos=-99 ptwell=0 sca=0 scb=0 scc=0 \ + pre_layout_local=1 ngcon=1 p_vta=0 p_la=0 u0mult_fet=1 lle_sa=71n \ + lle_sb=71n lle_rxrxa=78n lle_rxrxb=78n lle_rxrxn=192n \ + lle_rxrxs=192n lle_pcrxn=55n lle_pcrxs=55n lle_nwa=2u lle_nwb=2u \ + lle_nwn=192n lle_nws=192n lle_ctne=0 lle_ctnw=0 lle_ctse=0 \ + lle_ctsw=0 lle_sctne=0 lle_sctnw=0 lle_sctse=0 lle_sctsw=0 \ + lrsd=27n dtemp=0 l_shape=0 l_shape_s=0 nsig_dop1=0 nsig_dop2=0 \ + nsig_dibl=0 nsig_pc=0 nsig_rx=0 fc_index=0 fc_sigma=3 +N24 (net076 s3_ctle net072 0) nfet m=1 l=14n nfin=12 nf=4 par=(1) \ + par_nf=(1)*(4) asej=((54n)+(54n))*(11n)*12 + 12*1*(((78n)-(14n)-(10n)-(0))*(11n)) \ + adej=12*2*(((78n)-(14n)-(10n)-(0))*(11n)) psej=(1)*12*((54n)*2+(11n)+(54n)*2+(11n)) + 12*1*(1)*2*((78n)-(14n)-(10n)-(0)) \ + pdej=12*2*(1)*2*((78n)-(14n)-(10n)-(0)) pdevdops=1 pdevlgeos=1 \ + pdevwgeos=1 psw_acv_sign=1 plnest=1 pldist=1 plorient=0 cpp=78n \ + fpitch=48n xpos=-99 ypos=-99 ptwell=0 sca=0 scb=0 scc=0 \ + pre_layout_local=1 ngcon=1 p_vta=0 p_la=0 u0mult_fet=1 lle_sa=71n \ + lle_sb=71n lle_rxrxa=78n lle_rxrxb=78n lle_rxrxn=192n \ + lle_rxrxs=192n lle_pcrxn=55n lle_pcrxs=55n lle_nwa=2u lle_nwb=2u \ + lle_nwn=192n lle_nws=192n lle_ctne=0 lle_ctnw=0 lle_ctse=0 \ + lle_ctsw=0 lle_sctne=0 lle_sctnw=0 lle_sctse=0 lle_sctsw=0 \ + lrsd=27n dtemp=0 l_shape=0 l_shape_s=0 nsig_dop1=0 nsig_dop2=0 \ + nsig_dibl=0 nsig_pc=0 nsig_rx=0 fc_index=0 fc_sigma=3 +N23 (net077 s1_ctle net073 0) nfet m=1 l=14n nfin=12 nf=4 par=(1) \ + par_nf=(1)*(4) asej=((54n)+(54n))*(11n)*12 + 12*1*(((78n)-(14n)-(10n)-(0))*(11n)) \ + adej=12*2*(((78n)-(14n)-(10n)-(0))*(11n)) psej=(1)*12*((54n)*2+(11n)+(54n)*2+(11n)) + 12*1*(1)*2*((78n)-(14n)-(10n)-(0)) \ + pdej=12*2*(1)*2*((78n)-(14n)-(10n)-(0)) pdevdops=1 pdevlgeos=1 \ + pdevwgeos=1 psw_acv_sign=1 plnest=1 pldist=1 plorient=0 cpp=78n \ + fpitch=48n xpos=-99 ypos=-99 ptwell=0 sca=0 scb=0 scc=0 \ + pre_layout_local=1 ngcon=1 p_vta=0 p_la=0 u0mult_fet=1 lle_sa=71n \ + lle_sb=71n lle_rxrxa=78n lle_rxrxb=78n lle_rxrxn=192n \ + lle_rxrxs=192n lle_pcrxn=55n lle_pcrxs=55n lle_nwa=2u lle_nwb=2u \ + lle_nwn=192n lle_nws=192n lle_ctne=0 lle_ctnw=0 lle_ctse=0 \ + lle_ctsw=0 lle_sctne=0 lle_sctnw=0 lle_sctse=0 lle_sctsw=0 \ + lrsd=27n dtemp=0 l_shape=0 l_shape_s=0 nsig_dop1=0 nsig_dop2=0 \ + nsig_dibl=0 nsig_pc=0 nsig_rx=0 fc_index=0 fc_sigma=3 +N20 (net078 s2_ctle net074 0) nfet m=1 l=14n nfin=12 nf=4 par=(1) \ + par_nf=(1)*(4) asej=((54n)+(54n))*(11n)*12 + 12*1*(((78n)-(14n)-(10n)-(0))*(11n)) \ + adej=12*2*(((78n)-(14n)-(10n)-(0))*(11n)) psej=(1)*12*((54n)*2+(11n)+(54n)*2+(11n)) + 12*1*(1)*2*((78n)-(14n)-(10n)-(0)) \ + pdej=12*2*(1)*2*((78n)-(14n)-(10n)-(0)) pdevdops=1 pdevlgeos=1 \ + pdevwgeos=1 psw_acv_sign=1 plnest=1 pldist=1 plorient=0 cpp=78n \ + fpitch=48n xpos=-99 ypos=-99 ptwell=0 sca=0 scb=0 scc=0 \ + pre_layout_local=1 ngcon=1 p_vta=0 p_la=0 u0mult_fet=1 lle_sa=71n \ + lle_sb=71n lle_rxrxa=78n lle_rxrxb=78n lle_rxrxn=192n \ + lle_rxrxs=192n lle_pcrxn=55n lle_pcrxs=55n lle_nwa=2u lle_nwb=2u \ + lle_nwn=192n lle_nws=192n lle_ctne=0 lle_ctnw=0 lle_ctse=0 \ + lle_ctsw=0 lle_sctne=0 lle_sctnw=0 lle_sctse=0 lle_sctsw=0 \ + lrsd=27n dtemp=0 l_shape=0 l_shape_s=0 nsig_dop1=0 nsig_dop2=0 \ + nsig_dibl=0 nsig_pc=0 nsig_rx=0 fc_index=0 fc_sigma=3 +N19 (net079 vin1 net052 0) nfet m=1 l=14n nfin=12 nf=4 par=(1) \ + par_nf=(1)*(4) asej=((54n)+(54n))*(11n)*12 + 12*1*(((78n)-(14n)-(10n)-(0))*(11n)) \ + adej=12*2*(((78n)-(14n)-(10n)-(0))*(11n)) psej=(1)*12*((54n)*2+(11n)+(54n)*2+(11n)) + 12*1*(1)*2*((78n)-(14n)-(10n)-(0)) \ + pdej=12*2*(1)*2*((78n)-(14n)-(10n)-(0)) pdevdops=1 pdevlgeos=1 \ + pdevwgeos=1 psw_acv_sign=1 plnest=1 pldist=1 plorient=0 cpp=78n \ + fpitch=48n xpos=-99 ypos=-99 ptwell=0 sca=0 scb=0 scc=0 \ + pre_layout_local=1 ngcon=1 p_vta=0 p_la=0 u0mult_fet=1 lle_sa=71n \ + lle_sb=71n lle_rxrxa=78n lle_rxrxb=78n lle_rxrxn=192n \ + lle_rxrxs=192n lle_pcrxn=55n lle_pcrxs=55n lle_nwa=2u lle_nwb=2u \ + lle_nwn=192n lle_nws=192n lle_ctne=0 lle_ctnw=0 lle_ctse=0 \ + lle_ctsw=0 lle_sctne=0 lle_sctnw=0 lle_sctse=0 lle_sctsw=0 \ + lrsd=27n dtemp=0 l_shape=0 l_shape_s=0 nsig_dop1=0 nsig_dop2=0 \ + nsig_dibl=0 nsig_pc=0 nsig_rx=0 fc_index=0 fc_sigma=3 +N18 (net080 net048 0 0) nfet m=1 l=14n nfin=12 nf=7 par=(1) par_nf=(1)*(7) \ + asej=(54n)*(11n)*12 + 12*3*(((78n)-(14n)-(10n)-(0))*(11n)) adej=(54n)*(11n)*12+3*(((78n)-(14n)-(10n)-(0))*(11n))*12 \ + psej=(1)*12*(2*(54n)+(11n)) + 12*3*(1)*2*((78n)-(14n)-(10n)-(0)) pdej=(1)*12*(2*(54n)+(11n)) + 12*3*(1)*2*((78n)-(14n)-(10n)-(0)) \ + pdevdops=1 pdevlgeos=1 pdevwgeos=1 psw_acv_sign=1 plnest=1 \ + pldist=1 plorient=0 cpp=78n fpitch=48n xpos=-99 ypos=-99 ptwell=0 \ + sca=0 scb=0 scc=0 pre_layout_local=1 ngcon=1 p_vta=0 p_la=0 \ + u0mult_fet=1 lle_sa=71n lle_sb=71n lle_rxrxa=78n lle_rxrxb=78n \ + lle_rxrxn=192n lle_rxrxs=192n lle_pcrxn=55n lle_pcrxs=55n \ + lle_nwa=2u lle_nwb=2u lle_nwn=192n lle_nws=192n lle_ctne=0 \ + lle_ctnw=0 lle_ctse=0 lle_ctsw=0 lle_sctne=0 lle_sctnw=0 \ + lle_sctse=0 lle_sctsw=0 lrsd=27n dtemp=0 l_shape=0 l_shape_s=0 \ + nsig_dop1=0 nsig_dop2=0 nsig_dibl=0 nsig_pc=0 nsig_rx=0 fc_index=0 \ + fc_sigma=3 +N17 (net052 net048 net080 0) nfet m=1 l=14n nfin=12 nf=7 par=(1) \ + par_nf=(1)*(7) asej=(54n)*(11n)*12 + 12*3*(((78n)-(14n)-(10n)-(0))*(11n)) \ + adej=(54n)*(11n)*12+3*(((78n)-(14n)-(10n)-(0))*(11n))*12 psej=(1)*12*(2*(54n)+(11n)) + 12*3*(1)*2*((78n)-(14n)-(10n)-(0)) \ + pdej=(1)*12*(2*(54n)+(11n)) + 12*3*(1)*2*((78n)-(14n)-(10n)-(0)) pdevdops=1 \ + pdevlgeos=1 pdevwgeos=1 psw_acv_sign=1 plnest=1 pldist=1 \ + plorient=0 cpp=78n fpitch=48n xpos=-99 ypos=-99 ptwell=0 sca=0 \ + scb=0 scc=0 pre_layout_local=1 ngcon=1 p_vta=0 p_la=0 \ + u0mult_fet=1 lle_sa=71n lle_sb=71n lle_rxrxa=78n lle_rxrxb=78n \ + lle_rxrxn=192n lle_rxrxs=192n lle_pcrxn=55n lle_pcrxs=55n \ + lle_nwa=2u lle_nwb=2u lle_nwn=192n lle_nws=192n lle_ctne=0 \ + lle_ctnw=0 lle_ctse=0 lle_ctsw=0 lle_sctne=0 lle_sctnw=0 \ + lle_sctse=0 lle_sctsw=0 lrsd=27n dtemp=0 l_shape=0 l_shape_s=0 \ + nsig_dop1=0 nsig_dop2=0 nsig_dibl=0 nsig_pc=0 nsig_rx=0 fc_index=0 \ + fc_sigma=3 +N16 (vout1_ctle vin1 net079 0) nfet m=1 l=14n nfin=12 nf=4 par=(1) \ + par_nf=(1)*(4) asej=((54n)+(54n))*(11n)*12 + 12*1*(((78n)-(14n)-(10n)-(0))*(11n)) \ + adej=12*2*(((78n)-(14n)-(10n)-(0))*(11n)) psej=(1)*12*((54n)*2+(11n)+(54n)*2+(11n)) + 12*1*(1)*2*((78n)-(14n)-(10n)-(0)) \ + pdej=12*2*(1)*2*((78n)-(14n)-(10n)-(0)) pdevdops=1 pdevlgeos=1 \ + pdevwgeos=1 psw_acv_sign=1 plnest=1 pldist=1 plorient=0 cpp=78n \ + fpitch=48n xpos=-99 ypos=-99 ptwell=0 sca=0 scb=0 scc=0 \ + pre_layout_local=1 ngcon=1 p_vta=0 p_la=0 u0mult_fet=1 lle_sa=71n \ + lle_sb=71n lle_rxrxa=78n lle_rxrxb=78n lle_rxrxn=192n \ + lle_rxrxs=192n lle_pcrxn=55n lle_pcrxs=55n lle_nwa=2u lle_nwb=2u \ + lle_nwn=192n lle_nws=192n lle_ctne=0 lle_ctnw=0 lle_ctse=0 \ + lle_ctsw=0 lle_sctne=0 lle_sctnw=0 lle_sctse=0 lle_sctsw=0 \ + lrsd=27n dtemp=0 l_shape=0 l_shape_s=0 nsig_dop1=0 nsig_dop2=0 \ + nsig_dibl=0 nsig_pc=0 nsig_rx=0 fc_index=0 fc_sigma=3 +N22 (net081 net048 0 0) nfet m=1 l=14n nfin=12 nf=7 par=(1) par_nf=(1)*(7) \ + asej=(54n)*(11n)*12 + 12*3*(((78n)-(14n)-(10n)-(0))*(11n)) adej=(54n)*(11n)*12+3*(((78n)-(14n)-(10n)-(0))*(11n))*12 \ + psej=(1)*12*(2*(54n)+(11n)) + 12*3*(1)*2*((78n)-(14n)-(10n)-(0)) pdej=(1)*12*(2*(54n)+(11n)) + 12*3*(1)*2*((78n)-(14n)-(10n)-(0)) \ + pdevdops=1 pdevlgeos=1 pdevwgeos=1 psw_acv_sign=1 plnest=1 \ + pldist=1 plorient=0 cpp=78n fpitch=48n xpos=-99 ypos=-99 ptwell=0 \ + sca=0 scb=0 scc=0 pre_layout_local=1 ngcon=1 p_vta=0 p_la=0 \ + u0mult_fet=1 lle_sa=71n lle_sb=71n lle_rxrxa=78n lle_rxrxb=78n \ + lle_rxrxn=192n lle_rxrxs=192n lle_pcrxn=55n lle_pcrxs=55n \ + lle_nwa=2u lle_nwb=2u lle_nwn=192n lle_nws=192n lle_ctne=0 \ + lle_ctnw=0 lle_ctse=0 lle_ctsw=0 lle_sctne=0 lle_sctnw=0 \ + lle_sctse=0 lle_sctsw=0 lrsd=27n dtemp=0 l_shape=0 l_shape_s=0 \ + nsig_dop1=0 nsig_dop2=0 nsig_dibl=0 nsig_pc=0 nsig_rx=0 fc_index=0 \ + fc_sigma=3 +N21 (net048 net048 net081 0) nfet m=1 l=14n nfin=12 nf=7 par=(1) \ + par_nf=(1)*(7) asej=(54n)*(11n)*12 + 12*3*(((78n)-(14n)-(10n)-(0))*(11n)) \ + adej=(54n)*(11n)*12+3*(((78n)-(14n)-(10n)-(0))*(11n))*12 psej=(1)*12*(2*(54n)+(11n)) + 12*3*(1)*2*((78n)-(14n)-(10n)-(0)) \ + pdej=(1)*12*(2*(54n)+(11n)) + 12*3*(1)*2*((78n)-(14n)-(10n)-(0)) pdevdops=1 \ + pdevlgeos=1 pdevwgeos=1 psw_acv_sign=1 plnest=1 pldist=1 \ + plorient=0 cpp=78n fpitch=48n xpos=-99 ypos=-99 ptwell=0 sca=0 \ + scb=0 scc=0 pre_layout_local=1 ngcon=1 p_vta=0 p_la=0 \ + u0mult_fet=1 lle_sa=71n lle_sb=71n lle_rxrxa=78n lle_rxrxb=78n \ + lle_rxrxn=192n lle_rxrxs=192n lle_pcrxn=55n lle_pcrxs=55n \ + lle_nwa=2u lle_nwb=2u lle_nwn=192n lle_nws=192n lle_ctne=0 \ + lle_ctnw=0 lle_ctse=0 lle_ctsw=0 lle_sctne=0 lle_sctnw=0 \ + lle_sctse=0 lle_sctsw=0 lrsd=27n dtemp=0 l_shape=0 l_shape_s=0 \ + nsig_dop1=0 nsig_dop2=0 nsig_dibl=0 nsig_pc=0 nsig_rx=0 fc_index=0 \ + fc_sigma=3 +R13 (net069 net055) metalres w=32n l=40.144u metLayer=15 +R12 (net070 net055) metalres w=32n l=40.144u metLayer=15 +R11 (vout2_ctle vdd!) metalres w=32n l=73.626u metLayer=15 +R10 (net052 net075) metalres w=32n l=40.144u metLayer=15 +R9 (net052 net076) metalres w=32n l=40.144u metLayer=15 +R2 (vout1_ctle vdd!) metalres w=32n l=73.626u metLayer=15 +C11 (net055 net068) apmom1v2 m=1 w=5.724u l=3.2u botlev=1 toplev=3 par=(1) +C10 (net055 net067) apmom1v2 m=1 w=5.724u l=3.2u botlev=1 toplev=3 par=(1) +C9 (net052 net077) apmom1v2 m=1 w=5.724u l=3.2u botlev=1 toplev=3 par=(1) +C0 (net052 net078) apmom1v2 m=1 w=5.724u l=3.2u botlev=1 toplev=3 par=(1) +simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=27 \ + tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \ + digits=5 cols=80 pivrel=1e-3 sensfile="../psf/sens.output" \ + checklimitdest=psf +dcOp dc write="spectre.dc" maxiters=150 maxsteps=10000 annotate=status +dcOpInfo info what=oppoint where=rawfile +tran tran stop=10n errpreset=conservative write="spectre.ic" \ + writefinal="spectre.fc" annotate=status maxiters=5 +finalTimeOP info what=oppoint where=rawfile +ac ac start=10000 stop=100G dec=10 annotate=status +modelParameter info what=models where=rawfile +element info what=inst where=rawfile +outputParameter info what=output where=rawfile +designParamVals info what=parameters where=rawfile +primitives info what=primitives where=rawfile +subckts info what=subckts where=rawfile +saveOptions options save=allpub diff --git a/CircuitsDatabase/Sized netlists/Wireline/linear_equalizer_4_level/ctle_align.sp b/CircuitsDatabase/Sized netlists/Wireline/linear_equalizer_4_level/ctle_align.sp new file mode 100644 index 0000000000..9708174a1c --- /dev/null +++ b/CircuitsDatabase/Sized netlists/Wireline/linear_equalizer_4_level/ctle_align.sp @@ -0,0 +1,35 @@ + + +.subckt gain_control_block s0 s1 s2 s3 n1 n2 vgnd + R2 n1 n3 resistor r=1000 + R3 n4 n2 resistor r=1000 + R4 n1 n5 resistor r=1000 + R5 n6 n2 resistor r=1000 + R6 n1 n7 resistor r=1000 + R7 n8 n2 resistor r=1000 + R8 n1 n9 resistor r=1000 + R9 n10 n2 resistor r=1000 + MN5 n3 s0 n4 vgnd nfet l=14e-9 nfin=48 + MN6 n5 s1 n6 vgnd nfet l=14e-9 nfin=48 + MN7 n7 s2 n8 vgnd nfet l=14e-9 nfin=48 + MN8 n9 s3 n10 vgnd nfet l=14e-9 nfin=48 +.ends gain_control_block + +.subckt CMB2_ctle_align d1 d2 s b + MN0 d1 d1 s b nfet l=14e-9 nfin=84 + MN1 d2 d1 s b nfet l=14e-9 nfin=84 +.ends CMB2_ctle_align + +.subckt CMB3_ctle_align d1 d2 d3 s b + xI0 d1 d2 s b CMB2_ctle_align + MN2 d3 d1 s b nfet l=14e-9 nfin=84 +.ends CMB3_ctle_align + +.subckt ctle_align vmirror s0 s1 s2 s3 vin1 vin2 vout1 vout2 vps vgnd + MN0 vout2 vin2 n1 vgnd nfet l=14e-9 nfin=48 + MN1 vout1 vin1 n2 vgnd nfet l=14e-9 nfin=48 + R0 vps vout1 resistor r=2000 + R1 vps vout2 resistor r=2000 + xI0 s0 s1 s2 s3 n1 n2 vgnd gain_control_block + xI1 vmirror n1 n2 vgnd vgnd CMB3_ctle_align +.ends ctle_align diff --git a/CircuitsDatabase/Sized netlists/Wireline/linear_equalizer_4_level/ctle_layout.tiff b/CircuitsDatabase/Sized netlists/Wireline/linear_equalizer_4_level/ctle_layout.tiff new file mode 100644 index 0000000000..858f3af62f Binary files /dev/null and b/CircuitsDatabase/Sized netlists/Wireline/linear_equalizer_4_level/ctle_layout.tiff differ diff --git a/CircuitsDatabase/Sized netlists/Wireline/linear_equalizer_4_level/ctle_schematic.tiff b/CircuitsDatabase/Sized netlists/Wireline/linear_equalizer_4_level/ctle_schematic.tiff new file mode 100644 index 0000000000..986fe24936 Binary files /dev/null and b/CircuitsDatabase/Sized netlists/Wireline/linear_equalizer_4_level/ctle_schematic.tiff differ diff --git a/CircuitsDatabase/Sized netlists/Wireline/transimpedance_amplifier/TIA_layout.tiff b/CircuitsDatabase/Sized netlists/Wireline/transimpedance_amplifier/TIA_layout.tiff new file mode 100644 index 0000000000..5a3d321b73 Binary files /dev/null and b/CircuitsDatabase/Sized netlists/Wireline/transimpedance_amplifier/TIA_layout.tiff differ diff --git a/CircuitsDatabase/Sized netlists/Wireline/transimpedance_amplifier/TIA_schematic.tiff b/CircuitsDatabase/Sized netlists/Wireline/transimpedance_amplifier/TIA_schematic.tiff new file mode 100644 index 0000000000..c7ae41107f Binary files /dev/null and b/CircuitsDatabase/Sized netlists/Wireline/transimpedance_amplifier/TIA_schematic.tiff differ diff --git a/CircuitsDatabase/Sized netlists/Wireline/transimpedance_amplifier/transimpedance_amplifier.sp b/CircuitsDatabase/Sized netlists/Wireline/transimpedance_amplifier/transimpedance_amplifier.sp new file mode 100644 index 0000000000..7de6ea4435 --- /dev/null +++ b/CircuitsDatabase/Sized netlists/Wireline/transimpedance_amplifier/transimpedance_amplifier.sp @@ -0,0 +1,6 @@ + +.subckt transimpedance_amplifier vgnd vin vout vps + MN0 vout vin vgnd vgnd nfet l=14e-9 nfin=15 + MP0 vout vin vps vps pfet l=14e-9 nfin=15 + R0 vin vout resistor r=100 +.ends transimpedance_amplifier diff --git a/CircuitsDatabase/Sized netlists/Wireline/variable_gain_amplifier/variable_gain_amplifier.sp b/CircuitsDatabase/Sized netlists/Wireline/variable_gain_amplifier/variable_gain_amplifier.sp new file mode 100644 index 0000000000..eeb77bbd0a --- /dev/null +++ b/CircuitsDatabase/Sized netlists/Wireline/variable_gain_amplifier/variable_gain_amplifier.sp @@ -0,0 +1,13 @@ + +.subckt variable_gain_amplifier s0 vmirror vin1 vin2 vout1 vout2 vps vgnd + MN3 vmirror vmirror vgnd vgnd nfet l=14e-9 nfin=96 + MN2 net3 vmirror vgnd vgnd nfet l=14e-9 nfin=96 + MN1 vout2 vin2 net3 vgnd nfet l=14e-9 nfin=36 + MN0 vout1 vin1 net3 vgnd nfet l=14e-9 nfin=36 + MN4 net4p vmirror vgnd vgnd nfet l=14e-9 nfin=96 + MN5 vout2 vin2 net4 vgnd nfet l=14e-9 nfin=36 + MN6 vout1 vin1 net4 vgnd nfet l=14e-9 nfin=36 + MN7 net4 s0 net4p vgnd nfet l=14e-9 nfin=36 + R5 vps vout2 resistor r=400 + R6 vps vout1 resistor r=400 +.ends variable_gain_amplifier diff --git a/CircuitsDatabase/Sized netlists/Wireline/variable_gain_amplifier/variable_gain_amplifier_top.sp b/CircuitsDatabase/Sized netlists/Wireline/variable_gain_amplifier/variable_gain_amplifier_top.sp new file mode 100644 index 0000000000..5caa856a8b --- /dev/null +++ b/CircuitsDatabase/Sized netlists/Wireline/variable_gain_amplifier/variable_gain_amplifier_top.sp @@ -0,0 +1,121 @@ +// Generated for: spectre +// Generated on: Jan 2 11:59:36 2020 +// Design library name: Optical_receiver +// Design cell name: VGA_top +// Design view name: schematic +simulator lang=spectre +global 0 vdd! + + +parameters vs2=0 nfpf_vga_sw=80 vs0=850m cload=10f ib_vga=250u \ + rload_vga=400 vbias=600m vps=0.85 wireopt=9 + +// Library name: Optical_receiver +// Cell name: VGA_top +// View name: schematic +R3 (vout2 vdd!) metalres w=32n l=15.904u metLayer=15 +R2 (vout1 vdd!) metalres w=32n l=15.904u metLayer=15 +N230 (vout1 vin1 net0308 0) nfet m=1 l=14n nfin=12 nf=1 +N229 (vout1 vin1 net0310 0) nfet m=1 l=14n nfin=12 nf=1 +N228 (vout2 vin2 net0307 0) nfet m=1 l=14n nfin=12 nf=1 +N227 (vout2 vin2 net0305 0) nfet m=1 l=14n nfin=12 nf=1 +N226 (vout2 vin2 net0306 0) nfet m=1 l=14n nfin=12 nf=1 ß +N225 (vout1 vin1 net0309 0) nfet m=1 l=14n nfin=12 nf=1 +N224 (vout2 vin2 net0300 0) nfet m=1 l=14n nfin=12 nf=1 +N223 (vout2 vin2 net0299 0) nfet m=1 l=14n nfin=12 nf=1 +N222 (vout2 vin2 net0301 0) nfet m=1 l=14n nfin=12 nf=1 +N221 (vout1 vin1 net0302 0) nfet m=1 l=14n nfin=12 nf=1 +N220 (vout1 vin1 net0304 0) nfet m=1 l=14n nfin=12 nf=1 +N219 (vout1 vin1 net0303 0) nfet m=1 l=14n nfin=12 nf=1 +N218 (net0309 vin1 net0273 0) nfet m=1 l=14n nfin=12 nf=1 +N217 (net0310 vin1 net0273 0) nfet m=1 l=14n nfin=12 nf=1 +N216 (net0308 vin1 net0273 0) nfet m=1 l=14n nfin=12 nf=1 +N215 (net0307 vin2 net0273 0) nfet m=1 l=14n nfin=12 nf=1 +N214 (net0306 vin2 net0273 0) nfet m=1 l=14n nfin=12 nf=1 +N213 (net0305 vin2 net0273 0) nfet m=1 l=14n nfin=12 nf=1 +N212 (net0302 vin1 net0295 0) nfet m=1 l=14n nfin=12 nf=1 +N211 (net0303 vin1 net0295 0) nfet m=1 l=14n nfin=12 nf=1 +N210 (net0304 vin1 net0295 0) nfet m=1 l=14n nfin=12 nf=1 +N209 (net0299 vin2 net0295 0) nfet m=1 l=14n nfin=12 nf=1 +N208 (net0300 vin2 net0295 0) nfet m=1 l=14n nfin=12 nf=1 +N207 (net0301 vin2 net0295 0) nfet m=1 l=14n nfin=12 nf=1 +N206 (net0295 s0 net0311 0) nfet m=1 l=14n nfin=12 nf=1 +N205 (net0295 s0 net0312 0) nfet m=1 l=14n nfin=12 nf=1 +N204 (net0295 s0 net0313 0) nfet m=1 l=14n nfin=12 nf=1 +N203 (net0311 s0 net0288 0) nfet m=1 l=14n nfin=12 nf=1 +N202 (net0312 s0 net0288 0) nfet m=1 l=14n nfin=12 nf=1 +N201 (net0313 s0 net0288 0) nfet m=1 l=14n nfin=12 nf=1 +N200 (net0273 net0252 net0323 0) nfet m=1 l=14n nfin=12 nf=1 +N199 (net0273 net0252 net0324 0) nfet m=1 l=14n nfin=12 nf=1 +N198 (net0273 net0252 net0325 0) nfet m=1 l=14n nfin=12 nf=1 +N197 (net0273 net0252 net0326 0) nfet m=1 l=14n nfin=12 nf=1 +N196 (net0273 net0252 net0327 0) nfet m=1 l=14n nfin=12 nf=1 +N195 (net0273 net0252 net0328 0) nfet m=1 l=14n nfin=12 nf=1 +N194 (net0273 net0252 net0329 0) nfet m=1 l=14n nfin=12 nf=1 +N193 (net0273 net0252 net0330 0) nfet m=1 l=14n nfin=12 nf=1 +N192 (net0288 net0252 net0316 0) nfet m=1 l=14n nfin=12 nf=1 +N191 (net0288 net0252 net0317 0) nfet m=1 l=14n nfin=12 nf=1 +N190 (net0288 net0252 net0318 0) nfet m=1 l=14n nfin=12 nf=1 +N189 (net0288 net0252 net0319 0) nfet m=1 l=14n nfin=12 nf=1 +N188 (net0288 net0252 net0320 0) nfet m=1 l=14n nfin=12 nf=1 +N187 (net0288 net0252 net0321 0) nfet m=1 l=14n nfin=12 nf=1 +N186 (net0288 net0252 net0322 0) nfet m=1 l=14n nfin=12 nf=1 +N185 (net0288 net0252 net0315 0) nfet m=1 l=14n nfin=12 nf=1 +N184 (net0252 net0252 net0338 0) nfet m=1 l=14n nfin=12 nf=1 +N183 (net0252 net0252 net0336 0) nfet m=1 l=14n nfin=12 nf=1 +N182 (net0252 net0252 net0337 0) nfet m=1 l=14n nfin=12 nf=1 +N181 (net0252 net0252 net0331 0) nfet m=1 l=14n nfin=12 nf=1 +N180 (net0252 net0252 net0332 0) nfet m=1 l=14n nfin=12 nf=1 +N179 (net0252 net0252 net0333 0) nfet m=1 l=14n nfin=12 nf=1 +N178 (net0252 net0252 net0334 0) nfet m=1 l=14n nfin=12 nf=1 +N177 (net0252 net0252 net0335 0) nfet m=1 l=14n nfin=12 nf=1 +N176 (net0323 net0252 0 0) nfet m=1 l=14n nfin=12 nf=1 +N175 (net0324 net0252 0 0) nfet m=1 l=14n nfin=12 nf=1 +N174 (net0325 net0252 0 0) nfet m=1 l=14n nfin=12 nf=1 +N173 (net0326 net0252 0 0) nfet m=1 l=14n nfin=12 nf=1 +N172 (net0327 net0252 0 0) nfet m=1 l=14n nfin=12 nf=1 +N171 (net0328 net0252 0 0) nfet m=1 l=14n nfin=12 nf=1 +N170 (net0329 net0252 0 0) nfet m=1 l=14n nfin=12 nf=1 +N169 (net0330 net0252 0 0) nfet m=1 l=14n nfin=12 nf=1 +N168 (net0315 net0252 0 0) nfet m=1 l=14n nfin=12 nf=1 +N167 (net0316 net0252 0 0) nfet m=1 l=14n nfin=12 nf=1 +N166 (net0317 net0252 0 0) nfet m=1 l=14n nfin=12 nf=1 +N165 (net0318 net0252 0 0) nfet m=1 l=14n nfin=12 nf=1 +N164 (net0319 net0252 0 0) nfet m=1 l=14n nfin=12 nf=1 +N163 (net0320 net0252 0 0) nfet m=1 l=14n nfin=12 nf=1 +N162 (net0321 net0252 0 0) nfet m=1 l=14n nfin=12 nf=1 +N161 (net0322 net0252 0 0) nfet m=1 l=14n nfin=12 nf=1 +N160 (net0331 net0252 0 0) nfet m=1 l=14n nfin=12 nf=1 +N159 (net0332 net0252 0 0) nfet m=1 l=14n nfin=12 nf=1 +N158 (net0333 net0252 0 0) nfet m=1 l=14n nfin=12 nf=1 +N157 (net0334 net0252 0 0) nfet m=1 l=14n nfin=12 nf=1 +N156 (net0335 net0252 0 0) nfet m=1 l=14n nfin=12 nf=1 +N155 (net0338 net0252 0 0) nfet m=1 l=14n nfin=12 nf=1 +N154 (net0337 net0252 0 0) nfet m=1 l=14n nfin=12 nf=1 +N153 (net0336 net0252 0 0) nfet m=1 l=14n nfin=12 nf=1 +V1 (vdd! 0) vsource dc=vps type=dc +V0 (vb_vga 0) vsource dc=vbias type=dc +V3 (s0 0) vsource dc=vs0 type=dc +C2 (vout2 0) capacitor c=cload +C1 (vout1 0) capacitor c=cload +V2 (vac 0) vsource dc=0 mag=1 type=sine ampl=100m freq=1G +E2 (vin2 vb_vga vac 0) vcvs gain=-1 +E0 (vin1 vb_vga vac 0) vcvs gain=1 +I11 (vdd! net0252) isource dc=ib_vga type=dc +simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=27 \ + tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \ + digits=5 cols=80 pivrel=1e-3 sensfile="../psf/sens.output" \ + checklimitdest=psf +dcOp dc write="spectre.dc" maxiters=150 maxsteps=10000 annotate=status +dcOpInfo info what=oppoint where=rawfile +ac ac start=100k stop=100G dec=10 annotate=status +tran tran stop=10n errpreset=conservative write="spectre.ic" \ + writefinal="spectre.fc" annotate=status maxiters=5 +finalTimeOP info what=oppoint where=rawfile +modelParameter info what=models where=rawfile +element info what=inst where=rawfile +outputParameter info what=output where=rawfile +designParamVals info what=parameters where=rawfile +primitives info what=primitives where=rawfile +subckts info what=subckts where=rawfile +saveOptions options save=allpub diff --git a/CircuitsDatabase/Sized netlists/Wireline/variable_gain_amplifier/vga_layout.tiff b/CircuitsDatabase/Sized netlists/Wireline/variable_gain_amplifier/vga_layout.tiff new file mode 100644 index 0000000000..d4a4a17d0b Binary files /dev/null and b/CircuitsDatabase/Sized netlists/Wireline/variable_gain_amplifier/vga_layout.tiff differ diff --git a/CircuitsDatabase/Sized netlists/Wireline/variable_gain_amplifier/vga_schematic.tiff b/CircuitsDatabase/Sized netlists/Wireline/variable_gain_amplifier/vga_schematic.tiff new file mode 100644 index 0000000000..f7b0c41e20 Binary files /dev/null and b/CircuitsDatabase/Sized netlists/Wireline/variable_gain_amplifier/vga_schematic.tiff differ diff --git a/CircuitsDatabase/Sized netlists/Wireline/variable_gain_amplifier_3_stage/VGA_3_stage_layout.tiff b/CircuitsDatabase/Sized netlists/Wireline/variable_gain_amplifier_3_stage/VGA_3_stage_layout.tiff new file mode 100644 index 0000000000..3e551f0a95 Binary files /dev/null and b/CircuitsDatabase/Sized netlists/Wireline/variable_gain_amplifier_3_stage/VGA_3_stage_layout.tiff differ diff --git a/CircuitsDatabase/Sized netlists/Wireline/variable_gain_amplifier_3_stage/VGA_3_stage_schematic.tiff b/CircuitsDatabase/Sized netlists/Wireline/variable_gain_amplifier_3_stage/VGA_3_stage_schematic.tiff new file mode 100644 index 0000000000..085d187d2d Binary files /dev/null and b/CircuitsDatabase/Sized netlists/Wireline/variable_gain_amplifier_3_stage/VGA_3_stage_schematic.tiff differ diff --git a/CircuitsDatabase/Sized netlists/Wireline/variable_gain_amplifier_3_stage/variable_gain_amplifier_3_stage.sp b/CircuitsDatabase/Sized netlists/Wireline/variable_gain_amplifier_3_stage/variable_gain_amplifier_3_stage.sp new file mode 100644 index 0000000000..46f8b51730 --- /dev/null +++ b/CircuitsDatabase/Sized netlists/Wireline/variable_gain_amplifier_3_stage/variable_gain_amplifier_3_stage.sp @@ -0,0 +1,17 @@ + +.subckt vga_align s0 s1 vmirror vin1 vin2 vout1 vout2 vps vgnd + MN3 vmirror vmirror vgnd vgnd nfet l=14e-9 nfin=84 + MN2 net3 vmirror vgnd vgnd nfet l=14e-9 nfin=84 + MN1 vout2 vin2 net3 vgnd nfet l=14e-9 nfin=48 + MN0 vout1 vin1 net3 vgnd nfet l=14e-9 nfin=48 + MN4 net4p vmirror vgnd vgnd nfet l=14e-9 nfin=84 + MN5 vout2 vin2 net4 vgnd nfet l=14e-9 nfin=48 + MN6 vout1 vin1 net4 vgnd nfet l=14e-9 nfin=48 + MN7 net4 s0 net4p vgnd nfet l=14e-9 nfin=48 + MN8 net5p vmirror vgnd vgnd nfet l=14e-9 nfin=84 + MN9 vout2 vin2 net5 vgnd nfet l=14e-9 nfin=48 + MN10 vout1 vin1 net5 vgnd nfet l=14e-9 nfin=48 + MN11 net5 s1 net5p vgnd nfet l=14e-9 nfin=48 + R5 vps vout2 resistor r=400 + R6 vps vout1 resistor r=400 +.ends vga_align diff --git a/DesignDatabase/Design Examples Library/Analog/A1/Netlist/A1 b/DesignDatabase/Design Examples Library/Analog/A1/Netlist/A1 deleted file mode 100644 index ec24d48480..0000000000 --- a/DesignDatabase/Design Examples Library/Analog/A1/Netlist/A1 +++ /dev/null @@ -1,36 +0,0 @@ -// Generated for: spectre -// Generated on: Nov 2 11:59:19 2018 -// Design library name: DC_converter -// Design cell name: -//2018_11_2_fully_diff_cascoded_current_mirror_ota_symbol_database -// Design view name: schematic -simulator lang=spectre -global 0 vdd! - -// Library name: DC_converter -// Cell name: -//2018_11_2_fully_diff_cascoded_current_mirror_ota_symbol_database -// View name: schematic -M15 (net020 Vbiasp net021 net021) pch l=130.0n w=3u m=1 nf=1 -M14 (net010 Vbiasp net013 net013) pch l=130.0n w=3u m=1 nf=1 -M5 (Voutn Vbiasp net6 net6) pch l=200n w=12.305u m=1 nf=1 -M4 (net6 net010 vdd! vdd!) pch l=200n w=10.77u m=1 nf=1 -M3 (Voutp Vbiasp net23 net23) pch l=200n w=12.305u m=1 nf=1 -M2 (net23 net020 vdd! vdd!) pch l=200n w=10.77u m=1 nf=1 -M1 (net021 net020 vdd! vdd!) pch l=130.0n w=4.25u m=1 nf=1 -M0 (net013 net010 vdd! vdd!) pch l=130.0n w=4.25u m=1 nf=1 -M13 (net11 net11 0 0) nch l=130.0n w=2u m=1 nf=1 -M12 (net17 net11 0 0) nch l=130.0n w=2u m=1 nf=1 -M11 (Voutp Vbiasn net38 0) nch l=200n w=10.9u m=1 nf=1 -M10 (net38 Vbiasnd 0 0) nch l=300n w=11.5u m=1 nf=1 -M9 (Voutn Vbiasn net39 0) nch l=200n w=10.9u m=1 nf=1 -M8 (net39 Vbiasnd 0 0) nch l=300n w=11.5u m=1 nf=1 -M7 (net020 Vinp net17 0) nch l=130.0n w=3.56u m=1 nf=1 -M6 (net010 Vinn net17 0) nch l=130.0n w=3.56u m=1 nf=1 -I4 (vdd! net11) isource dc=200u type=dc -V2 (Vbiascmfb 0) vsource dc=449m type=dc -V1 (Vbiasn 0) vsource dc=700m type=dc -V0 (Vbiasp 0) vsource dc=410m type=dc -C1 (Voutp Vbiasnd) capacitor c=10f -C0 (Voutn Vbiasnd) capacitor c=10f - diff --git a/DesignDatabase/Design Examples Library/Analog/A1/README.md b/DesignDatabase/Design Examples Library/Analog/A1/README.md deleted file mode 100644 index d1f0fcbca1..0000000000 --- a/DesignDatabase/Design Examples Library/Analog/A1/README.md +++ /dev/null @@ -1,13 +0,0 @@ -Fully differential current mirror OTA - -Files present: - -1. Netlist with sizing - -To be added - -- Schematic snapshot - -- Layout snapshot - -- Testbench diff --git a/DesignDatabase/Design Examples Library/Analog/A2/Layout/A2_image.png b/DesignDatabase/Design Examples Library/Analog/A2/Layout/A2_image.png deleted file mode 100644 index c234340038..0000000000 Binary files a/DesignDatabase/Design Examples Library/Analog/A2/Layout/A2_image.png and /dev/null differ diff --git a/DesignDatabase/Design Examples Library/Analog/A2/Netlist/A2 b/DesignDatabase/Design Examples Library/Analog/A2/Netlist/A2 deleted file mode 100644 index 574cb13260..0000000000 --- a/DesignDatabase/Design Examples Library/Analog/A2/Netlist/A2 +++ /dev/null @@ -1,34 +0,0 @@ -// Generated for: spectre -// Generated on: Nov 2 10:37:45 2018 -// Design library name: DC_converter -// Design cell name: 23Dec_2017_comparator_symbol -// Design view name: schematic -simulator lang=spectre -global 0 - -// Library name: DC_converter -// Cell name: 23Dec_2017_comparator_symbol -// View name: schematic -M21 (net44 cgnd Vdd Vdd) pch l=1.32u w=120.0n m=1 nf=1 -M5 (net10 Vn net7 cgnd) nmos_rf lr=120.0n wr=600n nr=1 -M0 (net5 Vp net7 cgnd) nmos_rf lr=120.0n wr=600n nr=1 -M11 (net7 net44 cgnd cgnd) nmos_rf lr=120.0n wr=1.2u nr=1 -M9 (net44 net44 cgnd cgnd) nmos_rf lr=120.0n wr=600n nr=1 -M10 (Vop Von net18 cgnd) nmos_rf lr=120.0n wr=600n nr=1 -M8 (Von Vop net18 cgnd) nmos_rf lr=120.0n wr=600n nr=1 -M7 (Von Von net18 cgnd) nmos_rf lr=120.0n wr=600n nr=1 -M6 (Vop Vop net18 cgnd) nmos_rf lr=120.0n wr=600n nr=1 -M20 (net18 net18 cgnd cgnd) nmos_rf lr=120.0n wr=6u nr=1 -M18 (net17 net13 cgnd cgnd) nmos_rf lr=120.0n wr=600n nr=1 -M16 (Vout net23 cgnd cgnd) nmos_rf lr=120.0n wr=600n nr=1 -M14 (net23 Vop net17 cgnd) nmos_rf lr=120.0n wr=600n nr=1 -M12 (net13 Von net17 cgnd) nmos_rf lr=120.0n wr=600n nr=1 -M3 (Vop net5 Vdd Vdd) pmos_rf lr=240.0n wr=1.8u nr=1 -M2 (net5 net5 Vdd Vdd) pmos_rf lr=240.0n wr=1.8u nr=1 -M4 (Von net10 Vdd Vdd) pmos_rf lr=240.0n wr=1.8u nr=1 -M1 (net10 net10 Vdd Vdd) pmos_rf lr=240.0n wr=1.8u nr=1 -M19 (net14 net13 Vdd Vdd) pmos_rf lr=120.0n wr=900n nr=1 -M17 (Vout net23 Vdd Vdd) pmos_rf lr=120.0n wr=900n nr=1 -M15 (net23 Vop net14 net14) pmos_rf lr=120.0n wr=900n nr=1 -M13 (net13 Von net14 net14) pmos_rf lr=120.0n wr=900n nr=1 - diff --git a/DesignDatabase/Design Examples Library/Analog/A2/README.md b/DesignDatabase/Design Examples Library/Analog/A2/README.md deleted file mode 100644 index f2d658e4aa..0000000000 --- a/DesignDatabase/Design Examples Library/Analog/A2/README.md +++ /dev/null @@ -1,14 +0,0 @@ -Comparator (not clocked) - -Files present: - -1. Netlist with sizing - -2. Schematic snapshot - -3. Layout snapshot - -4. Testbench - a. Netlist - b. Performance specifications - c. Constraints diff --git a/DesignDatabase/Design Examples Library/Analog/A2/Schematic/A2_image.png b/DesignDatabase/Design Examples Library/Analog/A2/Schematic/A2_image.png deleted file mode 100644 index 4c32eb0779..0000000000 Binary files a/DesignDatabase/Design Examples Library/Analog/A2/Schematic/A2_image.png and /dev/null differ diff --git a/DesignDatabase/Design Examples Library/Analog/A2/Testbench/Constraints/A2_constraints.txt b/DesignDatabase/Design Examples Library/Analog/A2/Testbench/Constraints/A2_constraints.txt deleted file mode 100644 index a8b39e4146..0000000000 --- a/DesignDatabase/Design Examples Library/Analog/A2/Testbench/Constraints/A2_constraints.txt +++ /dev/null @@ -1,11 +0,0 @@ -Constraints for the comparator circuit - -Initial pre-amplifier stage -- matching between the differential pair and current mirror -- symmetry - -Decision making stage -- symmetry - -Output buffer -- None \ No newline at end of file diff --git a/DesignDatabase/Design Examples Library/Analog/A2/Testbench/Netlist/A2_testbench.txt b/DesignDatabase/Design Examples Library/Analog/A2/Testbench/Netlist/A2_testbench.txt deleted file mode 100644 index 10d402ba50..0000000000 --- a/DesignDatabase/Design Examples Library/Analog/A2/Testbench/Netlist/A2_testbench.txt +++ /dev/null @@ -1,70 +0,0 @@ -// Generated for: spectre -// Generated on: Apr 28 17:49:09 2019 -// Design library name: DC_converter -// Design cell name: 2019_04_28_comparator_testbench -// Design view name: schematic -simulator lang=spectre -global 0 - -// Library name: DC_converter -// Cell name: 23Dec_2017_comparator_symbol -// View name: schematic -subckt DC_converter_23Dec_2017_comparator_symbol_schematic Vn Vout Vp Vdd \ - cgnd - M21 (net44 cgnd Vdd Vdd) pch l=1.32u w=120.0n m=1 nf=1 - - - M5 (net10 Vn net7 cgnd) nmos_rf lr=120.0n wr=600n nr=1 sigma=1 m=1 - - M0 (net5 Vp net7 cgnd) nmos_rf lr=120.0n wr=600n nr=1 sigma=1 m=1 - - M11 (net7 net44 cgnd cgnd) nmos_rf lr=120.0n wr=1.2u nr=1 sigma=1 m=1 - - M9 (net44 net44 cgnd cgnd) nmos_rf lr=120.0n wr=600n nr=1 sigma=1 m=1 - - M10 (Vop Von net18 cgnd) nmos_rf lr=120.0n wr=600n nr=1 sigma=1 m=1 - - M8 (Von Vop net18 cgnd) nmos_rf lr=120.0n wr=600n nr=1 sigma=1 m=1 - - M7 (Von Von net18 cgnd) nmos_rf lr=120.0n wr=600n nr=1 sigma=1 m=1 - - M6 (Vop Vop net18 cgnd) nmos_rf lr=120.0n wr=600n nr=1 sigma=1 m=1 - - M20 (net18 net18 cgnd cgnd) nmos_rf lr=120.0n wr=6u nr=1 sigma=1 m=1 - - M18 (net17 net13 cgnd cgnd) nmos_rf lr=120.0n wr=600n nr=1 sigma=1 m=1 - - M16 (Vout net23 cgnd cgnd) nmos_rf lr=120.0n wr=600n nr=1 sigma=1 m=1 - - M14 (net23 Vop net17 cgnd) nmos_rf lr=120.0n wr=600n nr=1 sigma=1 m=1 - - M12 (net13 Von net17 cgnd) nmos_rf lr=120.0n wr=600n nr=1 sigma=1 m=1 - - M3 (Vop net5 Vdd Vdd) pmos_rf lr=240.0n wr=1.8u nr=1 sigma=1 m=1 - - M2 (net5 net5 Vdd Vdd) pmos_rf lr=240.0n wr=1.8u nr=1 sigma=1 m=1 - - M4 (Von net10 Vdd Vdd) pmos_rf lr=240.0n wr=1.8u nr=1 sigma=1 m=1 - - M1 (net10 net10 Vdd Vdd) pmos_rf lr=240.0n wr=1.8u nr=1 sigma=1 m=1 - - M19 (net14 net13 Vdd Vdd) pmos_rf lr=120.0n wr=900n nr=1 sigma=1 m=1 - - M17 (Vout net23 Vdd Vdd) pmos_rf lr=120.0n wr=900n nr=1 sigma=1 m=1 - - M15 (net23 Vop net14 net14) pmos_rf lr=120.0n wr=900n nr=1 sigma=1 m=1 - - M13 (net13 Von net14 net14) pmos_rf lr=120.0n wr=900n nr=1 sigma=1 m=1 - -ends DC_converter_23Dec_2017_comparator_symbol_schematic -// End of subcircuit definition. - -// Library name: DC_converter -// Cell name: 2019_04_28_comparator_testbench -// View name: schematic -I0 (vn vout vp vdd vss) DC_converter_23Dec_2017_comparator_symbol_schematic -V3 (vss 0) vsource dc=0 type=dc -V2 (vp 0) vsource dc=500m type=dc -V0 (vdd 0) vsource dc=1 type=dc -V1 (vn 0) vsource dc=500m type=sine ampl=500m freq=100M - diff --git a/DesignDatabase/Design Examples Library/Analog/A2/Testbench/Performance Specifications/Falling_time.png b/DesignDatabase/Design Examples Library/Analog/A2/Testbench/Performance Specifications/Falling_time.png deleted file mode 100644 index cfa131df3a..0000000000 Binary files a/DesignDatabase/Design Examples Library/Analog/A2/Testbench/Performance Specifications/Falling_time.png and /dev/null differ diff --git a/DesignDatabase/Design Examples Library/Analog/A2/Testbench/Performance Specifications/README.md b/DesignDatabase/Design Examples Library/Analog/A2/Testbench/Performance Specifications/README.md deleted file mode 100644 index 55ed7fe85e..0000000000 --- a/DesignDatabase/Design Examples Library/Analog/A2/Testbench/Performance Specifications/README.md +++ /dev/null @@ -1,12 +0,0 @@ -Comparator performance specifications - -The negative input is kept constant while the positive input is increased and decreased to evaluate the performance. - -1. Rise time - The output rises 2ns after the positive input becomes greater than the negative input. This limits the speed of operation to less than 500 MHz. - -2. Fall time - The output falls 2ns after the positive input becomes less than the negative input. This limits the speed of operation to less than 500 MHz. - -3. Hysteresis - This comparator has no hysteresis. Output switches from high to low and low to high at the same voltage. - -4. Power consumption - Power consumption of this comparator is approximately 23uW. - diff --git a/DesignDatabase/Design Examples Library/Analog/A2/Testbench/Performance Specifications/Rising_time.png b/DesignDatabase/Design Examples Library/Analog/A2/Testbench/Performance Specifications/Rising_time.png deleted file mode 100644 index 1e6ec3f00a..0000000000 Binary files a/DesignDatabase/Design Examples Library/Analog/A2/Testbench/Performance Specifications/Rising_time.png and /dev/null differ diff --git a/DesignDatabase/Design Examples Library/Analog/A3/Layout/A3.PNG b/DesignDatabase/Design Examples Library/Analog/A3/Layout/A3.PNG deleted file mode 100644 index bc4000ca35..0000000000 Binary files a/DesignDatabase/Design Examples Library/Analog/A3/Layout/A3.PNG and /dev/null differ diff --git a/DesignDatabase/Design Examples Library/Analog/A3/Netlist/A3 b/DesignDatabase/Design Examples Library/Analog/A3/Netlist/A3 deleted file mode 100644 index f078ecdd3d..0000000000 --- a/DesignDatabase/Design Examples Library/Analog/A3/Netlist/A3 +++ /dev/null @@ -1,37 +0,0 @@ -// Generated for: spectre -// Generated on: Nov 8 14:55:46 2018 -// Design library name: EnergyHarvesting -// Design cell name: Comp -// Design view name: schematic -simulator lang=spectre -global 0 - -// Library name: DC_converter -// Cell name: NOR -// View name: schematic -subckt NOR GND VDD VIN1 VIN2 VOUT - M0 (VOUT VIN1 GND GND) nch l=60n w=150.0n m=1 nf=1 - M1 (VOUT VIN2 GND GND) nch l=60n w=150.0n m=1 nf=1 - M3 (VOUT VIN1 net14 VDD) pch l=60n w=600n m=1 nf=1 - M2 (net14 VIN2 VDD VDD) pch l=60n w=600n m=1 nf=1 -ends NOR -// End of subcircuit definition. - -// Library name: EnergyHarvesting -// Cell name: Comp -// View name: schematic -M2 (OUT OUTP net021 VDD) pch l=60n w=3u m=1 nf=1 -M4 (OUTP OUT net020 VDD) pch l=60n w=3u m=1 nf=1 -M3 (net023 CLK VDD VDD) pch l=60n w=300n m=1 nf=1 -I1 (GND VDD OUT Q QB) NOR -I0 (GND VDD OUTP QB Q) NOR -M0 (net020 VINP net023 VDD) pch_25 l=20u w=400n m=1 nf=1 -M1 (net021 VINN net023 VDD) pch_25 l=20u w=400n m=1 nf=1 -M12 (net021 CLK GND GND) nch l=60n w=120.0n m=1 nf=1 -M11 (net020 CLK GND GND) nch l=60n w=120.0n m=1 nf=1 -M10 (net020 CLK net021 GND) nch l=60n w=120.0n m=1 nf=1 -M9 (OUT CLK GND GND) nch l=60n w=200n m=1 nf=1 -M6 (OUT OUTP GND GND) nch l=60n w=200n m=1 nf=1 -M7 (OUTP OUT GND GND) nch l=60n w=200n m=1 nf=1 -M8 (OUTP CLK GND GND) nch l=60n w=200n m=1 nf=1 - diff --git a/DesignDatabase/Design Examples Library/Analog/A3/README.md b/DesignDatabase/Design Examples Library/Analog/A3/README.md deleted file mode 100644 index b899f82713..0000000000 --- a/DesignDatabase/Design Examples Library/Analog/A3/README.md +++ /dev/null @@ -1,13 +0,0 @@ -Clocked Comparator - -Files present : - -1. Netlist with sizing - -2. Schematic - -3. Layout - -To be added : - -- Testbench diff --git a/DesignDatabase/Design Examples Library/Analog/A3/Schematic/A3.PNG b/DesignDatabase/Design Examples Library/Analog/A3/Schematic/A3.PNG deleted file mode 100644 index 3e570de7e5..0000000000 Binary files a/DesignDatabase/Design Examples Library/Analog/A3/Schematic/A3.PNG and /dev/null differ diff --git a/DesignDatabase/Design Examples Library/Analog/A4/Layout/A4.PNG b/DesignDatabase/Design Examples Library/Analog/A4/Layout/A4.PNG deleted file mode 100644 index 073ef45ae4..0000000000 Binary files a/DesignDatabase/Design Examples Library/Analog/A4/Layout/A4.PNG and /dev/null differ diff --git a/DesignDatabase/Design Examples Library/Analog/A4/Netlist/A4 b/DesignDatabase/Design Examples Library/Analog/A4/Netlist/A4 deleted file mode 100644 index be679e487e..0000000000 --- a/DesignDatabase/Design Examples Library/Analog/A4/Netlist/A4 +++ /dev/null @@ -1,62 +0,0 @@ -// Generated for: spectre -// Generated on: Nov 8 15:11:28 2018 -// Design library name: EnergyHarvesting -// Design cell name: NON_OVLP3 -// Design view name: schematic -simulator lang=spectre -global 0 - - -// Library name: DC_converter -// Cell name: NOR -// View name: schematic -subckt NOR GND VDD VIN1 VIN2 VOUT - M0 (VOUT VIN1 GND GND) nch l=60n w=150.0n m=1 nf=1 - M1 (VOUT VIN2 GND GND) nch l=60n w=150.0n m=1 nf=1 - M3 (VOUT VIN1 net14 VDD) pch l=60n w=600n m=1 nf=1 - M2 (net14 VIN2 VDD VDD) pch l=60n w=600n m=1 nf=1 -ends NOR -// End of subcircuit definition. - -// Library name: EnergyHarvesting -// Cell name: INV1x -// View name: schematic -subckt INV1x GND VDD VIN VOUT - M0 (VOUT VIN GND GND) nch l=60n w=120.0n m=1 nf=1 - M1 (VOUT VIN VDD VDD) pch l=60n w=240.0n m=1 nf=1 -ends INV1x -// End of subcircuit definition. - -// Library name: DC_converter -// Cell name: INV_L2x -// View name: schematic -subckt INV_L2x GND VDD VIN VOUT - M0 (VOUT VIN GND GND) nch l=120.0n w=120.0n m=1 nf=1 - M1 (VOUT VIN VDD VDD) pch l=120.0n w=240.0n m=1 nf=1 -ends INV_L2x -// End of subcircuit definition. - -// Library name: DC_converter -// Cell name: NAND -// View name: schematic -subckt NAND GND VDD VIN1 VIN2 VOUT - M2 (VOUT VIN1 net16 GND) nch l=60n w=240.0n m=1 nf=1 - M3 (net16 VIN2 GND GND) nch l=60n w=240.0n m=1 nf=1 - M0 (VOUT VIN1 VDD VDD) pch l=60n w=240.0n m=1 nf=1 - M1 (VOUT VIN2 VDD VDD) pch l=60n w=240.0n m=1 nf=1 -ends NAND -// End of subcircuit definition. - -// Library name: EnergyHarvesting -// Cell name: NON_OVLP3 -// View name: schematic -I36 (GND VDD net06 CLK A) NOR -I1 (GND VDD net011 net010 B) NOR -I37 (GND VDD CLK net010) INV1x -I43 (GND VDD net010 net012) INV1x -I39 (GND VDD net09 net011) INV_L2x -I40 (GND VDD B net08) INV_L2x -I41 (GND VDD net08 net06) INV_L2x -I38 (GND VDD A net09) INV_L2x -I44 (GND VDD D net010 C) NAND -I45 (GND VDD C net012 D) NAND diff --git a/DesignDatabase/Design Examples Library/Analog/A4/README.md b/DesignDatabase/Design Examples Library/Analog/A4/README.md deleted file mode 100644 index b9a66878ac..0000000000 --- a/DesignDatabase/Design Examples Library/Analog/A4/README.md +++ /dev/null @@ -1,13 +0,0 @@ -Non-overlapping Clock Generator - -Files present: - -1. Netlist with sizing - -2. Schematic - -3. Layout - -To be added: - -- Testbench diff --git a/DesignDatabase/Design Examples Library/Analog/A4/Schematic/A4.PNG b/DesignDatabase/Design Examples Library/Analog/A4/Schematic/A4.PNG deleted file mode 100644 index b69df3ca74..0000000000 Binary files a/DesignDatabase/Design Examples Library/Analog/A4/Schematic/A4.PNG and /dev/null differ diff --git a/DesignDatabase/Design Examples Library/Analog/A5/Netlist/A5_netlist b/DesignDatabase/Design Examples Library/Analog/A5/Netlist/A5_netlist deleted file mode 100644 index 83226cae5d..0000000000 --- a/DesignDatabase/Design Examples Library/Analog/A5/Netlist/A5_netlist +++ /dev/null @@ -1,40 +0,0 @@ -** Generated for: hspiceD -** Generated on: Nov 19 16:37:16 2018 -** Design library name: DC_converter -** Design cell name: 2018_11_09_ASAP7_SCFilter -** Design view name: schematic -.GLOBAL vdd! - -.AC DEC 100 1.0 1e11 - -.TRAN 1e-9 50e-6 START=1e-9 - -.OP - -.PSS - -.TEMP 25.0 -.OPTION INGOLD=2 ARTIST=2 PSF=2 MEASOUT=1 PARHIER=LOCAL PROBE=0 MARCH=2 ACCURACY=1 POST - -** Library name: DC_converter -** Cell name: 2018_11_09_ASAP7_current_mirror_ota -** View name: schematic -.subckt DC_converter_2018_11_09_ASAP7_telescopic_ota_schematic vbiasnd vinn vinp voutn voutp D1 - -m9 voutn vbiasn net8 0 nmos_rvt w=270e-9 l=20e-9 nfin=25 -m8 voutp vbiasn net014 0 nmos_rvt w=270e-9 l=20e-9 nfin=25 -m5 D1 D1 0 0 nmos_rvt w=270e-9 l=20e-9 nfin=10 -m4 net10 vbiasnd 0 0 nmos_rvt w=270e-9 l=20e-9 nfin=50 -m3 net014 vinn net10 0 nmos_rvt w=270e-9 l=20e-9 nfin=70 -m0 net8 vinp net10 0 nmos_rvt w=270e-9 l=20e-9 nfin=70 -m7 voutp vbiasp net012 net012 pmos_rvt w=270e-9 l=20e-9 nfin=15 -m6 voutn vbiasp net06 net06 pmos_rvt w=270e-9 l=20e-9 nfin=15 -m2 net012 vbiasp1 vdd! vdd! pmos_rvt w=270e-9 l=20e-9 nfin=10 -m1 net06 vbiasp1 vdd! vdd! pmos_rvt w=270e-9 l=20e-9 nfin=10 -c2 voutp 0 60e-15 -c3 voutn 0 60e-15 -.ends DC_converter_2018_11_09_ASAP7_telescopic_ota_schematic -** End of subcircuit definition. - -.END - diff --git a/DesignDatabase/Design Examples Library/Analog/A5/README.md b/DesignDatabase/Design Examples Library/Analog/A5/README.md deleted file mode 100644 index 06b8b91c42..0000000000 --- a/DesignDatabase/Design Examples Library/Analog/A5/README.md +++ /dev/null @@ -1,14 +0,0 @@ -Fully differential telescopic OTA - -Files present: - -1. Netlist with sizing - -2. Schematic - -3. Testbench - - -To be added: - -- Layout \ No newline at end of file diff --git a/DesignDatabase/Design Examples Library/Analog/A5/Schematic/A5_image.PNG b/DesignDatabase/Design Examples Library/Analog/A5/Schematic/A5_image.PNG deleted file mode 100644 index 3e90342db3..0000000000 Binary files a/DesignDatabase/Design Examples Library/Analog/A5/Schematic/A5_image.PNG and /dev/null differ diff --git a/DesignDatabase/Design Examples Library/Analog/A5/Testbench/Constraints/A5_constraints b/DesignDatabase/Design Examples Library/Analog/A5/Testbench/Constraints/A5_constraints deleted file mode 100644 index 165766454c..0000000000 --- a/DesignDatabase/Design Examples Library/Analog/A5/Testbench/Constraints/A5_constraints +++ /dev/null @@ -1,2 +0,0 @@ -Symmetry in the differential pair and the cascode load blocks -Matching between transistors in the current mirror diff --git a/DesignDatabase/Design Examples Library/Analog/A5/Testbench/Netlist/A5_testbench b/DesignDatabase/Design Examples Library/Analog/A5/Testbench/Netlist/A5_testbench deleted file mode 100644 index 124aea52ba..0000000000 --- a/DesignDatabase/Design Examples Library/Analog/A5/Testbench/Netlist/A5_testbench +++ /dev/null @@ -1,106 +0,0 @@ -** Generated for: hspiceD -** Generated on: Nov 19 16:37:16 2018 -** Design library name: DC_converter -** Design cell name: 2018_11_09_ASAP7_SCFilter -** Design view name: schematic -.GLOBAL vdd! - -.TRAN 1e-9 50e-6 START=1e-9 - -.OP - -.TEMP 25.0 -.OPTION INGOLD=2 ARTIST=2 PSF=2 MEASOUT=1 PARHIER=LOCAL PROBE=0 MARCH=2 ACCURACY=1 POST - -** Library name: asap7ssc7p5t -** Cell name: INVx1_ASAP7_75t_R -** View name: schematic -.subckt INVx1_ASAP7_75t_R a y vdd vss -m0 y a vss vss nmos_rvt w=81e-9 l=20e-9 nfin=3 -m1 y a vdd vdd pmos_rvt w=81e-9 l=20e-9 nfin=3 -.ends INVx1_ASAP7_75t_R -** End of subcircuit definition. - -** Library name: asap7ssc7p5t -** Cell name: INVx1_ASAP7_75t_R_21 -** View name: schematic -.subckt INVx1_ASAP7_75t_R_21 a y vdd vss -m0 y a vss vss nmos_rvt w=81e-9 l=20e-9 nfin=21 -m1 y a vdd vdd pmos_rvt w=81e-9 l=20e-9 nfin=21 -.ends INVx1_ASAP7_75t_R_21 -** End of subcircuit definition. - -** Library name: DC_converter -** Cell name: 2018_12_03_ASAP7_transmission_gate -** View name: schematic -.subckt DC_converter_2018_12_03_ASAP7_transmission_gate a y vdd vss -m0 y vdd a 0 nmos_rvt w=81e-9 l=20e-9 nfin=3 -m1 y vss a a pmos_rvt w=81e-9 l=20e-9 nfin=3 -.ends DC_converter_2018_12_03_ASAP7_transmission_gate -** End of subcircuit definition. - -** Library name: DC_converter -** Cell name: 2018_11_09_ASAP7_NAND_gate -** View name: schematic -.subckt DC_converter_2018_11_09_ASAP7_NAND_gate_schematic a b out vdd vss -m2 out a net22 vss nmos_rvt w=54e-9 l=20e-9 nfin=2 -m3 net22 b vss vss nmos_rvt w=54e-9 l=20e-9 nfin=2 -m0 out a vdd vdd pmos_rvt w=27e-9 l=20e-9 nfin=1 -m1 out b vdd vdd pmos_rvt w=27e-9 l=20e-9 nfin=1 -.ends DC_converter_2018_11_09_ASAP7_NAND_gate_schematic -** End of subcircuit definition. - -** Library name: DC_converter -** Cell name: 2018_11_09_ASAP7_non_overlapping_clock_generator -** View name: schematic -.subckt DC_converter_2018_11_09_ASAP7_non_overlapping_clock_generator_schematic clk d_vdd d_gnd phi1 phi2 -xi6 clk net9 d_vdd d_gnd INVx1_ASAP7_75t_R -xi6_tg clk net9_tg d_dd d_gnd DC_converter_2018_12_03_ASAP7_transmission_gate -xi5 net12 phi2 d_vdd d_gnd INVx1_ASAP7_75t_R_21 -xi4 net17 net12 d_vdd d_gnd INVx1_ASAP7_75t_R -xi3 net8 phi1 d_vdd d_gnd INVx1_ASAP7_75t_R_21 -xi2 net15 net8 d_vdd d_gnd INVx1_ASAP7_75t_R -xi1 net16 net15 d_vdd d_gnd INVx1_ASAP7_75t_R -xi0 net18 net17 d_vdd d_gnd INVx1_ASAP7_75t_R -xi8 net9 net8 net18 d_vdd d_gnd DC_converter_2018_11_09_ASAP7_NAND_gate_schematic -xi7 net12 net9_tg net16 d_vdd d_gnd DC_converter_2018_11_09_ASAP7_NAND_gate_schematic -.ends DC_converter_2018_11_09_ASAP7_non_overlapping_clock_generator_schematic -** End of subcircuit definition. - - -** Library name: DC_converter -** Cell name: 2018_11_09_ASAP7_cmfb -** View name: schematic -.subckt DC_converter_2018_11_09_ASAP7_cmfb_schematic va vb vbias vcm vg phi1 phi2 -c3 net10 vg 20e-15 -c2 vg net8 20e-15 -m4 vbias phi2 vg 0 nmos_rvt w=27e-9 l=20e-9 nfin=50 -m3 vcm phi2 net10 0 nmos_rvt w=27e-9 l=20e-9 nfin=50 -m2 vb phi1 net10 0 nmos_rvt w=27e-9 l=20e-9 nfin=50 -m1 net8 phi2 vcm 0 nmos_rvt w=27e-9 l=20e-9 nfin=50 -m0 net8 phi1 va 0 nmos_rvt w=27e-9 l=20e-9 nfin=50 -.ends DC_converter_2018_11_09_ASAP7_cmfb_schematic -** End of subcircuit definition. - - -** Library name: DC_converter -** Cell name: 2018_11_09_ASAP7_Testbench -** View name: schematic -i5 vdd! id DC=40e-6 -//xi0 vg vbiasn vbiasp1 vbiasp2 net08 net09 voutn voutp id vdd vss DC_converter_2018_11_09_ASAP7_telescopic_ota_schematic -xi3 clk vdd! 0 phi1 phi2 DC_converter_2018_11_09_ASAP7_non_overlapping_clock_generator_schematic -v0 clk 0 PULSE 0 1 0 0 0 115e-9 250e-9 -v11 vdd! 0 DC=1 -v6 vcm 0 DC=550e-3 -v5 vbias_cm 0 DC=375e-3 -v2 net09 0 SIN 550e-3 1e-4 50e+3 0 0 0 -v1 net08 0 SIN 550e-3 1e-4 50e+3 0 0 180 -v3 vbiasn 0 DC=700e-3 -v4 vbiasp1 0 DC=300e-3 -v7 vbiasp2 0 DC=575e-3 -v8 vss 0 DC=0 -v9 vdd 0 DC=1 -xi13 voutn voutp id vcm vg phi1 phi2 DC_converter_2018_11_09_ASAP7_cmfb_schematic -.probe vdiff1=par('v(voutn)-v(voutp)') -.probe vdiff=par('v(net09)-v(net08)') -.END diff --git a/DesignDatabase/Design Examples Library/Analog/A5/Testbench/Performance Specifications/A5_performance_specification b/DesignDatabase/Design Examples Library/Analog/A5/Testbench/Performance Specifications/A5_performance_specification deleted file mode 100644 index a92b77c38d..0000000000 --- a/DesignDatabase/Design Examples Library/Analog/A5/Testbench/Performance Specifications/A5_performance_specification +++ /dev/null @@ -1,7 +0,0 @@ -The fully differential telescopic OTA can be evaluated using the following performance metrics. - -1. Gain - This amplifier has a gain of around 50 dB - -2. Unity gain frequency - It has a unity gain frequency of around 800 MHz - -3. Phase Margin diff --git a/DesignDatabase/Design Examples Library/Analog/README.md b/DesignDatabase/Design Examples Library/Analog/README.md deleted file mode 100644 index 437ad0a708..0000000000 --- a/DesignDatabase/Design Examples Library/Analog/README.md +++ /dev/null @@ -1,11 +0,0 @@ -This folder contains example ANALOG circuits (some of which have been taped out) that can be used as benchmarks. - -A1 : Fully differential current mirror OTA - -A2 : Comparator (not clocked) - -A3 : Comparator (clocked) - -A4 : Non-overlapping clock generator - -A5 : Fully differential telescopic OTA diff --git a/DesignDatabase/Design Examples Library/Power Management/PM1/Layout/DC1.PNG b/DesignDatabase/Design Examples Library/Power Management/PM1/Layout/DC1.PNG deleted file mode 100644 index 2359801014..0000000000 Binary files a/DesignDatabase/Design Examples Library/Power Management/PM1/Layout/DC1.PNG and /dev/null differ diff --git a/DesignDatabase/Design Examples Library/Power Management/PM1/Netlist/PM1 b/DesignDatabase/Design Examples Library/Power Management/PM1/Netlist/PM1 deleted file mode 100644 index 7d4ebf184c..0000000000 --- a/DesignDatabase/Design Examples Library/Power Management/PM1/Netlist/PM1 +++ /dev/null @@ -1,71 +0,0 @@ -// Generated for: spectre -// Generated on: Nov 8 14:28:22 2018 -// Design library name: EnergyHarvesting -// Design cell name: ChargePump -// Design view name: schematic -simulator lang=spectre -global 0 - -// Library name: DC_converter -// Cell name: NAND -// View name: schematic -subckt NAND GND VDD VIN1 VIN2 VOUT - M2 (VOUT VIN1 net16 GND) nch l=60n w=240.0n m=1 nf=1 - M3 (net16 VIN2 GND GND) nch l=60n w=240.0n m=1 nf=1 - M0 (VOUT VIN1 VDD VDD) pch l=60n w=240.0n m=1 nf=1 - M1 (VOUT VIN2 VDD VDD) pch l=60n w=240.0n m=1 nf=1 -ends NAND -// End of subcircuit definition. - -// Library name: EnergyHarvesting -// Cell name: INV1x -// View name: schematic -subckt INV1x GND VDD VIN VOUT - M0 (VOUT VIN GND GND) nch l=60n w=120.0n m=1 nf=1 - M1 (VOUT VIN VDD VDD) pch l=60n w=240.0n m=1 nf=1 -ends INV1x -// End of subcircuit definition. - -// Library name: DC_converter -// Cell name: NOR -// View name: schematic -subckt NOR GND VDD VIN1 VIN2 VOUT - M0 (VOUT VIN1 GND GND) nch l=60n w=150.0n m=1 nf=1 - M1 (VOUT VIN2 GND GND) nch l=60n w=150.0n m=1 nf=1 - M3 (VOUT VIN1 net14 VDD) pch l=60n w=600n m=1 nf=1 - M2 (net14 VIN2 VDD VDD) pch l=60n w=600n m=1 nf=1 -ends NOR -// End of subcircuit definition. - -// Library name: EnergyHarvesting -// Cell name: ChargePump -// View name: schematic -M17 (net027 VSTEPD net044 GND) nch l=60n w=120.0n m=1 nf=1 -M16 (net044 PDB GND GND) nch l=60n w=120.0n m=1 nf=1 -M13 (net036 net036 GND GND) nch l=200n w=200n m=1 nf=1 -M14 (VSTEPD PD net036 GND) nch l=60n w=200n m=1 nf=1 -M12 (net026 net036 GND GND) nch l=200n w=200n m=1 nf=1 -M8 (net22 PU GND GND) nch l=60n w=120.0n m=1 nf=1 -M7 (net058 VSTEPU net22 GND) nch l=60n w=120.0n m=1 nf=1 -M0 (VSTEPU PUB GND GND) nch l=60n w=200n m=1 nf=1 -M19 (net043 PDB VDD VDD) pch l=60n w=200n m=1 nf=1 -M18 (net027 VSTEPD net043 VDD) pch l=60n w=200n m=1 nf=1 -M15 (VSTEPD PD VDD VDD) pch l=60n w=200n m=1 nf=1 -M6 (net058 VSTEPU net21 VDD) pch l=60n w=200n m=1 -M5 (net21 PU VDD VDD) pch l=60n w=200n m=1 nf=1 -M3 (net27 net8 VDD VDD) pch l=200n w=400n m=1 nf=1 -M2 (net8 net8 VDD VDD) pch l=200n w=400n m=1 nf=1 -M1 (VSTEPU PUB net8 VDD) pch l=60n w=200n m=1 nf=1 -C3 (VDD VSTEPD) mimcap_sin lt=5u wt=5u mimflag=3 mf=1 mismatchflag=0 -C1 (GND VSTEPU) mimcap_sin lt=5u wt=5u mimflag=3 mf=1 mismatchflag=0 -C4 (GND net058) mimcap_sin lt=5u wt=5u mimflag=3 mf=1 mismatchflag=0 -C5 (VDD net027) mimcap_sin lt=5u wt=5u mimflag=3 mf=1 mismatchflag=0 -C0 (GND VCTL) mimcap_sin lt=40u wt=40u mimflag=3 mf=1 mismatchflag=0 -I0 (GND VDD net058 PU VPULSEU) NAND -I11 (GND VDD PD PDB) INV1x -I1 (GND VDD PU PUB) INV1x -M4 (VCTL VPULSEU net27 VDD) pch_hvt l=60n w=400n m=1 nf=1 -M9 (VCTL VPULSED net026 GND) nch_hvt l=60n w=200n m=1 nf=1 -I10 (GND VDD net027 PDB VPULSED) NOR - - diff --git a/DesignDatabase/Design Examples Library/Power Management/PM1/README.md b/DesignDatabase/Design Examples Library/Power Management/PM1/README.md deleted file mode 100644 index 1c1bdfd762..0000000000 --- a/DesignDatabase/Design Examples Library/Power Management/PM1/README.md +++ /dev/null @@ -1,13 +0,0 @@ -Charge pump circuit used in a LDO - -Files present: - -1. Netlist with sizing - -2. Schematic - -3. Layout - -To be added: - -- Testbench diff --git a/DesignDatabase/Design Examples Library/Power Management/PM1/Schematic/DC1.PNG b/DesignDatabase/Design Examples Library/Power Management/PM1/Schematic/DC1.PNG deleted file mode 100644 index aff9c6574f..0000000000 Binary files a/DesignDatabase/Design Examples Library/Power Management/PM1/Schematic/DC1.PNG and /dev/null differ diff --git a/DesignDatabase/Design Examples Library/Power Management/PM2/Layout/PM2_layout.PNG b/DesignDatabase/Design Examples Library/Power Management/PM2/Layout/PM2_layout.PNG deleted file mode 100644 index a40c1331d9..0000000000 Binary files a/DesignDatabase/Design Examples Library/Power Management/PM2/Layout/PM2_layout.PNG and /dev/null differ diff --git a/DesignDatabase/Design Examples Library/Power Management/PM2/Netlist/PM2_netlist.txt b/DesignDatabase/Design Examples Library/Power Management/PM2/Netlist/PM2_netlist.txt deleted file mode 100644 index 50682e6103..0000000000 --- a/DesignDatabase/Design Examples Library/Power Management/PM2/Netlist/PM2_netlist.txt +++ /dev/null @@ -1,21 +0,0 @@ -// Generated for: spectre -// Generated on: Nov 2 10:25:43 2018 -// Design library name: DC_converter -// Design cell name: 31Dec_2017_Driver_cap -// Design view name: schematic -simulator lang=spectre -global 0 - -// Library name: DC_converter -// Cell name: 31Dec_2017_Driver_cap -// View name: schematic -M13 (net32 lres_nmos gnd gnd) nch l=4.8u w=120.0n m=1 nf=1 -M12 (net017 sres_nmos gnd gnd) nch l=60n w=240.0n m=1 nf=1 -M11 (net32 sw net33 gnd) nch l=60n w=120.0n m=2 nf=1 -M9 (net33 ctrl gnd gnd) nch l=60n w=120.0n m=2 nf=1 -M14 (Vout tin net32 gnd) nch l=60n w=120.0n m=1 nf=1 -M17 (Vout lres_pmos Vdd Vdd) pch l=4.8u w=120.0n m=1 nf=1 -M15 (net31 sres_pmos Vdd Vdd) pch l=120.0n w=120.0n m=1 nf=1 -M4 (net32 sw_sres_nmos net017 gnd) nmos_rf lr=60n wr=600n nr=1 -M6 (Vout sw_sres_pmos net31 Vdd) pmos_rf lr=60n wr=600n nr=1 -M5 (Vout tin Vdd Vdd) pch_hvt l=60n w=120.0n m=5 nf=1 diff --git a/DesignDatabase/Design Examples Library/Power Management/PM2/README.md b/DesignDatabase/Design Examples Library/Power Management/PM2/README.md deleted file mode 100644 index 1c1bdfd762..0000000000 --- a/DesignDatabase/Design Examples Library/Power Management/PM2/README.md +++ /dev/null @@ -1,13 +0,0 @@ -Charge pump circuit used in a LDO - -Files present: - -1. Netlist with sizing - -2. Schematic - -3. Layout - -To be added: - -- Testbench diff --git a/DesignDatabase/Design Examples Library/Power Management/PM2/Schematic/PM2_image.PNG b/DesignDatabase/Design Examples Library/Power Management/PM2/Schematic/PM2_image.PNG deleted file mode 100644 index df5729c154..0000000000 Binary files a/DesignDatabase/Design Examples Library/Power Management/PM2/Schematic/PM2_image.PNG and /dev/null differ diff --git a/DesignDatabase/Design Examples Library/Power Management/README.md b/DesignDatabase/Design Examples Library/Power Management/README.md deleted file mode 100644 index 2bf5243084..0000000000 --- a/DesignDatabase/Design Examples Library/Power Management/README.md +++ /dev/null @@ -1,5 +0,0 @@ -This folder contains example Power Management circuits (some of which have been taped out) that can be used as benchmarks. - -PM1: Charge pump circuit - -PM2: Low voltage dropout regulator gate driver circuit \ No newline at end of file diff --git a/DesignDatabase/Design Examples Library/README.md b/DesignDatabase/Design Examples Library/README.md deleted file mode 100644 index baa9c01672..0000000000 --- a/DesignDatabase/Design Examples Library/README.md +++ /dev/null @@ -1,13 +0,0 @@ -This folder contains example circuits (some of which have been taped out) that can be used as benchmarks. - -The circuits are mainly classified into 4 catergories: - -1. Analog : For eg. amplifiers, comparators etc. - -2. Power Delivery : For eg. buck converter, LDO, power management and related circuits. - -3. Wireline : For eg. equalizers, etc. - -4. Wireless : For eg. Low noise amplifiers, mixers, etc. - - diff --git a/DesignDatabase/Design Examples Library/Wireless/README.md b/DesignDatabase/Design Examples Library/Wireless/README.md deleted file mode 100644 index c6bef02650..0000000000 --- a/DesignDatabase/Design Examples Library/Wireless/README.md +++ /dev/null @@ -1,9 +0,0 @@ -This folder contains example Power Management circuits (some of which have been taped out) that can be used as benchmarks. - -WLESS1: Low Noise Amplifier used in a RF Transceiver - -WLESS2: Mixer - -WLESS3: Bandpass Filter - -WLESS4: Oscillator diff --git a/DesignDatabase/Design Examples Library/Wireless/WLESS1/Layout/WLESS1_image.png b/DesignDatabase/Design Examples Library/Wireless/WLESS1/Layout/WLESS1_image.png deleted file mode 100644 index 745e353273..0000000000 Binary files a/DesignDatabase/Design Examples Library/Wireless/WLESS1/Layout/WLESS1_image.png and /dev/null differ diff --git a/DesignDatabase/Design Examples Library/Wireless/WLESS1/Netlist/WLESS1_netlist.txt b/DesignDatabase/Design Examples Library/Wireless/WLESS1/Netlist/WLESS1_netlist.txt deleted file mode 100644 index 0c3dcb6779..0000000000 --- a/DesignDatabase/Design Examples Library/Wireless/WLESS1/Netlist/WLESS1_netlist.txt +++ /dev/null @@ -1,33 +0,0 @@ - -// Library name: LNA_qmeng -// Cell name: LNA_QM_CORE -// View name: schematic -R5 (net011 VAUX VDD) rppolywo_rf l=6u w=500n m=1 -R4 (net063 SF_BIAS VDD) rppolywo_rf l=6u w=500n m=1 -R10 (net0252 VMAIN VDD) rppolywo_rf l=6u w=500n m=1 -R3 (net033 SF_BIAS VDD) rppolywo_rf l=6u w=500n m=1 -C12 (net0252 VSS VSS) mimcap_um_sin_rf lt=16.0u wt=16.0u m=1 -C9 (net0252 VSS VSS) mimcap_um_sin_rf lt=16.0u wt=16.0u m=1 -C6 (OUTN net063 VDD) mimcap_um_sin_rf lt=20u wt=20u m=1 -C43 (IN_INT net011 VDD) mimcap_um_sin_rf lt=16.0u wt=16.0u m=1 -C5 (OUTP net033 VDD) mimcap_um_sin_rf lt=20u wt=20u m=1 -C11 (net059 VDD VDD) mimcap_um_sin_rf lt=100.0000u wt=50u m=1 -C8 (net047 VDD VDD) mimcap_um_sin_rf lt=100.0000u wt=50u m=1 -M10 (VDD net033 VOUTP VOUTP) nmos_rf lr=120.0n wr=2u nr=32 -M12 (VDD net063 VOUTN VOUTN) nmos_rf lr=120.0n wr=2u nr=32 -M4 (OUTN net011 VSS VSS) nmos_rf lr=60n wr=1u nr=10 -M13 (OUTP net0252 IN_INT IN_INT) nmos_rf lr=60n wr=1u nr=10 -R38 (net058 net057 VDD) rppolyl_rf l=24.0u w=3u m=1 -R0 (VOUTP VSS VDD) rppolys_rf l=20u w=1u m=1 -R36 (net042 net056 VDD) rppolyl_rf l=24.0u w=3u m=1 -R35 (net056 net055 VDD) rppolyl_rf l=24.0u w=3u m=1 -R34 (net055 net054 VDD) rppolyl_rf l=24.0u w=3u m=1 -R33 (net054 net060 VDD) rppolyl_rf l=24.0u w=3u m=1 -R41 (OUTN net032 VDD) rppolyl_rf l=24.0u w=3u m=1 -R32 (net060 OUTP VDD) rppolyl_rf l=24.0u w=3u m=1 -R1 (VOUTN VSS VDD) rppolys_rf l=20u w=1u m=1 -R40 (net032 VDD VDD) rppolyl_rf l=24.0u w=3u m=1 -R37 (net057 net042 VDD) rppolyl_rf l=24.0u w=3u m=1 -R39 (VDD net058 VDD) rppolyl_rf l=24.0u w=3u m=1 -L8 (net047 OUTP VSS) spiral_std_mu_z w=3u rad=41.0u nr=3.75 -L9 (net059 OUTN VSS) spiral_std_mu_z w=3u rad=39.0u nr=3.75 diff --git a/DesignDatabase/Design Examples Library/Wireless/WLESS1/README.md b/DesignDatabase/Design Examples Library/Wireless/WLESS1/README.md deleted file mode 100644 index 2d9e0463b1..0000000000 --- a/DesignDatabase/Design Examples Library/Wireless/WLESS1/README.md +++ /dev/null @@ -1,13 +0,0 @@ -Low noise amplifier used in an RF Transceiver - -Files present: - -1. Netlist with sizing - -2. Schematic - -3. Layout - -To be added: - -- Testbench diff --git a/DesignDatabase/Design Examples Library/Wireless/WLESS1/Schematic/WLESS1_image.jpg b/DesignDatabase/Design Examples Library/Wireless/WLESS1/Schematic/WLESS1_image.jpg deleted file mode 100644 index 886187e411..0000000000 Binary files a/DesignDatabase/Design Examples Library/Wireless/WLESS1/Schematic/WLESS1_image.jpg and /dev/null differ diff --git a/DesignDatabase/Design Examples Library/Wireless/WLESS2/Layout/WLESS2_image.png b/DesignDatabase/Design Examples Library/Wireless/WLESS2/Layout/WLESS2_image.png deleted file mode 100644 index 39bd42bcd4..0000000000 Binary files a/DesignDatabase/Design Examples Library/Wireless/WLESS2/Layout/WLESS2_image.png and /dev/null differ diff --git a/DesignDatabase/Design Examples Library/Wireless/WLESS2/Netlist/WLESS2_netlist.txt b/DesignDatabase/Design Examples Library/Wireless/WLESS2/Netlist/WLESS2_netlist.txt deleted file mode 100644 index b78f6d5fd5..0000000000 --- a/DesignDatabase/Design Examples Library/Wireless/WLESS2/Netlist/WLESS2_netlist.txt +++ /dev/null @@ -1,111 +0,0 @@ - -// Library name: test_qmeng -// Cell name: MIXER_RFBIAS_RES -// View name: schematic -subckt MIXER_RFBIAS_RES M P tail_bias -R3 (P net9 ) rppolywo l=6u w=1u m=1 mf=(1) - -R0 (net9 tail_bias ) rppolywo l=6u w=1u m=1 mf=(1) - -R1 (tail_bias net05 ) rppolywo l=6u w=1u m=1 mf=(1) - -R2 (net05 M ) rppolywo l=6u w=1u m=1 mf=(1) - -ends MIXER_RFBIAS_RES -// End of subcircuit definition. - -// Library name: test_qmeng -// Cell name: MIXER_LOSWBIAS_RES -// View name: schematic -subckt MIXER_LOSWBIAS_RES MIXER_LOBIAS VDD VSS -R5 (VDD net050 ) rppolywo l=4u w=1u m=1 mf=(1) - -R4 (net031 net034 ) rppolywo l=4u w=1u m=1 mf=(1) - -R9 (net049 net031 ) rppolywo l=4u w=1u m=1 mf=(1) - -R6 (net050 net051 ) rppolywo l=4u w=1u m=1 mf=(1) - -R7 (net051 MIXER_LOBIAS ) rppolywo l=4u w=1u m=1 mf=(1) - -R8 (MIXER_LOBIAS net049 ) rppolywo l=4u w=1u m=1 mf=(1) - -R0 (net039 VSS ) rppolywo l=4u w=1u m=1 mf=(1) - -R1 (net033 net039 ) rppolywo l=4u w=1u m=1 mf=(1) - -R3 (net034 net036 ) rppolywo l=4u w=1u m=1 mf=(1) - -R2 (net036 net033 ) rppolywo l=4u w=1u m=1 mf=(1) - -ends MIXER_LOSWBIAS_RES -// End of subcircuit definition. - -// Library name: test_qmeng -// Cell name: MIXER_LOAD_RES -// View name: schematic -subckt MIXER_LOAD_RES A B -R4 (net03 B ) rppolys l=13.0u w=1u m=1 mf=(1) - -R0 (A net06 ) rppolys l=13.0u w=1u m=1 mf=(1) - -R1 (net06 net05 ) rppolys l=13.0u w=1u m=1 mf=(1) - -R3 (net05 net03 ) rppolys l=13.0u w=1u m=1 mf=(1) - -ends MIXER_LOAD_RES -// End of subcircuit definition. - -// Library name: PhasedArray_WB_V2 -// Cell name: Mixer -// View name: schematic -M35 (net051 tailm VSS VSS) nmos_rf lr=240.0n wr=3.6u nr=12 -M34 (net039 tailp VSS VSS) nmos_rf lr=240.0n wr=3.6u nr=12 -M44\<1\> (VSS MIXER_TAIL_IIN VSS VSS) nmos_rf lr=240.0n wr=3.6u nr=2 -M44\<2\> (VSS MIXER_TAIL_IIN VSS VSS) nmos_rf lr=240.0n wr=3.6u nr=2 -M44\<3\> (VSS MIXER_TAIL_IIN VSS VSS) nmos_rf lr=240.0n wr=3.6u nr=2 -M44\<4\> (VSS MIXER_TAIL_IIN VSS VSS) nmos_rf lr=240.0n wr=3.6u nr=2 -M44\<5\> (VSS MIXER_TAIL_IIN VSS VSS) nmos_rf lr=240.0n wr=3.6u nr=2 -M44\<6\> (VSS MIXER_TAIL_IIN VSS VSS) nmos_rf lr=240.0n wr=3.6u nr=2 -M44\<7\> (VSS MIXER_TAIL_IIN VSS VSS) nmos_rf lr=240.0n wr=3.6u nr=2 -M44\<8\> (VSS MIXER_TAIL_IIN VSS VSS) nmos_rf lr=240.0n wr=3.6u nr=2 -M43 (VSS VSS VSS VSS) nmos_rf lr=60n wr=2u nr=4 -M38 (MIXER_TAIL_IIN MIXER_TAIL_IIN VSS VSS) nmos_rf lr=240.0n wr=3.6u nr=2 -M39 (pbias MIXER_TAIL_IIN VSS VSS) nmos_rf lr=240.0n wr=3.6u nr=2 -M7 (IFM Oscp net039 net039) nmos_rf lr=60n wr=2u nr=4 -M13 (IFP Oscp net051 net051) nmos_rf lr=60n wr=2u nr=4 -M12 (IFM Oscm net051 net051) nmos_rf lr=60n wr=2u nr=4 -M11 (IFP Oscm net039 net039) nmos_rf lr=60n wr=2u nr=4 -M29 (VDD VDD VDD VDD) pmos_rf lr=240.0n wr=2.05u nr=8 -M16 (pbias pbias VDD VDD) pmos_rf lr=240.0n wr=2.05u nr=8 -M24 (IFP pbias VDD VDD) pmos_rf lr=240.0n wr=2.05u nr=32 -M23 (IFM pbias VDD VDD) pmos_rf lr=240.0n wr=2.05u nr=32 -I29 (tailm tailp MIXER_TAIL_IIN) MIXER_RFBIAS_RES -I12 (Oscp VDD VSS) MIXER_LOSWBIAS_RES -I21 (Oscm VDD VSS) MIXER_LOSWBIAS_RES -I18 (IFP VDD) MIXER_LOAD_RES -I17 (IFM VDD) MIXER_LOAD_RES -R1\<1\> (VSS net040\<0\> ) rppolys l=13.0u w=1u m=1 mf=(1) - -R1\<2\> (VSS net040\<1\> ) rppolys l=13.0u w=1u m=1 mf=(1) - -R1\<3\> (VSS net040\<2\> ) rppolys l=13.0u w=1u m=1 mf=(1) - -R1\<4\> (VSS net040\<3\> ) rppolys l=13.0u w=1u m=1 mf=(1) - -C15 (LOP Oscp VSS) mimcap_woum_sin_rf lt=32.0u wt=16.0u lay=7 m=1 -C6 (RFM tailm VSS) mimcap_woum_sin_rf lt=22.0u wt=22.0u lay=7 m=1 -C7 (RFP tailp VSS) mimcap_woum_sin_rf lt=22.0u wt=22.0u lay=7 m=1 -C14 (LOM Oscm VSS) mimcap_woum_sin_rf lt=32.0u wt=16.0u lay=7 m=1 -R2 (IFP OUTP ) rppolywo l=6u w=1u m=1 mf=(1) - -R5\<1\> (VSS net043\<0\> ) rppolywo l=6u w=1u m=1 mf=(1) - -R5\<2\> (VSS net043\<1\> ) rppolywo l=6u w=1u m=1 mf=(1) - -R5\<3\> (VSS net043\<2\> ) rppolywo l=6u w=1u m=1 mf=(1) - -R5\<4\> (VSS net043\<3\> ) rppolywo l=6u w=1u m=1 mf=(1) - -R0 (OUTM IFM ) rppolywo l=6u w=1u m=1 mf=(1) - diff --git a/DesignDatabase/Design Examples Library/Wireless/WLESS2/README.md b/DesignDatabase/Design Examples Library/Wireless/WLESS2/README.md deleted file mode 100644 index 6056c58dd8..0000000000 --- a/DesignDatabase/Design Examples Library/Wireless/WLESS2/README.md +++ /dev/null @@ -1,13 +0,0 @@ -Mixer ciruit - -Files present: - -1. Netlist with sizing - -2. Schematic - -3. Layout - -To be added: - -- Testbench diff --git a/DesignDatabase/Design Examples Library/Wireless/WLESS2/Schematic/WLESS2_image.jpg b/DesignDatabase/Design Examples Library/Wireless/WLESS2/Schematic/WLESS2_image.jpg deleted file mode 100644 index f3778ee240..0000000000 Binary files a/DesignDatabase/Design Examples Library/Wireless/WLESS2/Schematic/WLESS2_image.jpg and /dev/null differ diff --git a/DesignDatabase/Design Examples Library/Wireless/WLESS3/Layout/WLESS3_image.png b/DesignDatabase/Design Examples Library/Wireless/WLESS3/Layout/WLESS3_image.png deleted file mode 100644 index 0933cd6616..0000000000 Binary files a/DesignDatabase/Design Examples Library/Wireless/WLESS3/Layout/WLESS3_image.png and /dev/null differ diff --git a/DesignDatabase/Design Examples Library/Wireless/WLESS3/Netlist/WLESS3_netlist.txt b/DesignDatabase/Design Examples Library/Wireless/WLESS3/Netlist/WLESS3_netlist.txt deleted file mode 100644 index cb1b8e3b5b..0000000000 --- a/DesignDatabase/Design Examples Library/Wireless/WLESS3/Netlist/WLESS3_netlist.txt +++ /dev/null @@ -1,151 +0,0 @@ - -// Library name: PhasedArray_WB_V2 -// Cell name: res_24K -// View name: schematic -subckt res_24K t1 t2 vss - R4 (t2 net05 vss) rppolywo_rf l=8u w=500n m=1 - R2 (net06 net05 vss) rppolywo_rf l=8u w=500n m=1 - R1 (net06 net6 vss) rppolywo_rf l=8u w=500n m=1 - R0 (t1 net6 vss) rppolywo_rf l=8u w=500n m=1 -ends res_24K -// End of subcircuit definition. - -// Library name: PhasedArray_WB_V2 -// Cell name: capbank_gp_lowC_noLSB_BPF -// View name: schematic -subckt capbank_gp_lowC_noLSB_BPF B\<3\> B\<2\> B\<1\> B\<0\> LEFT RIGHT - VDD VSS - C5 (RIGHT net07 VSS) mimcap_woum_sin_rf lt=10u wt=10u lay=7 m=1 - - C4 (LEFT net010 VSS) mimcap_woum_sin_rf lt=10u wt=10u lay=7 m=1 - - C3 (RIGHT net3 VSS) mimcap_woum_sin_rf lt=5u wt=5u lay=7 m=2 - - C2 (LEFT net1 VSS) mimcap_woum_sin_rf lt=5u wt=5u lay=7 m=2 - - C1 (RIGHT net4 VSS) mimcap_woum_sin_rf lt=5u wt=5u lay=7 m=1 - - C0 (LEFT net2 VSS) mimcap_woum_sin_rf lt=5u wt=5u lay=7 m=1 - - M2 (net010 b2_buf net07 VSS) nmos_rf lr=60n wr=2u nr=20 - - M1 (net1 b1_buf net3 VSS) nmos_rf lr=60n wr=2u nr=20 - - M0 (net2 b0_buf net4 VSS) nmos_rf lr=60n wr=2u nr=20 - - M44 (net0155 net0120 VSS VSS) nch l=60n w=1u m=1 nf=1 - - - M40 (net0120 B\<3\> VSS VSS) nch l=60n w=1u m=1 nf=1 - - - M37 (net0159 net0104 VSS VSS) nch l=60n w=1u m=1 nf=1 - - - M36 (net0158 net0105 VSS VSS) nch l=60n w=1u m=1 nf=1 - - - M35 (net0157 net0106 VSS VSS) nch l=60n w=1u m=1 nf=1 - - - M31 (net0104 B\<2\> VSS VSS) nch l=60n w=1u m=1 nf=1 - - - M30 (net0105 B\<1\> VSS VSS) nch l=60n w=1u m=1 nf=1 - - - M29 (net0106 B\<0\> VSS VSS) nch l=60n w=1u m=1 nf=1 - - - M18 (b3_buf b3_inv VSS VSS) nch l=60n w=1u m=1 nf=1 - - - M16 (b3_inv B\<3\> VSS VSS) nch l=60n w=1u m=1 nf=1 - - - M15 (b2_inv B\<2\> VSS VSS) nch l=60n w=1u m=1 nf=1 - - - M13 (b2_buf b2_inv VSS VSS) nch l=60n w=1u m=1 nf=1 - - - M11 (b1_buf b1_inv VSS VSS) nch l=60n w=1u m=1 nf=1 - - - M9 (b1_inv B\<1\> VSS VSS) nch l=60n w=1u m=1 nf=1 - - - M7 (b0_buf b0_inv VSS VSS) nch l=60n w=1u m=1 nf=1 - - - M4 (b0_inv B\<0\> VSS VSS) nch l=60n w=1u m=1 nf=1 - - - M42 (net0155 net0120 VDD VDD) pch l=60n w=1u m=1 nf=1 - - - M38 (net0120 B\<3\> VDD VDD) pch l=60n w=1u m=1 nf=1 - - - M34 (net0159 net0104 VDD VDD) pch l=60n w=1u m=1 nf=1 - - - M33 (net0158 net0105 VDD VDD) pch l=60n w=1u m=1 nf=1 - - - M32 (net0157 net0106 VDD VDD) pch l=60n w=1u m=1 nf=1 - - - M28 (net0104 B\<2\> VDD VDD) pch l=60n w=1u m=1 nf=1 - - - M27 (net0105 B\<1\> VDD VDD) pch l=60n w=1u m=1 nf=1 - - - M26 (net0106 B\<0\> VDD VDD) pch l=60n w=1u m=1 nf=1 - - - M19 (b3_inv B\<3\> VDD VDD) pch l=60n w=1u m=1 nf=1 - - - M17 (b3_buf b3_inv VDD VDD) pch l=60n w=1u m=1 nf=1 - - - M14 (b2_buf b2_inv VDD VDD) pch l=60n w=1u m=1 nf=1 - - - M12 (b2_inv B\<2\> VDD VDD) pch l=60n w=1u m=1 nf=1 - - - M10 (b1_buf b1_inv VDD VDD) pch l=60n w=1u m=1 nf=1 - - - M8 (b1_inv B\<1\> VDD VDD) pch l=60n w=1u m=1 nf=1 - - - M6 (b0_buf b0_inv VDD VDD) pch l=60n w=1u m=1 nf=1 - - - M5 (b0_inv B\<0\> VDD VDD) pch l=60n w=1u m=1 nf=1 - - - I14 (b2_inv net010 VSS) res_24K - I15 (b2_inv net07 VSS) res_24K - I16 (b1_inv net3 VSS) res_24K - I17 (b1_inv net1 VSS) res_24K - I18 (b0_inv net2 VSS) res_24K - I19 (b0_inv net4 VSS) res_24K -ends capbank_gp_lowC_noLSB_BPF -// End of subcircuit definition. - -// Library name: PhasedArray_WB_V2 -// Cell name: BPF4 -// View name: schematic -M2 (OUTP INM VSS VSS) nmos_rf lr=120.0n wr=2.5u nr=32 - -M8 (OUTM INP VSS VSS) nmos_rf lr=120.0n wr=2.5u nr=32 - -I5 (DIG_BPF\<3\> DIG_BPF\<2\> DIG_BPF\<1\> DIG_BPF\<0\> OUTM OUTP VDDSW - VSS) capbank_gp_lowC_noLSB_BPF -L4 (OUTM OUTP VSS VDD_BPF0P5) spiral_sym_ct_mu_z w=7u nr=3 rad=24.0u lay=9 - spacing=3u gdis=10u m=1 diff --git a/DesignDatabase/Design Examples Library/Wireless/WLESS3/README.md b/DesignDatabase/Design Examples Library/Wireless/WLESS3/README.md deleted file mode 100644 index 5fb1116d52..0000000000 --- a/DesignDatabase/Design Examples Library/Wireless/WLESS3/README.md +++ /dev/null @@ -1,13 +0,0 @@ -Bandpass filter circuit - -Files present: - -1. Netlist with sizing - -2. Schematic - -3. Layout - -To be added: - -- Testbench diff --git a/DesignDatabase/Design Examples Library/Wireless/WLESS3/Schematic/WLESS3_image.jpg b/DesignDatabase/Design Examples Library/Wireless/WLESS3/Schematic/WLESS3_image.jpg deleted file mode 100644 index bd38a48606..0000000000 Binary files a/DesignDatabase/Design Examples Library/Wireless/WLESS3/Schematic/WLESS3_image.jpg and /dev/null differ diff --git a/DesignDatabase/Design Examples Library/Wireless/WLESS4/Layout/WLESS4_image.png b/DesignDatabase/Design Examples Library/Wireless/WLESS4/Layout/WLESS4_image.png deleted file mode 100644 index 7492c2970b..0000000000 Binary files a/DesignDatabase/Design Examples Library/Wireless/WLESS4/Layout/WLESS4_image.png and /dev/null differ diff --git a/DesignDatabase/Design Examples Library/Wireless/WLESS4/Netlist/WLESS4_netlist.txt b/DesignDatabase/Design Examples Library/Wireless/WLESS4/Netlist/WLESS4_netlist.txt deleted file mode 100644 index f924247386..0000000000 --- a/DesignDatabase/Design Examples Library/Wireless/WLESS4/Netlist/WLESS4_netlist.txt +++ /dev/null @@ -1,177 +0,0 @@ - -// Library name: PhasedArray_WB_V2 -// Cell name: res_24K -// View name: schematic -subckt res_24K t1 t2 vss - R4 (t2 net05 vss) rppolywo_rf l=8u w=500n m=1 - R2 (net06 net05 vss) rppolywo_rf l=8u w=500n m=1 - R1 (net06 net6 vss) rppolywo_rf l=8u w=500n m=1 - R0 (t1 net6 vss) rppolywo_rf l=8u w=500n m=1 -ends res_24K -// End of subcircuit definition. - -// Library name: PhasedArray_WB_V2 -// Cell name: capbank_gp_lowC_noLSB -// View name: schematic -subckt capbank_gp_lowC_noLSB B\<3\> B\<2\> B\<1\> B\<0\> LEFT RIGHT VDD VSS - C9 (LEFT net06 VSS) mimcap_woum_sin_rf lt=16.0u wt=16.0u lay=7 m=2 - - C8 (RIGHT net08 VSS) mimcap_woum_sin_rf lt=16.0u wt=16.0u lay=7 m=2 - - C5 (RIGHT net07 VSS) mimcap_woum_sin_rf lt=16.0u wt=16.0u lay=7 m=1 - - C4 (LEFT net010 VSS) mimcap_woum_sin_rf lt=16.0u wt=16.0u lay=7 m=1 - - C3 (RIGHT net3 VSS) mimcap_woum_sin_rf lt=8u wt=8u lay=7 m=2 - - C2 (LEFT net1 VSS) mimcap_woum_sin_rf lt=8u wt=8u lay=7 m=2 - - C1 (RIGHT net4 VSS) mimcap_woum_sin_rf lt=8u wt=8u lay=7 m=1 - - C0 (LEFT net2 VSS) mimcap_woum_sin_rf lt=8u wt=8u lay=7 m=1 - - M3 (net08 b3_buf net06 VSS) nmos_rf lr=60n wr=2u nr=20 sigma=1 m=10 - - M2 (net010 b2_buf net07 VSS) nmos_rf lr=60n wr=2u nr=20 sigma=1 m=5 - - M1 (net1 b1_buf net3 VSS) nmos_rf lr=60n wr=2u nr=20 sigma=1 m=2 - - M0 (net2 b0_buf net4 VSS) nmos_rf lr=60n wr=2u nr=20 sigma=1 m=1 - - M44 (net0155 net0120 VSS VSS) nch l=60n w=1u m=1 nf=1 - - - M40 (net0120 B\<3\> VSS VSS) nch l=60n w=1u m=1 nf=1 - - - M37 (net0159 net0104 VSS VSS) nch l=60n w=1u m=1 nf=1 - - - M36 (net0158 net0105 VSS VSS) nch l=60n w=1u m=1 nf=1 - - - M35 (net0157 net0106 VSS VSS) nch l=60n w=1u m=1 nf=1 - - - M31 (net0104 B\<2\> VSS VSS) nch l=60n w=1u m=1 nf=1 - - - M30 (net0105 B\<1\> VSS VSS) nch l=60n w=1u m=1 nf=1 - - - M29 (net0106 B\<0\> VSS VSS) nch l=60n w=1u m=1 nf=1 - - - M18 (b3_buf b3_inv VSS VSS) nch l=60n w=1u m=1 nf=1 - - - M16 (b3_inv B\<3\> VSS VSS) nch l=60n w=1u m=1 nf=1 - - - M15 (b2_inv B\<2\> VSS VSS) nch l=60n w=1u m=1 nf=1 - - - M13 (b2_buf b2_inv VSS VSS) nch l=60n w=1u m=1 nf=1 - - - M11 (b1_buf b1_inv VSS VSS) nch l=60n w=1u m=1 nf=1 - - - M9 (b1_inv B\<1\> VSS VSS) nch l=60n w=1u m=1 nf=1 - - - M7 (b0_buf b0_inv VSS VSS) nch l=60n w=1u m=1 nf=1 - - - M4 (b0_inv B\<0\> VSS VSS) nch l=60n w=1u m=1 nf=1 - - - M42 (net0155 net0120 VDD VDD) pch l=60n w=1u m=1 nf=1 - - - M38 (net0120 B\<3\> VDD VDD) pch l=60n w=1u m=1 nf=1 - - - M34 (net0159 net0104 VDD VDD) pch l=60n w=1u m=1 nf=1 - - - M33 (net0158 net0105 VDD VDD) pch l=60n w=1u m=1 nf=1 - - - M32 (net0157 net0106 VDD VDD) pch l=60n w=1u m=1 nf=1 - - - M28 (net0104 B\<2\> VDD VDD) pch l=60n w=1u m=1 nf=1 - - - M27 (net0105 B\<1\> VDD VDD) pch l=60n w=1u m=1 nf=1 - - - M26 (net0106 B\<0\> VDD VDD) pch l=60n w=1u m=1 nf=1 - - - M19 (b3_inv B\<3\> VDD VDD) pch l=60n w=1u m=1 nf=1 - - - M17 (b3_buf b3_inv VDD VDD) pch l=60n w=1u m=1 nf=1 - - - M14 (b2_buf b2_inv VDD VDD) pch l=60n w=1u m=1 nf=1 - - - M12 (b2_inv B\<2\> VDD VDD) pch l=60n w=1u m=1 nf=1 - - - M10 (b1_buf b1_inv VDD VDD) pch l=60n w=1u m=1 nf=1 - - - M8 (b1_inv B\<1\> VDD VDD) pch l=60n w=1u m=1 nf=1 - - - M6 (b0_buf b0_inv VDD VDD) pch l=60n w=1u m=1 nf=1 - - - M5 (b0_inv B\<0\> VDD VDD) pch l=60n w=1u m=1 nf=1 - - I12 (b3_inv net08 VSS) res_24K - I13 (b3_inv net06 VSS) res_24K - I14 (b2_inv net010 VSS) res_24K - I15 (b2_inv net07 VSS) res_24K - I16 (b1_inv net3 VSS) res_24K - I17 (b1_inv net1 VSS) res_24K - I18 (b0_inv net2 VSS) res_24K - I19 (b0_inv net4 VSS) res_24K -ends capbank_gp_lowC_noLSB -// End of subcircuit definition. - -// Library name: PhasedArray_WB_V2 -// Cell name: VCO -// View name: schematic -subckt VCO DIG_VCO\<3\> DIG_VCO\<2\> DIG_VCO\<1\> DIG_VCO\<0\> OUTM OUTP VDDSW VDD_VCO0P5 VSS - M0 (OUTP OUTM VSS VSS) nmos_rf lr=60n wr=1u nr=25 sigma=1 m=2 - M1 (OUTM OUTP VSS VSS) nmos_rf lr=60n wr=1u nr=25 sigma=1 m=2 - I10 (DIG_VCO\<3\> DIG_VCO\<2\> DIG_VCO\<1\> DIG_VCO\<0\> OUTM OUTP VDDSW VSS) capbank_gp_lowC_noLSB - L4 (OUTP OUTM VSS VDD_VCO0P5) spiral_sym_ct_mu_z w=9u nr=2 rad=27.0u - ends VCO -// End of subcircuit definition. - -// Library name: PhasedArray_WB_V2 -// Cell name: ILO_IN -// View name: schematic -subckt ILO_IN IN OUT VDDSW VSS - C2 (IN net7 VSS) mimcap_woum_sin_rf lt=20u wt=20u lay=7 m=1 - R3 (VSS net7 VSS) rppolywo_rf l=12.0u w=1u m=1 - R2 (net7 VDDSW VSS) rppolywo_rf l=12.0u w=1u m=1 - M3 (OUT net7 VSS VSS) nmos_rf lr=60n wr=1u nr=32 sigma=1 m=1 - -ends ILO_IN -// End of subcircuit definition. - -// Library name: PhasedArray_WB_V2 -// Cell name: ILO -// View name: schematic -I11 (DIG_VCO\<3\> DIG_VCO\<2\> DIG_VCO\<1\> DIG_VCO\<0\> OUTM OUTP VDDSW VDD_VCO0P5 VSS) VCO -L0 (OUTM net5) inductor l=pind_in_ILO -L1 (OUTP net6) inductor l=pind_in_ILO -I12 (INP net5 VDDSW VSS) ILO_IN -I13 (INM net6 VDDSW VSS) ILO_IN diff --git a/DesignDatabase/Design Examples Library/Wireless/WLESS4/README.md b/DesignDatabase/Design Examples Library/Wireless/WLESS4/README.md deleted file mode 100644 index 76efa28d98..0000000000 --- a/DesignDatabase/Design Examples Library/Wireless/WLESS4/README.md +++ /dev/null @@ -1,13 +0,0 @@ -Oscillator circuit - -Files present: - -1. Netlist with sizing - -2. Schematic - -3. Layout - -To be added: - -- Testbench diff --git a/DesignDatabase/Design Examples Library/Wireless/WLESS4/Schematic/WLESS4_image.jpg b/DesignDatabase/Design Examples Library/Wireless/WLESS4/Schematic/WLESS4_image.jpg deleted file mode 100644 index 46a9457699..0000000000 Binary files a/DesignDatabase/Design Examples Library/Wireless/WLESS4/Schematic/WLESS4_image.jpg and /dev/null differ diff --git a/DesignDatabase/Design Examples Library/Wireline/README.md b/DesignDatabase/Design Examples Library/Wireline/README.md deleted file mode 100644 index c68d637f3a..0000000000 --- a/DesignDatabase/Design Examples Library/Wireline/README.md +++ /dev/null @@ -1,7 +0,0 @@ -This folder contains example ANALOG circuits (some of which have been taped out) that can be used as benchmarks. - -W1 : Single to differential converter - -W2 : Adder - -W3 : Variable gain amplifier \ No newline at end of file diff --git a/DesignDatabase/Design Examples Library/Wireline/W1/Netlist/W1.sp b/DesignDatabase/Design Examples Library/Wireline/W1/Netlist/W1.sp deleted file mode 100644 index 9e005122bb..0000000000 --- a/DesignDatabase/Design Examples Library/Wireline/W1/Netlist/W1.sp +++ /dev/null @@ -1,35 +0,0 @@ -// Generated for: spectre -// Generated on: Jun 2 02:57:04 2019 -// Design library name: EQ_12nm -// Design cell name: SDC_top -// Design view name: schematic -simulator lang=spectre -global VDD! VSS! - -.param cload=10f ccoup=50f nfpf=30 ngf=1 rbias=20k rload=900 \ - vbias=600m vps=0.85 -// Library name: EQ_12nm -// Cell name: SDC_top -// View name: schematic - -.subckt nfet2x d g s b -.param p1=30 - MN0 d g n1 b nfet l=0.014u nfin=p1 - MN1 n1 g s b nfet l=0.014u nfin=p1 -.ends nfet2x - -.subckt sdc vb vin vout_sdc1 vout_sdc2 vps vgnd -.param fin_count=24 rb=20k rl=900 cc=48f cl=12f - - xI0 vd net1 vs vgnd nfet2x p1=fin_count - R2 vb net1 resistor r=rb - R1 vs vgnd resistor r=rl - R0 vps vd resistor r=rl - C2 vs vout_sdc2 capacitor c=cl - C1 vd vout_sdc1 capacitor c=cl - C0 vin net1 capacitor c=cc -.ends sdc - - - - diff --git a/DesignDatabase/Design Examples Library/Wireline/W1/README.md b/DesignDatabase/Design Examples Library/Wireline/W1/README.md deleted file mode 100644 index 19ccb5d992..0000000000 --- a/DesignDatabase/Design Examples Library/Wireline/W1/README.md +++ /dev/null @@ -1,13 +0,0 @@ -Single to differential converter - -Files present: - -1. Netlist with sizing - -To be added - -- Schematic snapshot - -- Layout snapshot - -- Testbench diff --git a/DesignDatabase/Design Examples Library/Wireline/W2/Netlist/adder.sp b/DesignDatabase/Design Examples Library/Wireline/W2/Netlist/adder.sp deleted file mode 100644 index a252590782..0000000000 --- a/DesignDatabase/Design Examples Library/Wireline/W2/Netlist/adder.sp +++ /dev/null @@ -1,39 +0,0 @@ -// Generated for: spectre -// Generated on: Jun 4 11:15:16 2019 -// Design library name: EQ_12nm -// Design cell name: Adder_top -// Design view name: schematic -simulator lang=spectre -global VDD! VSS! - -.param cload_adder=10f vps=0.85 ccoup_adder=50f nfpf_adder=50 \ - ngf_adder=1 rbias_adder=20K rload_adder=500 vbias_nfet_adder=600m \ - vbias_pfet_adder=450m - -// Library name: EQ_12nm -// Cell name: Adder_top -// View name: schematic - -.subckt nfet2x d g s b -.param p1=2 - MN0 d g n1 b nfet l=0.014u nfin=p1 - MN1 n1 g s b nfet l=0.014u nfin=p1 -.ends nfet2x - -.subckt pfet2x d g s b -.param p1=2 - MP0 d g n1 b pfet l=0.014u nfin=p1 - MP1 n1 g s b pfet l=0.014u nfin=p1 -.ends pfet2x - -.subckt adder n1 n2 vin vout vps vgnd -.param cc=48f nfpf=48 rb=20K rl=500 - - xI0 vout vbn1 vgnd vgnd nfet2x p1=nfpf - xI1 vout vbp1 vps vps pfet2x p1=nfpf - R0 vbn1 n1 resistor r=rb - C0 vin vbn1 capacitor c=cc - R1 vbp1 n2 resistor r=rb - C1 vin vbp1 capacitor c=cc - R2 vps vout resistor r=rl -.ends adder diff --git a/DesignDatabase/Design Examples Library/Wireline/W2/README.md b/DesignDatabase/Design Examples Library/Wireline/W2/README.md deleted file mode 100644 index 4bd982127f..0000000000 --- a/DesignDatabase/Design Examples Library/Wireline/W2/README.md +++ /dev/null @@ -1,13 +0,0 @@ -Adder - -Files present: - -1. Netlist with sizing - -To be added - -- Schematic snapshot - -- Layout snapshot - -- Testbench diff --git a/DesignDatabase/Design Examples Library/Wireline/W3/Netlist/W3.sp b/DesignDatabase/Design Examples Library/Wireline/W3/Netlist/W3.sp deleted file mode 100644 index 57bbe443c6..0000000000 --- a/DesignDatabase/Design Examples Library/Wireline/W3/Netlist/W3.sp +++ /dev/null @@ -1,41 +0,0 @@ -// Generated for: spectre -// Generated on: Jun 3 13:08:52 2019 -// Design library name: EQ_12nm -// Design cell name: VGA_top -// Design view name: schematic -simulator lang=spectre -global VDD! VSS! - - -// Library name: EQ_12nm -// Cell name: VGA_top -// View name: schematic -.subckt nfet2x d g s b -.param p1=2 - MN0 d g n1 b nfet l=0.014u nfin=p1 - MN1 n1 g s b nfet l=0.014u nfin=p1 -.ends nfet2x - -// current mirror -.subckt vga vmirror_vga s0 s1 s2 vin1 vin2 vout_vga1 vout_vga2 vps vgnd -.param nfpf_sw=72 nfpf_sw_2=144 nfpf_sw_4=288 cload=12f nfpf_cm=72 nfpf_cm_2=144 nfpf_cm_4=288 nfpf_dp=48 nfpf_dp_2=96 nfpf_dp_4=192 rl=400 - - xI03 vmirror_vga vmirror_vga vgnd vgnd nfet2x p1=nfpf_cm - xI02 net3 vmirror_vga vgnd vgnd nfet2x p1=nfpf_cm - xI01 vout_vga2 vin2 net3 vgnd nfet2x p1=nfpf_dp - xI00 vout_vga1 vin1 net3 vgnd nfet2x p1=nfpf_dp - Msw0 net5 s0 net5p vgnd nfet l=0.014u nfin=nfpf_sw - xI12 net5p vmirror_vga vgnd vgnd nfet2x p1=nfpf_cm - xI11 vout_vga2 vin2 net5 vgnd nfet2x p1=nfpf_dp - xI10 vout_vga1 vin1 net5 vgnd nfet2x p1=nfpf_dp - Msw1 net4 s1 net4p vgnd nfet l=0.014u nfin=nfpf_sw_2 - xI22 net4p vmirror_vga vgnd vgnd nfet2x p1=nfpf_cm_2 - xI21 vout_vga2 vin2 net4 vgnd nfet2x p1=nfpf_dp_2 - xI20 vout_vga1 vin1 net4 vgnd nfet2x p1=nfpf_dp_2 - Msw2 net6 s2 net6p vgnd nfet l=0.014u nfin=nfpf_sw_4 - xI32 net6p vmirror_vga vgnd vgnd nfet2x p1=nfpf_cm_4 - xI31 vout_vga2 vin2 net6 vgnd nfet2x p1=nfpf_dp_4 - xI30 vout_vga1 vin1 net6 vgnd nfet2x p1=nfpf_dp_4 - R5 vps vout_vga2 resistor r=rl - R6 vps vout_vga1 resistor r=rl -.ends vga \ No newline at end of file diff --git a/DesignDatabase/Design Examples Library/Wireline/W3/README.md b/DesignDatabase/Design Examples Library/Wireline/W3/README.md deleted file mode 100644 index ec820a1dd2..0000000000 --- a/DesignDatabase/Design Examples Library/Wireline/W3/README.md +++ /dev/null @@ -1,13 +0,0 @@ -Variable gain amplifier - -Files present: - -1. Netlist with sizing - -To be added - -- Schematic snapshot - -- Layout snapshot - -- Testbench diff --git a/DesignDatabase/DesignExamplesLibrary/Analog/A1/Netlist/A1 b/DesignDatabase/DesignExamplesLibrary/Analog/A1/Netlist/A1 deleted file mode 100644 index ec24d48480..0000000000 --- a/DesignDatabase/DesignExamplesLibrary/Analog/A1/Netlist/A1 +++ /dev/null @@ -1,36 +0,0 @@ -// Generated for: spectre -// Generated on: Nov 2 11:59:19 2018 -// Design library name: DC_converter -// Design cell name: -//2018_11_2_fully_diff_cascoded_current_mirror_ota_symbol_database -// Design view name: schematic -simulator lang=spectre -global 0 vdd! - -// Library name: DC_converter -// Cell name: -//2018_11_2_fully_diff_cascoded_current_mirror_ota_symbol_database -// View name: schematic -M15 (net020 Vbiasp net021 net021) pch l=130.0n w=3u m=1 nf=1 -M14 (net010 Vbiasp net013 net013) pch l=130.0n w=3u m=1 nf=1 -M5 (Voutn Vbiasp net6 net6) pch l=200n w=12.305u m=1 nf=1 -M4 (net6 net010 vdd! vdd!) pch l=200n w=10.77u m=1 nf=1 -M3 (Voutp Vbiasp net23 net23) pch l=200n w=12.305u m=1 nf=1 -M2 (net23 net020 vdd! vdd!) pch l=200n w=10.77u m=1 nf=1 -M1 (net021 net020 vdd! vdd!) pch l=130.0n w=4.25u m=1 nf=1 -M0 (net013 net010 vdd! vdd!) pch l=130.0n w=4.25u m=1 nf=1 -M13 (net11 net11 0 0) nch l=130.0n w=2u m=1 nf=1 -M12 (net17 net11 0 0) nch l=130.0n w=2u m=1 nf=1 -M11 (Voutp Vbiasn net38 0) nch l=200n w=10.9u m=1 nf=1 -M10 (net38 Vbiasnd 0 0) nch l=300n w=11.5u m=1 nf=1 -M9 (Voutn Vbiasn net39 0) nch l=200n w=10.9u m=1 nf=1 -M8 (net39 Vbiasnd 0 0) nch l=300n w=11.5u m=1 nf=1 -M7 (net020 Vinp net17 0) nch l=130.0n w=3.56u m=1 nf=1 -M6 (net010 Vinn net17 0) nch l=130.0n w=3.56u m=1 nf=1 -I4 (vdd! net11) isource dc=200u type=dc -V2 (Vbiascmfb 0) vsource dc=449m type=dc -V1 (Vbiasn 0) vsource dc=700m type=dc -V0 (Vbiasp 0) vsource dc=410m type=dc -C1 (Voutp Vbiasnd) capacitor c=10f -C0 (Voutn Vbiasnd) capacitor c=10f - diff --git a/DesignDatabase/DesignExamplesLibrary/Analog/A1/README.md b/DesignDatabase/DesignExamplesLibrary/Analog/A1/README.md deleted file mode 100644 index d1f0fcbca1..0000000000 --- a/DesignDatabase/DesignExamplesLibrary/Analog/A1/README.md +++ /dev/null @@ -1,13 +0,0 @@ -Fully differential current mirror OTA - -Files present: - -1. Netlist with sizing - -To be added - -- Schematic snapshot - -- Layout snapshot - -- Testbench diff --git a/DesignDatabase/DesignExamplesLibrary/Analog/A2/Layout/A2_image.png b/DesignDatabase/DesignExamplesLibrary/Analog/A2/Layout/A2_image.png deleted file mode 100644 index c234340038..0000000000 Binary files a/DesignDatabase/DesignExamplesLibrary/Analog/A2/Layout/A2_image.png and /dev/null differ diff --git a/DesignDatabase/DesignExamplesLibrary/Analog/A2/Netlist/A2 b/DesignDatabase/DesignExamplesLibrary/Analog/A2/Netlist/A2 deleted file mode 100644 index 574cb13260..0000000000 --- a/DesignDatabase/DesignExamplesLibrary/Analog/A2/Netlist/A2 +++ /dev/null @@ -1,34 +0,0 @@ -// Generated for: spectre -// Generated on: Nov 2 10:37:45 2018 -// Design library name: DC_converter -// Design cell name: 23Dec_2017_comparator_symbol -// Design view name: schematic -simulator lang=spectre -global 0 - -// Library name: DC_converter -// Cell name: 23Dec_2017_comparator_symbol -// View name: schematic -M21 (net44 cgnd Vdd Vdd) pch l=1.32u w=120.0n m=1 nf=1 -M5 (net10 Vn net7 cgnd) nmos_rf lr=120.0n wr=600n nr=1 -M0 (net5 Vp net7 cgnd) nmos_rf lr=120.0n wr=600n nr=1 -M11 (net7 net44 cgnd cgnd) nmos_rf lr=120.0n wr=1.2u nr=1 -M9 (net44 net44 cgnd cgnd) nmos_rf lr=120.0n wr=600n nr=1 -M10 (Vop Von net18 cgnd) nmos_rf lr=120.0n wr=600n nr=1 -M8 (Von Vop net18 cgnd) nmos_rf lr=120.0n wr=600n nr=1 -M7 (Von Von net18 cgnd) nmos_rf lr=120.0n wr=600n nr=1 -M6 (Vop Vop net18 cgnd) nmos_rf lr=120.0n wr=600n nr=1 -M20 (net18 net18 cgnd cgnd) nmos_rf lr=120.0n wr=6u nr=1 -M18 (net17 net13 cgnd cgnd) nmos_rf lr=120.0n wr=600n nr=1 -M16 (Vout net23 cgnd cgnd) nmos_rf lr=120.0n wr=600n nr=1 -M14 (net23 Vop net17 cgnd) nmos_rf lr=120.0n wr=600n nr=1 -M12 (net13 Von net17 cgnd) nmos_rf lr=120.0n wr=600n nr=1 -M3 (Vop net5 Vdd Vdd) pmos_rf lr=240.0n wr=1.8u nr=1 -M2 (net5 net5 Vdd Vdd) pmos_rf lr=240.0n wr=1.8u nr=1 -M4 (Von net10 Vdd Vdd) pmos_rf lr=240.0n wr=1.8u nr=1 -M1 (net10 net10 Vdd Vdd) pmos_rf lr=240.0n wr=1.8u nr=1 -M19 (net14 net13 Vdd Vdd) pmos_rf lr=120.0n wr=900n nr=1 -M17 (Vout net23 Vdd Vdd) pmos_rf lr=120.0n wr=900n nr=1 -M15 (net23 Vop net14 net14) pmos_rf lr=120.0n wr=900n nr=1 -M13 (net13 Von net14 net14) pmos_rf lr=120.0n wr=900n nr=1 - diff --git a/DesignDatabase/DesignExamplesLibrary/Analog/A2/README.md b/DesignDatabase/DesignExamplesLibrary/Analog/A2/README.md deleted file mode 100644 index f2d658e4aa..0000000000 --- a/DesignDatabase/DesignExamplesLibrary/Analog/A2/README.md +++ /dev/null @@ -1,14 +0,0 @@ -Comparator (not clocked) - -Files present: - -1. Netlist with sizing - -2. Schematic snapshot - -3. Layout snapshot - -4. Testbench - a. Netlist - b. Performance specifications - c. Constraints diff --git a/DesignDatabase/DesignExamplesLibrary/Analog/A2/Schematic/A2_image.png b/DesignDatabase/DesignExamplesLibrary/Analog/A2/Schematic/A2_image.png deleted file mode 100644 index 4c32eb0779..0000000000 Binary files a/DesignDatabase/DesignExamplesLibrary/Analog/A2/Schematic/A2_image.png and /dev/null differ diff --git a/DesignDatabase/DesignExamplesLibrary/Analog/A2/Testbench/Constraints/A2_constraints.txt b/DesignDatabase/DesignExamplesLibrary/Analog/A2/Testbench/Constraints/A2_constraints.txt deleted file mode 100644 index a8b39e4146..0000000000 --- a/DesignDatabase/DesignExamplesLibrary/Analog/A2/Testbench/Constraints/A2_constraints.txt +++ /dev/null @@ -1,11 +0,0 @@ -Constraints for the comparator circuit - -Initial pre-amplifier stage -- matching between the differential pair and current mirror -- symmetry - -Decision making stage -- symmetry - -Output buffer -- None \ No newline at end of file diff --git a/DesignDatabase/DesignExamplesLibrary/Analog/A2/Testbench/Netlist/A2_testbench.txt b/DesignDatabase/DesignExamplesLibrary/Analog/A2/Testbench/Netlist/A2_testbench.txt deleted file mode 100644 index 10d402ba50..0000000000 --- a/DesignDatabase/DesignExamplesLibrary/Analog/A2/Testbench/Netlist/A2_testbench.txt +++ /dev/null @@ -1,70 +0,0 @@ -// Generated for: spectre -// Generated on: Apr 28 17:49:09 2019 -// Design library name: DC_converter -// Design cell name: 2019_04_28_comparator_testbench -// Design view name: schematic -simulator lang=spectre -global 0 - -// Library name: DC_converter -// Cell name: 23Dec_2017_comparator_symbol -// View name: schematic -subckt DC_converter_23Dec_2017_comparator_symbol_schematic Vn Vout Vp Vdd \ - cgnd - M21 (net44 cgnd Vdd Vdd) pch l=1.32u w=120.0n m=1 nf=1 - - - M5 (net10 Vn net7 cgnd) nmos_rf lr=120.0n wr=600n nr=1 sigma=1 m=1 - - M0 (net5 Vp net7 cgnd) nmos_rf lr=120.0n wr=600n nr=1 sigma=1 m=1 - - M11 (net7 net44 cgnd cgnd) nmos_rf lr=120.0n wr=1.2u nr=1 sigma=1 m=1 - - M9 (net44 net44 cgnd cgnd) nmos_rf lr=120.0n wr=600n nr=1 sigma=1 m=1 - - M10 (Vop Von net18 cgnd) nmos_rf lr=120.0n wr=600n nr=1 sigma=1 m=1 - - M8 (Von Vop net18 cgnd) nmos_rf lr=120.0n wr=600n nr=1 sigma=1 m=1 - - M7 (Von Von net18 cgnd) nmos_rf lr=120.0n wr=600n nr=1 sigma=1 m=1 - - M6 (Vop Vop net18 cgnd) nmos_rf lr=120.0n wr=600n nr=1 sigma=1 m=1 - - M20 (net18 net18 cgnd cgnd) nmos_rf lr=120.0n wr=6u nr=1 sigma=1 m=1 - - M18 (net17 net13 cgnd cgnd) nmos_rf lr=120.0n wr=600n nr=1 sigma=1 m=1 - - M16 (Vout net23 cgnd cgnd) nmos_rf lr=120.0n wr=600n nr=1 sigma=1 m=1 - - M14 (net23 Vop net17 cgnd) nmos_rf lr=120.0n wr=600n nr=1 sigma=1 m=1 - - M12 (net13 Von net17 cgnd) nmos_rf lr=120.0n wr=600n nr=1 sigma=1 m=1 - - M3 (Vop net5 Vdd Vdd) pmos_rf lr=240.0n wr=1.8u nr=1 sigma=1 m=1 - - M2 (net5 net5 Vdd Vdd) pmos_rf lr=240.0n wr=1.8u nr=1 sigma=1 m=1 - - M4 (Von net10 Vdd Vdd) pmos_rf lr=240.0n wr=1.8u nr=1 sigma=1 m=1 - - M1 (net10 net10 Vdd Vdd) pmos_rf lr=240.0n wr=1.8u nr=1 sigma=1 m=1 - - M19 (net14 net13 Vdd Vdd) pmos_rf lr=120.0n wr=900n nr=1 sigma=1 m=1 - - M17 (Vout net23 Vdd Vdd) pmos_rf lr=120.0n wr=900n nr=1 sigma=1 m=1 - - M15 (net23 Vop net14 net14) pmos_rf lr=120.0n wr=900n nr=1 sigma=1 m=1 - - M13 (net13 Von net14 net14) pmos_rf lr=120.0n wr=900n nr=1 sigma=1 m=1 - -ends DC_converter_23Dec_2017_comparator_symbol_schematic -// End of subcircuit definition. - -// Library name: DC_converter -// Cell name: 2019_04_28_comparator_testbench -// View name: schematic -I0 (vn vout vp vdd vss) DC_converter_23Dec_2017_comparator_symbol_schematic -V3 (vss 0) vsource dc=0 type=dc -V2 (vp 0) vsource dc=500m type=dc -V0 (vdd 0) vsource dc=1 type=dc -V1 (vn 0) vsource dc=500m type=sine ampl=500m freq=100M - diff --git a/DesignDatabase/DesignExamplesLibrary/Analog/A2/Testbench/Performance Specifications/Falling_time.png b/DesignDatabase/DesignExamplesLibrary/Analog/A2/Testbench/Performance Specifications/Falling_time.png deleted file mode 100644 index cfa131df3a..0000000000 Binary files a/DesignDatabase/DesignExamplesLibrary/Analog/A2/Testbench/Performance Specifications/Falling_time.png and /dev/null differ diff --git a/DesignDatabase/DesignExamplesLibrary/Analog/A2/Testbench/Performance Specifications/README.md b/DesignDatabase/DesignExamplesLibrary/Analog/A2/Testbench/Performance Specifications/README.md deleted file mode 100644 index 55ed7fe85e..0000000000 --- a/DesignDatabase/DesignExamplesLibrary/Analog/A2/Testbench/Performance Specifications/README.md +++ /dev/null @@ -1,12 +0,0 @@ -Comparator performance specifications - -The negative input is kept constant while the positive input is increased and decreased to evaluate the performance. - -1. Rise time - The output rises 2ns after the positive input becomes greater than the negative input. This limits the speed of operation to less than 500 MHz. - -2. Fall time - The output falls 2ns after the positive input becomes less than the negative input. This limits the speed of operation to less than 500 MHz. - -3. Hysteresis - This comparator has no hysteresis. Output switches from high to low and low to high at the same voltage. - -4. Power consumption - Power consumption of this comparator is approximately 23uW. - diff --git a/DesignDatabase/DesignExamplesLibrary/Analog/A2/Testbench/Performance Specifications/Rising_time.png b/DesignDatabase/DesignExamplesLibrary/Analog/A2/Testbench/Performance Specifications/Rising_time.png deleted file mode 100644 index 1e6ec3f00a..0000000000 Binary files a/DesignDatabase/DesignExamplesLibrary/Analog/A2/Testbench/Performance Specifications/Rising_time.png and /dev/null differ diff --git a/DesignDatabase/DesignExamplesLibrary/Analog/A3/Layout/A3.PNG b/DesignDatabase/DesignExamplesLibrary/Analog/A3/Layout/A3.PNG deleted file mode 100644 index bc4000ca35..0000000000 Binary files a/DesignDatabase/DesignExamplesLibrary/Analog/A3/Layout/A3.PNG and /dev/null differ diff --git a/DesignDatabase/DesignExamplesLibrary/Analog/A3/Netlist/A3 b/DesignDatabase/DesignExamplesLibrary/Analog/A3/Netlist/A3 deleted file mode 100644 index f078ecdd3d..0000000000 --- a/DesignDatabase/DesignExamplesLibrary/Analog/A3/Netlist/A3 +++ /dev/null @@ -1,37 +0,0 @@ -// Generated for: spectre -// Generated on: Nov 8 14:55:46 2018 -// Design library name: EnergyHarvesting -// Design cell name: Comp -// Design view name: schematic -simulator lang=spectre -global 0 - -// Library name: DC_converter -// Cell name: NOR -// View name: schematic -subckt NOR GND VDD VIN1 VIN2 VOUT - M0 (VOUT VIN1 GND GND) nch l=60n w=150.0n m=1 nf=1 - M1 (VOUT VIN2 GND GND) nch l=60n w=150.0n m=1 nf=1 - M3 (VOUT VIN1 net14 VDD) pch l=60n w=600n m=1 nf=1 - M2 (net14 VIN2 VDD VDD) pch l=60n w=600n m=1 nf=1 -ends NOR -// End of subcircuit definition. - -// Library name: EnergyHarvesting -// Cell name: Comp -// View name: schematic -M2 (OUT OUTP net021 VDD) pch l=60n w=3u m=1 nf=1 -M4 (OUTP OUT net020 VDD) pch l=60n w=3u m=1 nf=1 -M3 (net023 CLK VDD VDD) pch l=60n w=300n m=1 nf=1 -I1 (GND VDD OUT Q QB) NOR -I0 (GND VDD OUTP QB Q) NOR -M0 (net020 VINP net023 VDD) pch_25 l=20u w=400n m=1 nf=1 -M1 (net021 VINN net023 VDD) pch_25 l=20u w=400n m=1 nf=1 -M12 (net021 CLK GND GND) nch l=60n w=120.0n m=1 nf=1 -M11 (net020 CLK GND GND) nch l=60n w=120.0n m=1 nf=1 -M10 (net020 CLK net021 GND) nch l=60n w=120.0n m=1 nf=1 -M9 (OUT CLK GND GND) nch l=60n w=200n m=1 nf=1 -M6 (OUT OUTP GND GND) nch l=60n w=200n m=1 nf=1 -M7 (OUTP OUT GND GND) nch l=60n w=200n m=1 nf=1 -M8 (OUTP CLK GND GND) nch l=60n w=200n m=1 nf=1 - diff --git a/DesignDatabase/DesignExamplesLibrary/Analog/A3/README.md b/DesignDatabase/DesignExamplesLibrary/Analog/A3/README.md deleted file mode 100644 index b899f82713..0000000000 --- a/DesignDatabase/DesignExamplesLibrary/Analog/A3/README.md +++ /dev/null @@ -1,13 +0,0 @@ -Clocked Comparator - -Files present : - -1. Netlist with sizing - -2. Schematic - -3. Layout - -To be added : - -- Testbench diff --git a/DesignDatabase/DesignExamplesLibrary/Analog/A3/Schematic/A3.PNG b/DesignDatabase/DesignExamplesLibrary/Analog/A3/Schematic/A3.PNG deleted file mode 100644 index 3e570de7e5..0000000000 Binary files a/DesignDatabase/DesignExamplesLibrary/Analog/A3/Schematic/A3.PNG and /dev/null differ diff --git a/DesignDatabase/DesignExamplesLibrary/Analog/A4/Layout/A4.PNG b/DesignDatabase/DesignExamplesLibrary/Analog/A4/Layout/A4.PNG deleted file mode 100644 index 073ef45ae4..0000000000 Binary files a/DesignDatabase/DesignExamplesLibrary/Analog/A4/Layout/A4.PNG and /dev/null differ diff --git a/DesignDatabase/DesignExamplesLibrary/Analog/A4/Netlist/A4 b/DesignDatabase/DesignExamplesLibrary/Analog/A4/Netlist/A4 deleted file mode 100644 index be679e487e..0000000000 --- a/DesignDatabase/DesignExamplesLibrary/Analog/A4/Netlist/A4 +++ /dev/null @@ -1,62 +0,0 @@ -// Generated for: spectre -// Generated on: Nov 8 15:11:28 2018 -// Design library name: EnergyHarvesting -// Design cell name: NON_OVLP3 -// Design view name: schematic -simulator lang=spectre -global 0 - - -// Library name: DC_converter -// Cell name: NOR -// View name: schematic -subckt NOR GND VDD VIN1 VIN2 VOUT - M0 (VOUT VIN1 GND GND) nch l=60n w=150.0n m=1 nf=1 - M1 (VOUT VIN2 GND GND) nch l=60n w=150.0n m=1 nf=1 - M3 (VOUT VIN1 net14 VDD) pch l=60n w=600n m=1 nf=1 - M2 (net14 VIN2 VDD VDD) pch l=60n w=600n m=1 nf=1 -ends NOR -// End of subcircuit definition. - -// Library name: EnergyHarvesting -// Cell name: INV1x -// View name: schematic -subckt INV1x GND VDD VIN VOUT - M0 (VOUT VIN GND GND) nch l=60n w=120.0n m=1 nf=1 - M1 (VOUT VIN VDD VDD) pch l=60n w=240.0n m=1 nf=1 -ends INV1x -// End of subcircuit definition. - -// Library name: DC_converter -// Cell name: INV_L2x -// View name: schematic -subckt INV_L2x GND VDD VIN VOUT - M0 (VOUT VIN GND GND) nch l=120.0n w=120.0n m=1 nf=1 - M1 (VOUT VIN VDD VDD) pch l=120.0n w=240.0n m=1 nf=1 -ends INV_L2x -// End of subcircuit definition. - -// Library name: DC_converter -// Cell name: NAND -// View name: schematic -subckt NAND GND VDD VIN1 VIN2 VOUT - M2 (VOUT VIN1 net16 GND) nch l=60n w=240.0n m=1 nf=1 - M3 (net16 VIN2 GND GND) nch l=60n w=240.0n m=1 nf=1 - M0 (VOUT VIN1 VDD VDD) pch l=60n w=240.0n m=1 nf=1 - M1 (VOUT VIN2 VDD VDD) pch l=60n w=240.0n m=1 nf=1 -ends NAND -// End of subcircuit definition. - -// Library name: EnergyHarvesting -// Cell name: NON_OVLP3 -// View name: schematic -I36 (GND VDD net06 CLK A) NOR -I1 (GND VDD net011 net010 B) NOR -I37 (GND VDD CLK net010) INV1x -I43 (GND VDD net010 net012) INV1x -I39 (GND VDD net09 net011) INV_L2x -I40 (GND VDD B net08) INV_L2x -I41 (GND VDD net08 net06) INV_L2x -I38 (GND VDD A net09) INV_L2x -I44 (GND VDD D net010 C) NAND -I45 (GND VDD C net012 D) NAND diff --git a/DesignDatabase/DesignExamplesLibrary/Analog/A4/README.md b/DesignDatabase/DesignExamplesLibrary/Analog/A4/README.md deleted file mode 100644 index b9a66878ac..0000000000 --- a/DesignDatabase/DesignExamplesLibrary/Analog/A4/README.md +++ /dev/null @@ -1,13 +0,0 @@ -Non-overlapping Clock Generator - -Files present: - -1. Netlist with sizing - -2. Schematic - -3. Layout - -To be added: - -- Testbench diff --git a/DesignDatabase/DesignExamplesLibrary/Analog/A4/Schematic/A4.PNG b/DesignDatabase/DesignExamplesLibrary/Analog/A4/Schematic/A4.PNG deleted file mode 100644 index b69df3ca74..0000000000 Binary files a/DesignDatabase/DesignExamplesLibrary/Analog/A4/Schematic/A4.PNG and /dev/null differ diff --git a/DesignDatabase/DesignExamplesLibrary/Analog/A5/Netlist/A5_netlist b/DesignDatabase/DesignExamplesLibrary/Analog/A5/Netlist/A5_netlist deleted file mode 100644 index 83226cae5d..0000000000 --- a/DesignDatabase/DesignExamplesLibrary/Analog/A5/Netlist/A5_netlist +++ /dev/null @@ -1,40 +0,0 @@ -** Generated for: hspiceD -** Generated on: Nov 19 16:37:16 2018 -** Design library name: DC_converter -** Design cell name: 2018_11_09_ASAP7_SCFilter -** Design view name: schematic -.GLOBAL vdd! - -.AC DEC 100 1.0 1e11 - -.TRAN 1e-9 50e-6 START=1e-9 - -.OP - -.PSS - -.TEMP 25.0 -.OPTION INGOLD=2 ARTIST=2 PSF=2 MEASOUT=1 PARHIER=LOCAL PROBE=0 MARCH=2 ACCURACY=1 POST - -** Library name: DC_converter -** Cell name: 2018_11_09_ASAP7_current_mirror_ota -** View name: schematic -.subckt DC_converter_2018_11_09_ASAP7_telescopic_ota_schematic vbiasnd vinn vinp voutn voutp D1 - -m9 voutn vbiasn net8 0 nmos_rvt w=270e-9 l=20e-9 nfin=25 -m8 voutp vbiasn net014 0 nmos_rvt w=270e-9 l=20e-9 nfin=25 -m5 D1 D1 0 0 nmos_rvt w=270e-9 l=20e-9 nfin=10 -m4 net10 vbiasnd 0 0 nmos_rvt w=270e-9 l=20e-9 nfin=50 -m3 net014 vinn net10 0 nmos_rvt w=270e-9 l=20e-9 nfin=70 -m0 net8 vinp net10 0 nmos_rvt w=270e-9 l=20e-9 nfin=70 -m7 voutp vbiasp net012 net012 pmos_rvt w=270e-9 l=20e-9 nfin=15 -m6 voutn vbiasp net06 net06 pmos_rvt w=270e-9 l=20e-9 nfin=15 -m2 net012 vbiasp1 vdd! vdd! pmos_rvt w=270e-9 l=20e-9 nfin=10 -m1 net06 vbiasp1 vdd! vdd! pmos_rvt w=270e-9 l=20e-9 nfin=10 -c2 voutp 0 60e-15 -c3 voutn 0 60e-15 -.ends DC_converter_2018_11_09_ASAP7_telescopic_ota_schematic -** End of subcircuit definition. - -.END - diff --git a/DesignDatabase/DesignExamplesLibrary/Analog/A5/README.md b/DesignDatabase/DesignExamplesLibrary/Analog/A5/README.md deleted file mode 100644 index 06b8b91c42..0000000000 --- a/DesignDatabase/DesignExamplesLibrary/Analog/A5/README.md +++ /dev/null @@ -1,14 +0,0 @@ -Fully differential telescopic OTA - -Files present: - -1. Netlist with sizing - -2. Schematic - -3. Testbench - - -To be added: - -- Layout \ No newline at end of file diff --git a/DesignDatabase/DesignExamplesLibrary/Analog/A5/Schematic/A5_image.PNG b/DesignDatabase/DesignExamplesLibrary/Analog/A5/Schematic/A5_image.PNG deleted file mode 100644 index 3e90342db3..0000000000 Binary files a/DesignDatabase/DesignExamplesLibrary/Analog/A5/Schematic/A5_image.PNG and /dev/null differ diff --git a/DesignDatabase/DesignExamplesLibrary/Analog/A5/Testbench/Constraints/A5_constraints b/DesignDatabase/DesignExamplesLibrary/Analog/A5/Testbench/Constraints/A5_constraints deleted file mode 100644 index 165766454c..0000000000 --- a/DesignDatabase/DesignExamplesLibrary/Analog/A5/Testbench/Constraints/A5_constraints +++ /dev/null @@ -1,2 +0,0 @@ -Symmetry in the differential pair and the cascode load blocks -Matching between transistors in the current mirror diff --git a/DesignDatabase/DesignExamplesLibrary/Analog/A5/Testbench/Netlist/A5_testbench b/DesignDatabase/DesignExamplesLibrary/Analog/A5/Testbench/Netlist/A5_testbench deleted file mode 100644 index 124aea52ba..0000000000 --- a/DesignDatabase/DesignExamplesLibrary/Analog/A5/Testbench/Netlist/A5_testbench +++ /dev/null @@ -1,106 +0,0 @@ -** Generated for: hspiceD -** Generated on: Nov 19 16:37:16 2018 -** Design library name: DC_converter -** Design cell name: 2018_11_09_ASAP7_SCFilter -** Design view name: schematic -.GLOBAL vdd! - -.TRAN 1e-9 50e-6 START=1e-9 - -.OP - -.TEMP 25.0 -.OPTION INGOLD=2 ARTIST=2 PSF=2 MEASOUT=1 PARHIER=LOCAL PROBE=0 MARCH=2 ACCURACY=1 POST - -** Library name: asap7ssc7p5t -** Cell name: INVx1_ASAP7_75t_R -** View name: schematic -.subckt INVx1_ASAP7_75t_R a y vdd vss -m0 y a vss vss nmos_rvt w=81e-9 l=20e-9 nfin=3 -m1 y a vdd vdd pmos_rvt w=81e-9 l=20e-9 nfin=3 -.ends INVx1_ASAP7_75t_R -** End of subcircuit definition. - -** Library name: asap7ssc7p5t -** Cell name: INVx1_ASAP7_75t_R_21 -** View name: schematic -.subckt INVx1_ASAP7_75t_R_21 a y vdd vss -m0 y a vss vss nmos_rvt w=81e-9 l=20e-9 nfin=21 -m1 y a vdd vdd pmos_rvt w=81e-9 l=20e-9 nfin=21 -.ends INVx1_ASAP7_75t_R_21 -** End of subcircuit definition. - -** Library name: DC_converter -** Cell name: 2018_12_03_ASAP7_transmission_gate -** View name: schematic -.subckt DC_converter_2018_12_03_ASAP7_transmission_gate a y vdd vss -m0 y vdd a 0 nmos_rvt w=81e-9 l=20e-9 nfin=3 -m1 y vss a a pmos_rvt w=81e-9 l=20e-9 nfin=3 -.ends DC_converter_2018_12_03_ASAP7_transmission_gate -** End of subcircuit definition. - -** Library name: DC_converter -** Cell name: 2018_11_09_ASAP7_NAND_gate -** View name: schematic -.subckt DC_converter_2018_11_09_ASAP7_NAND_gate_schematic a b out vdd vss -m2 out a net22 vss nmos_rvt w=54e-9 l=20e-9 nfin=2 -m3 net22 b vss vss nmos_rvt w=54e-9 l=20e-9 nfin=2 -m0 out a vdd vdd pmos_rvt w=27e-9 l=20e-9 nfin=1 -m1 out b vdd vdd pmos_rvt w=27e-9 l=20e-9 nfin=1 -.ends DC_converter_2018_11_09_ASAP7_NAND_gate_schematic -** End of subcircuit definition. - -** Library name: DC_converter -** Cell name: 2018_11_09_ASAP7_non_overlapping_clock_generator -** View name: schematic -.subckt DC_converter_2018_11_09_ASAP7_non_overlapping_clock_generator_schematic clk d_vdd d_gnd phi1 phi2 -xi6 clk net9 d_vdd d_gnd INVx1_ASAP7_75t_R -xi6_tg clk net9_tg d_dd d_gnd DC_converter_2018_12_03_ASAP7_transmission_gate -xi5 net12 phi2 d_vdd d_gnd INVx1_ASAP7_75t_R_21 -xi4 net17 net12 d_vdd d_gnd INVx1_ASAP7_75t_R -xi3 net8 phi1 d_vdd d_gnd INVx1_ASAP7_75t_R_21 -xi2 net15 net8 d_vdd d_gnd INVx1_ASAP7_75t_R -xi1 net16 net15 d_vdd d_gnd INVx1_ASAP7_75t_R -xi0 net18 net17 d_vdd d_gnd INVx1_ASAP7_75t_R -xi8 net9 net8 net18 d_vdd d_gnd DC_converter_2018_11_09_ASAP7_NAND_gate_schematic -xi7 net12 net9_tg net16 d_vdd d_gnd DC_converter_2018_11_09_ASAP7_NAND_gate_schematic -.ends DC_converter_2018_11_09_ASAP7_non_overlapping_clock_generator_schematic -** End of subcircuit definition. - - -** Library name: DC_converter -** Cell name: 2018_11_09_ASAP7_cmfb -** View name: schematic -.subckt DC_converter_2018_11_09_ASAP7_cmfb_schematic va vb vbias vcm vg phi1 phi2 -c3 net10 vg 20e-15 -c2 vg net8 20e-15 -m4 vbias phi2 vg 0 nmos_rvt w=27e-9 l=20e-9 nfin=50 -m3 vcm phi2 net10 0 nmos_rvt w=27e-9 l=20e-9 nfin=50 -m2 vb phi1 net10 0 nmos_rvt w=27e-9 l=20e-9 nfin=50 -m1 net8 phi2 vcm 0 nmos_rvt w=27e-9 l=20e-9 nfin=50 -m0 net8 phi1 va 0 nmos_rvt w=27e-9 l=20e-9 nfin=50 -.ends DC_converter_2018_11_09_ASAP7_cmfb_schematic -** End of subcircuit definition. - - -** Library name: DC_converter -** Cell name: 2018_11_09_ASAP7_Testbench -** View name: schematic -i5 vdd! id DC=40e-6 -//xi0 vg vbiasn vbiasp1 vbiasp2 net08 net09 voutn voutp id vdd vss DC_converter_2018_11_09_ASAP7_telescopic_ota_schematic -xi3 clk vdd! 0 phi1 phi2 DC_converter_2018_11_09_ASAP7_non_overlapping_clock_generator_schematic -v0 clk 0 PULSE 0 1 0 0 0 115e-9 250e-9 -v11 vdd! 0 DC=1 -v6 vcm 0 DC=550e-3 -v5 vbias_cm 0 DC=375e-3 -v2 net09 0 SIN 550e-3 1e-4 50e+3 0 0 0 -v1 net08 0 SIN 550e-3 1e-4 50e+3 0 0 180 -v3 vbiasn 0 DC=700e-3 -v4 vbiasp1 0 DC=300e-3 -v7 vbiasp2 0 DC=575e-3 -v8 vss 0 DC=0 -v9 vdd 0 DC=1 -xi13 voutn voutp id vcm vg phi1 phi2 DC_converter_2018_11_09_ASAP7_cmfb_schematic -.probe vdiff1=par('v(voutn)-v(voutp)') -.probe vdiff=par('v(net09)-v(net08)') -.END diff --git a/DesignDatabase/DesignExamplesLibrary/Analog/A5/Testbench/Performance Specifications/A5_performance_specification b/DesignDatabase/DesignExamplesLibrary/Analog/A5/Testbench/Performance Specifications/A5_performance_specification deleted file mode 100644 index a92b77c38d..0000000000 --- a/DesignDatabase/DesignExamplesLibrary/Analog/A5/Testbench/Performance Specifications/A5_performance_specification +++ /dev/null @@ -1,7 +0,0 @@ -The fully differential telescopic OTA can be evaluated using the following performance metrics. - -1. Gain - This amplifier has a gain of around 50 dB - -2. Unity gain frequency - It has a unity gain frequency of around 800 MHz - -3. Phase Margin diff --git a/DesignDatabase/DesignExamplesLibrary/Analog/README.md b/DesignDatabase/DesignExamplesLibrary/Analog/README.md deleted file mode 100644 index 437ad0a708..0000000000 --- a/DesignDatabase/DesignExamplesLibrary/Analog/README.md +++ /dev/null @@ -1,11 +0,0 @@ -This folder contains example ANALOG circuits (some of which have been taped out) that can be used as benchmarks. - -A1 : Fully differential current mirror OTA - -A2 : Comparator (not clocked) - -A3 : Comparator (clocked) - -A4 : Non-overlapping clock generator - -A5 : Fully differential telescopic OTA diff --git a/DesignDatabase/DesignExamplesLibrary/PowerManagement/PM1/Layout/DC1.PNG b/DesignDatabase/DesignExamplesLibrary/PowerManagement/PM1/Layout/DC1.PNG deleted file mode 100644 index 2359801014..0000000000 Binary files a/DesignDatabase/DesignExamplesLibrary/PowerManagement/PM1/Layout/DC1.PNG and /dev/null differ diff --git a/DesignDatabase/DesignExamplesLibrary/PowerManagement/PM1/Netlist/PM1 b/DesignDatabase/DesignExamplesLibrary/PowerManagement/PM1/Netlist/PM1 deleted file mode 100644 index 7d4ebf184c..0000000000 --- a/DesignDatabase/DesignExamplesLibrary/PowerManagement/PM1/Netlist/PM1 +++ /dev/null @@ -1,71 +0,0 @@ -// Generated for: spectre -// Generated on: Nov 8 14:28:22 2018 -// Design library name: EnergyHarvesting -// Design cell name: ChargePump -// Design view name: schematic -simulator lang=spectre -global 0 - -// Library name: DC_converter -// Cell name: NAND -// View name: schematic -subckt NAND GND VDD VIN1 VIN2 VOUT - M2 (VOUT VIN1 net16 GND) nch l=60n w=240.0n m=1 nf=1 - M3 (net16 VIN2 GND GND) nch l=60n w=240.0n m=1 nf=1 - M0 (VOUT VIN1 VDD VDD) pch l=60n w=240.0n m=1 nf=1 - M1 (VOUT VIN2 VDD VDD) pch l=60n w=240.0n m=1 nf=1 -ends NAND -// End of subcircuit definition. - -// Library name: EnergyHarvesting -// Cell name: INV1x -// View name: schematic -subckt INV1x GND VDD VIN VOUT - M0 (VOUT VIN GND GND) nch l=60n w=120.0n m=1 nf=1 - M1 (VOUT VIN VDD VDD) pch l=60n w=240.0n m=1 nf=1 -ends INV1x -// End of subcircuit definition. - -// Library name: DC_converter -// Cell name: NOR -// View name: schematic -subckt NOR GND VDD VIN1 VIN2 VOUT - M0 (VOUT VIN1 GND GND) nch l=60n w=150.0n m=1 nf=1 - M1 (VOUT VIN2 GND GND) nch l=60n w=150.0n m=1 nf=1 - M3 (VOUT VIN1 net14 VDD) pch l=60n w=600n m=1 nf=1 - M2 (net14 VIN2 VDD VDD) pch l=60n w=600n m=1 nf=1 -ends NOR -// End of subcircuit definition. - -// Library name: EnergyHarvesting -// Cell name: ChargePump -// View name: schematic -M17 (net027 VSTEPD net044 GND) nch l=60n w=120.0n m=1 nf=1 -M16 (net044 PDB GND GND) nch l=60n w=120.0n m=1 nf=1 -M13 (net036 net036 GND GND) nch l=200n w=200n m=1 nf=1 -M14 (VSTEPD PD net036 GND) nch l=60n w=200n m=1 nf=1 -M12 (net026 net036 GND GND) nch l=200n w=200n m=1 nf=1 -M8 (net22 PU GND GND) nch l=60n w=120.0n m=1 nf=1 -M7 (net058 VSTEPU net22 GND) nch l=60n w=120.0n m=1 nf=1 -M0 (VSTEPU PUB GND GND) nch l=60n w=200n m=1 nf=1 -M19 (net043 PDB VDD VDD) pch l=60n w=200n m=1 nf=1 -M18 (net027 VSTEPD net043 VDD) pch l=60n w=200n m=1 nf=1 -M15 (VSTEPD PD VDD VDD) pch l=60n w=200n m=1 nf=1 -M6 (net058 VSTEPU net21 VDD) pch l=60n w=200n m=1 -M5 (net21 PU VDD VDD) pch l=60n w=200n m=1 nf=1 -M3 (net27 net8 VDD VDD) pch l=200n w=400n m=1 nf=1 -M2 (net8 net8 VDD VDD) pch l=200n w=400n m=1 nf=1 -M1 (VSTEPU PUB net8 VDD) pch l=60n w=200n m=1 nf=1 -C3 (VDD VSTEPD) mimcap_sin lt=5u wt=5u mimflag=3 mf=1 mismatchflag=0 -C1 (GND VSTEPU) mimcap_sin lt=5u wt=5u mimflag=3 mf=1 mismatchflag=0 -C4 (GND net058) mimcap_sin lt=5u wt=5u mimflag=3 mf=1 mismatchflag=0 -C5 (VDD net027) mimcap_sin lt=5u wt=5u mimflag=3 mf=1 mismatchflag=0 -C0 (GND VCTL) mimcap_sin lt=40u wt=40u mimflag=3 mf=1 mismatchflag=0 -I0 (GND VDD net058 PU VPULSEU) NAND -I11 (GND VDD PD PDB) INV1x -I1 (GND VDD PU PUB) INV1x -M4 (VCTL VPULSEU net27 VDD) pch_hvt l=60n w=400n m=1 nf=1 -M9 (VCTL VPULSED net026 GND) nch_hvt l=60n w=200n m=1 nf=1 -I10 (GND VDD net027 PDB VPULSED) NOR - - diff --git a/DesignDatabase/DesignExamplesLibrary/PowerManagement/PM1/README.md b/DesignDatabase/DesignExamplesLibrary/PowerManagement/PM1/README.md deleted file mode 100644 index 1c1bdfd762..0000000000 --- a/DesignDatabase/DesignExamplesLibrary/PowerManagement/PM1/README.md +++ /dev/null @@ -1,13 +0,0 @@ -Charge pump circuit used in a LDO - -Files present: - -1. Netlist with sizing - -2. Schematic - -3. Layout - -To be added: - -- Testbench diff --git a/DesignDatabase/DesignExamplesLibrary/PowerManagement/PM1/Schematic/DC1.PNG b/DesignDatabase/DesignExamplesLibrary/PowerManagement/PM1/Schematic/DC1.PNG deleted file mode 100644 index aff9c6574f..0000000000 Binary files a/DesignDatabase/DesignExamplesLibrary/PowerManagement/PM1/Schematic/DC1.PNG and /dev/null differ diff --git a/DesignDatabase/DesignExamplesLibrary/PowerManagement/PM2/Layout/PM2_layout.PNG b/DesignDatabase/DesignExamplesLibrary/PowerManagement/PM2/Layout/PM2_layout.PNG deleted file mode 100644 index a40c1331d9..0000000000 Binary files a/DesignDatabase/DesignExamplesLibrary/PowerManagement/PM2/Layout/PM2_layout.PNG and /dev/null differ diff --git a/DesignDatabase/DesignExamplesLibrary/PowerManagement/PM2/Netlist/PM2_netlist.txt b/DesignDatabase/DesignExamplesLibrary/PowerManagement/PM2/Netlist/PM2_netlist.txt deleted file mode 100644 index 50682e6103..0000000000 --- a/DesignDatabase/DesignExamplesLibrary/PowerManagement/PM2/Netlist/PM2_netlist.txt +++ /dev/null @@ -1,21 +0,0 @@ -// Generated for: spectre -// Generated on: Nov 2 10:25:43 2018 -// Design library name: DC_converter -// Design cell name: 31Dec_2017_Driver_cap -// Design view name: schematic -simulator lang=spectre -global 0 - -// Library name: DC_converter -// Cell name: 31Dec_2017_Driver_cap -// View name: schematic -M13 (net32 lres_nmos gnd gnd) nch l=4.8u w=120.0n m=1 nf=1 -M12 (net017 sres_nmos gnd gnd) nch l=60n w=240.0n m=1 nf=1 -M11 (net32 sw net33 gnd) nch l=60n w=120.0n m=2 nf=1 -M9 (net33 ctrl gnd gnd) nch l=60n w=120.0n m=2 nf=1 -M14 (Vout tin net32 gnd) nch l=60n w=120.0n m=1 nf=1 -M17 (Vout lres_pmos Vdd Vdd) pch l=4.8u w=120.0n m=1 nf=1 -M15 (net31 sres_pmos Vdd Vdd) pch l=120.0n w=120.0n m=1 nf=1 -M4 (net32 sw_sres_nmos net017 gnd) nmos_rf lr=60n wr=600n nr=1 -M6 (Vout sw_sres_pmos net31 Vdd) pmos_rf lr=60n wr=600n nr=1 -M5 (Vout tin Vdd Vdd) pch_hvt l=60n w=120.0n m=5 nf=1 diff --git a/DesignDatabase/DesignExamplesLibrary/PowerManagement/PM2/README.md b/DesignDatabase/DesignExamplesLibrary/PowerManagement/PM2/README.md deleted file mode 100644 index 1c1bdfd762..0000000000 --- a/DesignDatabase/DesignExamplesLibrary/PowerManagement/PM2/README.md +++ /dev/null @@ -1,13 +0,0 @@ -Charge pump circuit used in a LDO - -Files present: - -1. Netlist with sizing - -2. Schematic - -3. Layout - -To be added: - -- Testbench diff --git a/DesignDatabase/DesignExamplesLibrary/PowerManagement/PM2/Schematic/PM2_image.PNG b/DesignDatabase/DesignExamplesLibrary/PowerManagement/PM2/Schematic/PM2_image.PNG deleted file mode 100644 index df5729c154..0000000000 Binary files a/DesignDatabase/DesignExamplesLibrary/PowerManagement/PM2/Schematic/PM2_image.PNG and /dev/null differ diff --git a/DesignDatabase/DesignExamplesLibrary/PowerManagement/README.md b/DesignDatabase/DesignExamplesLibrary/PowerManagement/README.md deleted file mode 100644 index 2bf5243084..0000000000 --- a/DesignDatabase/DesignExamplesLibrary/PowerManagement/README.md +++ /dev/null @@ -1,5 +0,0 @@ -This folder contains example Power Management circuits (some of which have been taped out) that can be used as benchmarks. - -PM1: Charge pump circuit - -PM2: Low voltage dropout regulator gate driver circuit \ No newline at end of file diff --git a/DesignDatabase/DesignExamplesLibrary/README.md b/DesignDatabase/DesignExamplesLibrary/README.md deleted file mode 100644 index baa9c01672..0000000000 --- a/DesignDatabase/DesignExamplesLibrary/README.md +++ /dev/null @@ -1,13 +0,0 @@ -This folder contains example circuits (some of which have been taped out) that can be used as benchmarks. - -The circuits are mainly classified into 4 catergories: - -1. Analog : For eg. amplifiers, comparators etc. - -2. Power Delivery : For eg. buck converter, LDO, power management and related circuits. - -3. Wireline : For eg. equalizers, etc. - -4. Wireless : For eg. Low noise amplifiers, mixers, etc. - - diff --git a/DesignDatabase/DesignExamplesLibrary/Wireless/README.md b/DesignDatabase/DesignExamplesLibrary/Wireless/README.md deleted file mode 100644 index c6bef02650..0000000000 --- a/DesignDatabase/DesignExamplesLibrary/Wireless/README.md +++ /dev/null @@ -1,9 +0,0 @@ -This folder contains example Power Management circuits (some of which have been taped out) that can be used as benchmarks. - -WLESS1: Low Noise Amplifier used in a RF Transceiver - -WLESS2: Mixer - -WLESS3: Bandpass Filter - -WLESS4: Oscillator diff --git a/DesignDatabase/DesignExamplesLibrary/Wireless/WLESS1/Layout/WLESS1_image.png b/DesignDatabase/DesignExamplesLibrary/Wireless/WLESS1/Layout/WLESS1_image.png deleted file mode 100644 index 745e353273..0000000000 Binary files a/DesignDatabase/DesignExamplesLibrary/Wireless/WLESS1/Layout/WLESS1_image.png and /dev/null differ diff --git a/DesignDatabase/DesignExamplesLibrary/Wireless/WLESS1/Netlist/WLESS1_netlist.txt b/DesignDatabase/DesignExamplesLibrary/Wireless/WLESS1/Netlist/WLESS1_netlist.txt deleted file mode 100644 index 0c3dcb6779..0000000000 --- a/DesignDatabase/DesignExamplesLibrary/Wireless/WLESS1/Netlist/WLESS1_netlist.txt +++ /dev/null @@ -1,33 +0,0 @@ - -// Library name: LNA_qmeng -// Cell name: LNA_QM_CORE -// View name: schematic -R5 (net011 VAUX VDD) rppolywo_rf l=6u w=500n m=1 -R4 (net063 SF_BIAS VDD) rppolywo_rf l=6u w=500n m=1 -R10 (net0252 VMAIN VDD) rppolywo_rf l=6u w=500n m=1 -R3 (net033 SF_BIAS VDD) rppolywo_rf l=6u w=500n m=1 -C12 (net0252 VSS VSS) mimcap_um_sin_rf lt=16.0u wt=16.0u m=1 -C9 (net0252 VSS VSS) mimcap_um_sin_rf lt=16.0u wt=16.0u m=1 -C6 (OUTN net063 VDD) mimcap_um_sin_rf lt=20u wt=20u m=1 -C43 (IN_INT net011 VDD) mimcap_um_sin_rf lt=16.0u wt=16.0u m=1 -C5 (OUTP net033 VDD) mimcap_um_sin_rf lt=20u wt=20u m=1 -C11 (net059 VDD VDD) mimcap_um_sin_rf lt=100.0000u wt=50u m=1 -C8 (net047 VDD VDD) mimcap_um_sin_rf lt=100.0000u wt=50u m=1 -M10 (VDD net033 VOUTP VOUTP) nmos_rf lr=120.0n wr=2u nr=32 -M12 (VDD net063 VOUTN VOUTN) nmos_rf lr=120.0n wr=2u nr=32 -M4 (OUTN net011 VSS VSS) nmos_rf lr=60n wr=1u nr=10 -M13 (OUTP net0252 IN_INT IN_INT) nmos_rf lr=60n wr=1u nr=10 -R38 (net058 net057 VDD) rppolyl_rf l=24.0u w=3u m=1 -R0 (VOUTP VSS VDD) rppolys_rf l=20u w=1u m=1 -R36 (net042 net056 VDD) rppolyl_rf l=24.0u w=3u m=1 -R35 (net056 net055 VDD) rppolyl_rf l=24.0u w=3u m=1 -R34 (net055 net054 VDD) rppolyl_rf l=24.0u w=3u m=1 -R33 (net054 net060 VDD) rppolyl_rf l=24.0u w=3u m=1 -R41 (OUTN net032 VDD) rppolyl_rf l=24.0u w=3u m=1 -R32 (net060 OUTP VDD) rppolyl_rf l=24.0u w=3u m=1 -R1 (VOUTN VSS VDD) rppolys_rf l=20u w=1u m=1 -R40 (net032 VDD VDD) rppolyl_rf l=24.0u w=3u m=1 -R37 (net057 net042 VDD) rppolyl_rf l=24.0u w=3u m=1 -R39 (VDD net058 VDD) rppolyl_rf l=24.0u w=3u m=1 -L8 (net047 OUTP VSS) spiral_std_mu_z w=3u rad=41.0u nr=3.75 -L9 (net059 OUTN VSS) spiral_std_mu_z w=3u rad=39.0u nr=3.75 diff --git a/DesignDatabase/DesignExamplesLibrary/Wireless/WLESS1/README.md b/DesignDatabase/DesignExamplesLibrary/Wireless/WLESS1/README.md deleted file mode 100644 index 2d9e0463b1..0000000000 --- a/DesignDatabase/DesignExamplesLibrary/Wireless/WLESS1/README.md +++ /dev/null @@ -1,13 +0,0 @@ -Low noise amplifier used in an RF Transceiver - -Files present: - -1. Netlist with sizing - -2. Schematic - -3. Layout - -To be added: - -- Testbench diff --git a/DesignDatabase/DesignExamplesLibrary/Wireless/WLESS1/Schematic/WLESS1_image.jpg b/DesignDatabase/DesignExamplesLibrary/Wireless/WLESS1/Schematic/WLESS1_image.jpg deleted file mode 100644 index 886187e411..0000000000 Binary files a/DesignDatabase/DesignExamplesLibrary/Wireless/WLESS1/Schematic/WLESS1_image.jpg and /dev/null differ diff --git a/DesignDatabase/DesignExamplesLibrary/Wireless/WLESS2/Layout/WLESS2_image.png b/DesignDatabase/DesignExamplesLibrary/Wireless/WLESS2/Layout/WLESS2_image.png deleted file mode 100644 index 39bd42bcd4..0000000000 Binary files a/DesignDatabase/DesignExamplesLibrary/Wireless/WLESS2/Layout/WLESS2_image.png and /dev/null differ diff --git a/DesignDatabase/DesignExamplesLibrary/Wireless/WLESS2/Netlist/WLESS2_netlist.txt b/DesignDatabase/DesignExamplesLibrary/Wireless/WLESS2/Netlist/WLESS2_netlist.txt deleted file mode 100644 index b78f6d5fd5..0000000000 --- a/DesignDatabase/DesignExamplesLibrary/Wireless/WLESS2/Netlist/WLESS2_netlist.txt +++ /dev/null @@ -1,111 +0,0 @@ - -// Library name: test_qmeng -// Cell name: MIXER_RFBIAS_RES -// View name: schematic -subckt MIXER_RFBIAS_RES M P tail_bias -R3 (P net9 ) rppolywo l=6u w=1u m=1 mf=(1) - -R0 (net9 tail_bias ) rppolywo l=6u w=1u m=1 mf=(1) - -R1 (tail_bias net05 ) rppolywo l=6u w=1u m=1 mf=(1) - -R2 (net05 M ) rppolywo l=6u w=1u m=1 mf=(1) - -ends MIXER_RFBIAS_RES -// End of subcircuit definition. - -// Library name: test_qmeng -// Cell name: MIXER_LOSWBIAS_RES -// View name: schematic -subckt MIXER_LOSWBIAS_RES MIXER_LOBIAS VDD VSS -R5 (VDD net050 ) rppolywo l=4u w=1u m=1 mf=(1) - -R4 (net031 net034 ) rppolywo l=4u w=1u m=1 mf=(1) - -R9 (net049 net031 ) rppolywo l=4u w=1u m=1 mf=(1) - -R6 (net050 net051 ) rppolywo l=4u w=1u m=1 mf=(1) - -R7 (net051 MIXER_LOBIAS ) rppolywo l=4u w=1u m=1 mf=(1) - -R8 (MIXER_LOBIAS net049 ) rppolywo l=4u w=1u m=1 mf=(1) - -R0 (net039 VSS ) rppolywo l=4u w=1u m=1 mf=(1) - -R1 (net033 net039 ) rppolywo l=4u w=1u m=1 mf=(1) - -R3 (net034 net036 ) rppolywo l=4u w=1u m=1 mf=(1) - -R2 (net036 net033 ) rppolywo l=4u w=1u m=1 mf=(1) - -ends MIXER_LOSWBIAS_RES -// End of subcircuit definition. - -// Library name: test_qmeng -// Cell name: MIXER_LOAD_RES -// View name: schematic -subckt MIXER_LOAD_RES A B -R4 (net03 B ) rppolys l=13.0u w=1u m=1 mf=(1) - -R0 (A net06 ) rppolys l=13.0u w=1u m=1 mf=(1) - -R1 (net06 net05 ) rppolys l=13.0u w=1u m=1 mf=(1) - -R3 (net05 net03 ) rppolys l=13.0u w=1u m=1 mf=(1) - -ends MIXER_LOAD_RES -// End of subcircuit definition. - -// Library name: PhasedArray_WB_V2 -// Cell name: Mixer -// View name: schematic -M35 (net051 tailm VSS VSS) nmos_rf lr=240.0n wr=3.6u nr=12 -M34 (net039 tailp VSS VSS) nmos_rf lr=240.0n wr=3.6u nr=12 -M44\<1\> (VSS MIXER_TAIL_IIN VSS VSS) nmos_rf lr=240.0n wr=3.6u nr=2 -M44\<2\> (VSS MIXER_TAIL_IIN VSS VSS) nmos_rf lr=240.0n wr=3.6u nr=2 -M44\<3\> (VSS MIXER_TAIL_IIN VSS VSS) nmos_rf lr=240.0n wr=3.6u nr=2 -M44\<4\> (VSS MIXER_TAIL_IIN VSS VSS) nmos_rf lr=240.0n wr=3.6u nr=2 -M44\<5\> (VSS MIXER_TAIL_IIN VSS VSS) nmos_rf lr=240.0n wr=3.6u nr=2 -M44\<6\> (VSS MIXER_TAIL_IIN VSS VSS) nmos_rf lr=240.0n wr=3.6u nr=2 -M44\<7\> (VSS MIXER_TAIL_IIN VSS VSS) nmos_rf lr=240.0n wr=3.6u nr=2 -M44\<8\> (VSS MIXER_TAIL_IIN VSS VSS) nmos_rf lr=240.0n wr=3.6u nr=2 -M43 (VSS VSS VSS VSS) nmos_rf lr=60n wr=2u nr=4 -M38 (MIXER_TAIL_IIN MIXER_TAIL_IIN VSS VSS) nmos_rf lr=240.0n wr=3.6u nr=2 -M39 (pbias MIXER_TAIL_IIN VSS VSS) nmos_rf lr=240.0n wr=3.6u nr=2 -M7 (IFM Oscp net039 net039) nmos_rf lr=60n wr=2u nr=4 -M13 (IFP Oscp net051 net051) nmos_rf lr=60n wr=2u nr=4 -M12 (IFM Oscm net051 net051) nmos_rf lr=60n wr=2u nr=4 -M11 (IFP Oscm net039 net039) nmos_rf lr=60n wr=2u nr=4 -M29 (VDD VDD VDD VDD) pmos_rf lr=240.0n wr=2.05u nr=8 -M16 (pbias pbias VDD VDD) pmos_rf lr=240.0n wr=2.05u nr=8 -M24 (IFP pbias VDD VDD) pmos_rf lr=240.0n wr=2.05u nr=32 -M23 (IFM pbias VDD VDD) pmos_rf lr=240.0n wr=2.05u nr=32 -I29 (tailm tailp MIXER_TAIL_IIN) MIXER_RFBIAS_RES -I12 (Oscp VDD VSS) MIXER_LOSWBIAS_RES -I21 (Oscm VDD VSS) MIXER_LOSWBIAS_RES -I18 (IFP VDD) MIXER_LOAD_RES -I17 (IFM VDD) MIXER_LOAD_RES -R1\<1\> (VSS net040\<0\> ) rppolys l=13.0u w=1u m=1 mf=(1) - -R1\<2\> (VSS net040\<1\> ) rppolys l=13.0u w=1u m=1 mf=(1) - -R1\<3\> (VSS net040\<2\> ) rppolys l=13.0u w=1u m=1 mf=(1) - -R1\<4\> (VSS net040\<3\> ) rppolys l=13.0u w=1u m=1 mf=(1) - -C15 (LOP Oscp VSS) mimcap_woum_sin_rf lt=32.0u wt=16.0u lay=7 m=1 -C6 (RFM tailm VSS) mimcap_woum_sin_rf lt=22.0u wt=22.0u lay=7 m=1 -C7 (RFP tailp VSS) mimcap_woum_sin_rf lt=22.0u wt=22.0u lay=7 m=1 -C14 (LOM Oscm VSS) mimcap_woum_sin_rf lt=32.0u wt=16.0u lay=7 m=1 -R2 (IFP OUTP ) rppolywo l=6u w=1u m=1 mf=(1) - -R5\<1\> (VSS net043\<0\> ) rppolywo l=6u w=1u m=1 mf=(1) - -R5\<2\> (VSS net043\<1\> ) rppolywo l=6u w=1u m=1 mf=(1) - -R5\<3\> (VSS net043\<2\> ) rppolywo l=6u w=1u m=1 mf=(1) - -R5\<4\> (VSS net043\<3\> ) rppolywo l=6u w=1u m=1 mf=(1) - -R0 (OUTM IFM ) rppolywo l=6u w=1u m=1 mf=(1) - diff --git a/DesignDatabase/DesignExamplesLibrary/Wireless/WLESS2/README.md b/DesignDatabase/DesignExamplesLibrary/Wireless/WLESS2/README.md deleted file mode 100644 index 6056c58dd8..0000000000 --- a/DesignDatabase/DesignExamplesLibrary/Wireless/WLESS2/README.md +++ /dev/null @@ -1,13 +0,0 @@ -Mixer ciruit - -Files present: - -1. Netlist with sizing - -2. Schematic - -3. Layout - -To be added: - -- Testbench diff --git a/DesignDatabase/DesignExamplesLibrary/Wireless/WLESS2/Schematic/WLESS2_image.jpg b/DesignDatabase/DesignExamplesLibrary/Wireless/WLESS2/Schematic/WLESS2_image.jpg deleted file mode 100644 index f3778ee240..0000000000 Binary files a/DesignDatabase/DesignExamplesLibrary/Wireless/WLESS2/Schematic/WLESS2_image.jpg and /dev/null differ diff --git a/DesignDatabase/DesignExamplesLibrary/Wireless/WLESS3/Layout/WLESS3_image.png b/DesignDatabase/DesignExamplesLibrary/Wireless/WLESS3/Layout/WLESS3_image.png deleted file mode 100644 index 0933cd6616..0000000000 Binary files a/DesignDatabase/DesignExamplesLibrary/Wireless/WLESS3/Layout/WLESS3_image.png and /dev/null differ diff --git a/DesignDatabase/DesignExamplesLibrary/Wireless/WLESS3/Netlist/WLESS3_netlist.txt b/DesignDatabase/DesignExamplesLibrary/Wireless/WLESS3/Netlist/WLESS3_netlist.txt deleted file mode 100644 index cb1b8e3b5b..0000000000 --- a/DesignDatabase/DesignExamplesLibrary/Wireless/WLESS3/Netlist/WLESS3_netlist.txt +++ /dev/null @@ -1,151 +0,0 @@ - -// Library name: PhasedArray_WB_V2 -// Cell name: res_24K -// View name: schematic -subckt res_24K t1 t2 vss - R4 (t2 net05 vss) rppolywo_rf l=8u w=500n m=1 - R2 (net06 net05 vss) rppolywo_rf l=8u w=500n m=1 - R1 (net06 net6 vss) rppolywo_rf l=8u w=500n m=1 - R0 (t1 net6 vss) rppolywo_rf l=8u w=500n m=1 -ends res_24K -// End of subcircuit definition. - -// Library name: PhasedArray_WB_V2 -// Cell name: capbank_gp_lowC_noLSB_BPF -// View name: schematic -subckt capbank_gp_lowC_noLSB_BPF B\<3\> B\<2\> B\<1\> B\<0\> LEFT RIGHT - VDD VSS - C5 (RIGHT net07 VSS) mimcap_woum_sin_rf lt=10u wt=10u lay=7 m=1 - - C4 (LEFT net010 VSS) mimcap_woum_sin_rf lt=10u wt=10u lay=7 m=1 - - C3 (RIGHT net3 VSS) mimcap_woum_sin_rf lt=5u wt=5u lay=7 m=2 - - C2 (LEFT net1 VSS) mimcap_woum_sin_rf lt=5u wt=5u lay=7 m=2 - - C1 (RIGHT net4 VSS) mimcap_woum_sin_rf lt=5u wt=5u lay=7 m=1 - - C0 (LEFT net2 VSS) mimcap_woum_sin_rf lt=5u wt=5u lay=7 m=1 - - M2 (net010 b2_buf net07 VSS) nmos_rf lr=60n wr=2u nr=20 - - M1 (net1 b1_buf net3 VSS) nmos_rf lr=60n wr=2u nr=20 - - M0 (net2 b0_buf net4 VSS) nmos_rf lr=60n wr=2u nr=20 - - M44 (net0155 net0120 VSS VSS) nch l=60n w=1u m=1 nf=1 - - - M40 (net0120 B\<3\> VSS VSS) nch l=60n w=1u m=1 nf=1 - - - M37 (net0159 net0104 VSS VSS) nch l=60n w=1u m=1 nf=1 - - - M36 (net0158 net0105 VSS VSS) nch l=60n w=1u m=1 nf=1 - - - M35 (net0157 net0106 VSS VSS) nch l=60n w=1u m=1 nf=1 - - - M31 (net0104 B\<2\> VSS VSS) nch l=60n w=1u m=1 nf=1 - - - M30 (net0105 B\<1\> VSS VSS) nch l=60n w=1u m=1 nf=1 - - - M29 (net0106 B\<0\> VSS VSS) nch l=60n w=1u m=1 nf=1 - - - M18 (b3_buf b3_inv VSS VSS) nch l=60n w=1u m=1 nf=1 - - - M16 (b3_inv B\<3\> VSS VSS) nch l=60n w=1u m=1 nf=1 - - - M15 (b2_inv B\<2\> VSS VSS) nch l=60n w=1u m=1 nf=1 - - - M13 (b2_buf b2_inv VSS VSS) nch l=60n w=1u m=1 nf=1 - - - M11 (b1_buf b1_inv VSS VSS) nch l=60n w=1u m=1 nf=1 - - - M9 (b1_inv B\<1\> VSS VSS) nch l=60n w=1u m=1 nf=1 - - - M7 (b0_buf b0_inv VSS VSS) nch l=60n w=1u m=1 nf=1 - - - M4 (b0_inv B\<0\> VSS VSS) nch l=60n w=1u m=1 nf=1 - - - M42 (net0155 net0120 VDD VDD) pch l=60n w=1u m=1 nf=1 - - - M38 (net0120 B\<3\> VDD VDD) pch l=60n w=1u m=1 nf=1 - - - M34 (net0159 net0104 VDD VDD) pch l=60n w=1u m=1 nf=1 - - - M33 (net0158 net0105 VDD VDD) pch l=60n w=1u m=1 nf=1 - - - M32 (net0157 net0106 VDD VDD) pch l=60n w=1u m=1 nf=1 - - - M28 (net0104 B\<2\> VDD VDD) pch l=60n w=1u m=1 nf=1 - - - M27 (net0105 B\<1\> VDD VDD) pch l=60n w=1u m=1 nf=1 - - - M26 (net0106 B\<0\> VDD VDD) pch l=60n w=1u m=1 nf=1 - - - M19 (b3_inv B\<3\> VDD VDD) pch l=60n w=1u m=1 nf=1 - - - M17 (b3_buf b3_inv VDD VDD) pch l=60n w=1u m=1 nf=1 - - - M14 (b2_buf b2_inv VDD VDD) pch l=60n w=1u m=1 nf=1 - - - M12 (b2_inv B\<2\> VDD VDD) pch l=60n w=1u m=1 nf=1 - - - M10 (b1_buf b1_inv VDD VDD) pch l=60n w=1u m=1 nf=1 - - - M8 (b1_inv B\<1\> VDD VDD) pch l=60n w=1u m=1 nf=1 - - - M6 (b0_buf b0_inv VDD VDD) pch l=60n w=1u m=1 nf=1 - - - M5 (b0_inv B\<0\> VDD VDD) pch l=60n w=1u m=1 nf=1 - - - I14 (b2_inv net010 VSS) res_24K - I15 (b2_inv net07 VSS) res_24K - I16 (b1_inv net3 VSS) res_24K - I17 (b1_inv net1 VSS) res_24K - I18 (b0_inv net2 VSS) res_24K - I19 (b0_inv net4 VSS) res_24K -ends capbank_gp_lowC_noLSB_BPF -// End of subcircuit definition. - -// Library name: PhasedArray_WB_V2 -// Cell name: BPF4 -// View name: schematic -M2 (OUTP INM VSS VSS) nmos_rf lr=120.0n wr=2.5u nr=32 - -M8 (OUTM INP VSS VSS) nmos_rf lr=120.0n wr=2.5u nr=32 - -I5 (DIG_BPF\<3\> DIG_BPF\<2\> DIG_BPF\<1\> DIG_BPF\<0\> OUTM OUTP VDDSW - VSS) capbank_gp_lowC_noLSB_BPF -L4 (OUTM OUTP VSS VDD_BPF0P5) spiral_sym_ct_mu_z w=7u nr=3 rad=24.0u lay=9 - spacing=3u gdis=10u m=1 diff --git a/DesignDatabase/DesignExamplesLibrary/Wireless/WLESS3/README.md b/DesignDatabase/DesignExamplesLibrary/Wireless/WLESS3/README.md deleted file mode 100644 index 5fb1116d52..0000000000 --- a/DesignDatabase/DesignExamplesLibrary/Wireless/WLESS3/README.md +++ /dev/null @@ -1,13 +0,0 @@ -Bandpass filter circuit - -Files present: - -1. Netlist with sizing - -2. Schematic - -3. Layout - -To be added: - -- Testbench diff --git a/DesignDatabase/DesignExamplesLibrary/Wireless/WLESS3/Schematic/WLESS3_image.jpg b/DesignDatabase/DesignExamplesLibrary/Wireless/WLESS3/Schematic/WLESS3_image.jpg deleted file mode 100644 index bd38a48606..0000000000 Binary files a/DesignDatabase/DesignExamplesLibrary/Wireless/WLESS3/Schematic/WLESS3_image.jpg and /dev/null differ diff --git a/DesignDatabase/DesignExamplesLibrary/Wireless/WLESS4/Layout/WLESS4_image.png b/DesignDatabase/DesignExamplesLibrary/Wireless/WLESS4/Layout/WLESS4_image.png deleted file mode 100644 index 7492c2970b..0000000000 Binary files a/DesignDatabase/DesignExamplesLibrary/Wireless/WLESS4/Layout/WLESS4_image.png and /dev/null differ diff --git a/DesignDatabase/DesignExamplesLibrary/Wireless/WLESS4/Netlist/WLESS4_netlist.txt b/DesignDatabase/DesignExamplesLibrary/Wireless/WLESS4/Netlist/WLESS4_netlist.txt deleted file mode 100644 index f924247386..0000000000 --- a/DesignDatabase/DesignExamplesLibrary/Wireless/WLESS4/Netlist/WLESS4_netlist.txt +++ /dev/null @@ -1,177 +0,0 @@ - -// Library name: PhasedArray_WB_V2 -// Cell name: res_24K -// View name: schematic -subckt res_24K t1 t2 vss - R4 (t2 net05 vss) rppolywo_rf l=8u w=500n m=1 - R2 (net06 net05 vss) rppolywo_rf l=8u w=500n m=1 - R1 (net06 net6 vss) rppolywo_rf l=8u w=500n m=1 - R0 (t1 net6 vss) rppolywo_rf l=8u w=500n m=1 -ends res_24K -// End of subcircuit definition. - -// Library name: PhasedArray_WB_V2 -// Cell name: capbank_gp_lowC_noLSB -// View name: schematic -subckt capbank_gp_lowC_noLSB B\<3\> B\<2\> B\<1\> B\<0\> LEFT RIGHT VDD VSS - C9 (LEFT net06 VSS) mimcap_woum_sin_rf lt=16.0u wt=16.0u lay=7 m=2 - - C8 (RIGHT net08 VSS) mimcap_woum_sin_rf lt=16.0u wt=16.0u lay=7 m=2 - - C5 (RIGHT net07 VSS) mimcap_woum_sin_rf lt=16.0u wt=16.0u lay=7 m=1 - - C4 (LEFT net010 VSS) mimcap_woum_sin_rf lt=16.0u wt=16.0u lay=7 m=1 - - C3 (RIGHT net3 VSS) mimcap_woum_sin_rf lt=8u wt=8u lay=7 m=2 - - C2 (LEFT net1 VSS) mimcap_woum_sin_rf lt=8u wt=8u lay=7 m=2 - - C1 (RIGHT net4 VSS) mimcap_woum_sin_rf lt=8u wt=8u lay=7 m=1 - - C0 (LEFT net2 VSS) mimcap_woum_sin_rf lt=8u wt=8u lay=7 m=1 - - M3 (net08 b3_buf net06 VSS) nmos_rf lr=60n wr=2u nr=20 sigma=1 m=10 - - M2 (net010 b2_buf net07 VSS) nmos_rf lr=60n wr=2u nr=20 sigma=1 m=5 - - M1 (net1 b1_buf net3 VSS) nmos_rf lr=60n wr=2u nr=20 sigma=1 m=2 - - M0 (net2 b0_buf net4 VSS) nmos_rf lr=60n wr=2u nr=20 sigma=1 m=1 - - M44 (net0155 net0120 VSS VSS) nch l=60n w=1u m=1 nf=1 - - - M40 (net0120 B\<3\> VSS VSS) nch l=60n w=1u m=1 nf=1 - - - M37 (net0159 net0104 VSS VSS) nch l=60n w=1u m=1 nf=1 - - - M36 (net0158 net0105 VSS VSS) nch l=60n w=1u m=1 nf=1 - - - M35 (net0157 net0106 VSS VSS) nch l=60n w=1u m=1 nf=1 - - - M31 (net0104 B\<2\> VSS VSS) nch l=60n w=1u m=1 nf=1 - - - M30 (net0105 B\<1\> VSS VSS) nch l=60n w=1u m=1 nf=1 - - - M29 (net0106 B\<0\> VSS VSS) nch l=60n w=1u m=1 nf=1 - - - M18 (b3_buf b3_inv VSS VSS) nch l=60n w=1u m=1 nf=1 - - - M16 (b3_inv B\<3\> VSS VSS) nch l=60n w=1u m=1 nf=1 - - - M15 (b2_inv B\<2\> VSS VSS) nch l=60n w=1u m=1 nf=1 - - - M13 (b2_buf b2_inv VSS VSS) nch l=60n w=1u m=1 nf=1 - - - M11 (b1_buf b1_inv VSS VSS) nch l=60n w=1u m=1 nf=1 - - - M9 (b1_inv B\<1\> VSS VSS) nch l=60n w=1u m=1 nf=1 - - - M7 (b0_buf b0_inv VSS VSS) nch l=60n w=1u m=1 nf=1 - - - M4 (b0_inv B\<0\> VSS VSS) nch l=60n w=1u m=1 nf=1 - - - M42 (net0155 net0120 VDD VDD) pch l=60n w=1u m=1 nf=1 - - - M38 (net0120 B\<3\> VDD VDD) pch l=60n w=1u m=1 nf=1 - - - M34 (net0159 net0104 VDD VDD) pch l=60n w=1u m=1 nf=1 - - - M33 (net0158 net0105 VDD VDD) pch l=60n w=1u m=1 nf=1 - - - M32 (net0157 net0106 VDD VDD) pch l=60n w=1u m=1 nf=1 - - - M28 (net0104 B\<2\> VDD VDD) pch l=60n w=1u m=1 nf=1 - - - M27 (net0105 B\<1\> VDD VDD) pch l=60n w=1u m=1 nf=1 - - - M26 (net0106 B\<0\> VDD VDD) pch l=60n w=1u m=1 nf=1 - - - M19 (b3_inv B\<3\> VDD VDD) pch l=60n w=1u m=1 nf=1 - - - M17 (b3_buf b3_inv VDD VDD) pch l=60n w=1u m=1 nf=1 - - - M14 (b2_buf b2_inv VDD VDD) pch l=60n w=1u m=1 nf=1 - - - M12 (b2_inv B\<2\> VDD VDD) pch l=60n w=1u m=1 nf=1 - - - M10 (b1_buf b1_inv VDD VDD) pch l=60n w=1u m=1 nf=1 - - - M8 (b1_inv B\<1\> VDD VDD) pch l=60n w=1u m=1 nf=1 - - - M6 (b0_buf b0_inv VDD VDD) pch l=60n w=1u m=1 nf=1 - - - M5 (b0_inv B\<0\> VDD VDD) pch l=60n w=1u m=1 nf=1 - - I12 (b3_inv net08 VSS) res_24K - I13 (b3_inv net06 VSS) res_24K - I14 (b2_inv net010 VSS) res_24K - I15 (b2_inv net07 VSS) res_24K - I16 (b1_inv net3 VSS) res_24K - I17 (b1_inv net1 VSS) res_24K - I18 (b0_inv net2 VSS) res_24K - I19 (b0_inv net4 VSS) res_24K -ends capbank_gp_lowC_noLSB -// End of subcircuit definition. - -// Library name: PhasedArray_WB_V2 -// Cell name: VCO -// View name: schematic -subckt VCO DIG_VCO\<3\> DIG_VCO\<2\> DIG_VCO\<1\> DIG_VCO\<0\> OUTM OUTP VDDSW VDD_VCO0P5 VSS - M0 (OUTP OUTM VSS VSS) nmos_rf lr=60n wr=1u nr=25 sigma=1 m=2 - M1 (OUTM OUTP VSS VSS) nmos_rf lr=60n wr=1u nr=25 sigma=1 m=2 - I10 (DIG_VCO\<3\> DIG_VCO\<2\> DIG_VCO\<1\> DIG_VCO\<0\> OUTM OUTP VDDSW VSS) capbank_gp_lowC_noLSB - L4 (OUTP OUTM VSS VDD_VCO0P5) spiral_sym_ct_mu_z w=9u nr=2 rad=27.0u - ends VCO -// End of subcircuit definition. - -// Library name: PhasedArray_WB_V2 -// Cell name: ILO_IN -// View name: schematic -subckt ILO_IN IN OUT VDDSW VSS - C2 (IN net7 VSS) mimcap_woum_sin_rf lt=20u wt=20u lay=7 m=1 - R3 (VSS net7 VSS) rppolywo_rf l=12.0u w=1u m=1 - R2 (net7 VDDSW VSS) rppolywo_rf l=12.0u w=1u m=1 - M3 (OUT net7 VSS VSS) nmos_rf lr=60n wr=1u nr=32 sigma=1 m=1 - -ends ILO_IN -// End of subcircuit definition. - -// Library name: PhasedArray_WB_V2 -// Cell name: ILO -// View name: schematic -I11 (DIG_VCO\<3\> DIG_VCO\<2\> DIG_VCO\<1\> DIG_VCO\<0\> OUTM OUTP VDDSW VDD_VCO0P5 VSS) VCO -L0 (OUTM net5) inductor l=pind_in_ILO -L1 (OUTP net6) inductor l=pind_in_ILO -I12 (INP net5 VDDSW VSS) ILO_IN -I13 (INM net6 VDDSW VSS) ILO_IN diff --git a/DesignDatabase/DesignExamplesLibrary/Wireless/WLESS4/README.md b/DesignDatabase/DesignExamplesLibrary/Wireless/WLESS4/README.md deleted file mode 100644 index 76efa28d98..0000000000 --- a/DesignDatabase/DesignExamplesLibrary/Wireless/WLESS4/README.md +++ /dev/null @@ -1,13 +0,0 @@ -Oscillator circuit - -Files present: - -1. Netlist with sizing - -2. Schematic - -3. Layout - -To be added: - -- Testbench diff --git a/DesignDatabase/DesignExamplesLibrary/Wireless/WLESS4/Schematic/WLESS4_image.jpg b/DesignDatabase/DesignExamplesLibrary/Wireless/WLESS4/Schematic/WLESS4_image.jpg deleted file mode 100644 index 46a9457699..0000000000 Binary files a/DesignDatabase/DesignExamplesLibrary/Wireless/WLESS4/Schematic/WLESS4_image.jpg and /dev/null differ diff --git a/DesignDatabase/DesignExamplesLibrary/Wireline/README.md b/DesignDatabase/DesignExamplesLibrary/Wireline/README.md deleted file mode 100644 index c68d637f3a..0000000000 --- a/DesignDatabase/DesignExamplesLibrary/Wireline/README.md +++ /dev/null @@ -1,7 +0,0 @@ -This folder contains example ANALOG circuits (some of which have been taped out) that can be used as benchmarks. - -W1 : Single to differential converter - -W2 : Adder - -W3 : Variable gain amplifier \ No newline at end of file diff --git a/DesignDatabase/DesignExamplesLibrary/Wireline/W1/Netlist/W1.sp b/DesignDatabase/DesignExamplesLibrary/Wireline/W1/Netlist/W1.sp deleted file mode 100644 index 9e005122bb..0000000000 --- a/DesignDatabase/DesignExamplesLibrary/Wireline/W1/Netlist/W1.sp +++ /dev/null @@ -1,35 +0,0 @@ -// Generated for: spectre -// Generated on: Jun 2 02:57:04 2019 -// Design library name: EQ_12nm -// Design cell name: SDC_top -// Design view name: schematic -simulator lang=spectre -global VDD! VSS! - -.param cload=10f ccoup=50f nfpf=30 ngf=1 rbias=20k rload=900 \ - vbias=600m vps=0.85 -// Library name: EQ_12nm -// Cell name: SDC_top -// View name: schematic - -.subckt nfet2x d g s b -.param p1=30 - MN0 d g n1 b nfet l=0.014u nfin=p1 - MN1 n1 g s b nfet l=0.014u nfin=p1 -.ends nfet2x - -.subckt sdc vb vin vout_sdc1 vout_sdc2 vps vgnd -.param fin_count=24 rb=20k rl=900 cc=48f cl=12f - - xI0 vd net1 vs vgnd nfet2x p1=fin_count - R2 vb net1 resistor r=rb - R1 vs vgnd resistor r=rl - R0 vps vd resistor r=rl - C2 vs vout_sdc2 capacitor c=cl - C1 vd vout_sdc1 capacitor c=cl - C0 vin net1 capacitor c=cc -.ends sdc - - - - diff --git a/DesignDatabase/DesignExamplesLibrary/Wireline/W1/README.md b/DesignDatabase/DesignExamplesLibrary/Wireline/W1/README.md deleted file mode 100644 index 19ccb5d992..0000000000 --- a/DesignDatabase/DesignExamplesLibrary/Wireline/W1/README.md +++ /dev/null @@ -1,13 +0,0 @@ -Single to differential converter - -Files present: - -1. Netlist with sizing - -To be added - -- Schematic snapshot - -- Layout snapshot - -- Testbench diff --git a/DesignDatabase/DesignExamplesLibrary/Wireline/W2/Netlist/adder.sp b/DesignDatabase/DesignExamplesLibrary/Wireline/W2/Netlist/adder.sp deleted file mode 100644 index a252590782..0000000000 --- a/DesignDatabase/DesignExamplesLibrary/Wireline/W2/Netlist/adder.sp +++ /dev/null @@ -1,39 +0,0 @@ -// Generated for: spectre -// Generated on: Jun 4 11:15:16 2019 -// Design library name: EQ_12nm -// Design cell name: Adder_top -// Design view name: schematic -simulator lang=spectre -global VDD! VSS! - -.param cload_adder=10f vps=0.85 ccoup_adder=50f nfpf_adder=50 \ - ngf_adder=1 rbias_adder=20K rload_adder=500 vbias_nfet_adder=600m \ - vbias_pfet_adder=450m - -// Library name: EQ_12nm -// Cell name: Adder_top -// View name: schematic - -.subckt nfet2x d g s b -.param p1=2 - MN0 d g n1 b nfet l=0.014u nfin=p1 - MN1 n1 g s b nfet l=0.014u nfin=p1 -.ends nfet2x - -.subckt pfet2x d g s b -.param p1=2 - MP0 d g n1 b pfet l=0.014u nfin=p1 - MP1 n1 g s b pfet l=0.014u nfin=p1 -.ends pfet2x - -.subckt adder n1 n2 vin vout vps vgnd -.param cc=48f nfpf=48 rb=20K rl=500 - - xI0 vout vbn1 vgnd vgnd nfet2x p1=nfpf - xI1 vout vbp1 vps vps pfet2x p1=nfpf - R0 vbn1 n1 resistor r=rb - C0 vin vbn1 capacitor c=cc - R1 vbp1 n2 resistor r=rb - C1 vin vbp1 capacitor c=cc - R2 vps vout resistor r=rl -.ends adder diff --git a/DesignDatabase/DesignExamplesLibrary/Wireline/W2/README.md b/DesignDatabase/DesignExamplesLibrary/Wireline/W2/README.md deleted file mode 100644 index 4bd982127f..0000000000 --- a/DesignDatabase/DesignExamplesLibrary/Wireline/W2/README.md +++ /dev/null @@ -1,13 +0,0 @@ -Adder - -Files present: - -1. Netlist with sizing - -To be added - -- Schematic snapshot - -- Layout snapshot - -- Testbench diff --git a/DesignDatabase/DesignExamplesLibrary/Wireline/W3/Netlist/W3.sp b/DesignDatabase/DesignExamplesLibrary/Wireline/W3/Netlist/W3.sp deleted file mode 100644 index 57bbe443c6..0000000000 --- a/DesignDatabase/DesignExamplesLibrary/Wireline/W3/Netlist/W3.sp +++ /dev/null @@ -1,41 +0,0 @@ -// Generated for: spectre -// Generated on: Jun 3 13:08:52 2019 -// Design library name: EQ_12nm -// Design cell name: VGA_top -// Design view name: schematic -simulator lang=spectre -global VDD! VSS! - - -// Library name: EQ_12nm -// Cell name: VGA_top -// View name: schematic -.subckt nfet2x d g s b -.param p1=2 - MN0 d g n1 b nfet l=0.014u nfin=p1 - MN1 n1 g s b nfet l=0.014u nfin=p1 -.ends nfet2x - -// current mirror -.subckt vga vmirror_vga s0 s1 s2 vin1 vin2 vout_vga1 vout_vga2 vps vgnd -.param nfpf_sw=72 nfpf_sw_2=144 nfpf_sw_4=288 cload=12f nfpf_cm=72 nfpf_cm_2=144 nfpf_cm_4=288 nfpf_dp=48 nfpf_dp_2=96 nfpf_dp_4=192 rl=400 - - xI03 vmirror_vga vmirror_vga vgnd vgnd nfet2x p1=nfpf_cm - xI02 net3 vmirror_vga vgnd vgnd nfet2x p1=nfpf_cm - xI01 vout_vga2 vin2 net3 vgnd nfet2x p1=nfpf_dp - xI00 vout_vga1 vin1 net3 vgnd nfet2x p1=nfpf_dp - Msw0 net5 s0 net5p vgnd nfet l=0.014u nfin=nfpf_sw - xI12 net5p vmirror_vga vgnd vgnd nfet2x p1=nfpf_cm - xI11 vout_vga2 vin2 net5 vgnd nfet2x p1=nfpf_dp - xI10 vout_vga1 vin1 net5 vgnd nfet2x p1=nfpf_dp - Msw1 net4 s1 net4p vgnd nfet l=0.014u nfin=nfpf_sw_2 - xI22 net4p vmirror_vga vgnd vgnd nfet2x p1=nfpf_cm_2 - xI21 vout_vga2 vin2 net4 vgnd nfet2x p1=nfpf_dp_2 - xI20 vout_vga1 vin1 net4 vgnd nfet2x p1=nfpf_dp_2 - Msw2 net6 s2 net6p vgnd nfet l=0.014u nfin=nfpf_sw_4 - xI32 net6p vmirror_vga vgnd vgnd nfet2x p1=nfpf_cm_4 - xI31 vout_vga2 vin2 net6 vgnd nfet2x p1=nfpf_dp_4 - xI30 vout_vga1 vin1 net6 vgnd nfet2x p1=nfpf_dp_4 - R5 vps vout_vga2 resistor r=rl - R6 vps vout_vga1 resistor r=rl -.ends vga \ No newline at end of file diff --git a/DesignDatabase/DesignExamplesLibrary/Wireline/W3/README.md b/DesignDatabase/DesignExamplesLibrary/Wireline/W3/README.md deleted file mode 100644 index ec820a1dd2..0000000000 --- a/DesignDatabase/DesignExamplesLibrary/Wireline/W3/README.md +++ /dev/null @@ -1,13 +0,0 @@ -Variable gain amplifier - -Files present: - -1. Netlist with sizing - -To be added - -- Schematic snapshot - -- Layout snapshot - -- Testbench diff --git a/DesignDatabase/README.md b/DesignDatabase/README.md deleted file mode 100644 index 11f78fd14e..0000000000 --- a/DesignDatabase/README.md +++ /dev/null @@ -1,3 +0,0 @@ -Design Examples Library : Contains example circuits with netlist, schematic, layout, etc. that can be used for benchmarking. - -Testcases : Contains the different circuits that have been tried on the tool. \ No newline at end of file diff --git a/DesignDatabase/Testcases/Equalizer/README.md b/DesignDatabase/Testcases/Equalizer/README.md deleted file mode 100644 index 5bba03a08e..0000000000 --- a/DesignDatabase/Testcases/Equalizer/README.md +++ /dev/null @@ -1,5 +0,0 @@ -This folder contains the Equalizer circuits that have been tried on the tool - -equalizer_50nm_2018_10_29 : Contains the Equalizer circuit netlists designed using FreePDK 50nm - -equalizer_7nm_2018_11_20 : Contains the Equalizer circuit netlists designed using ASAP 7nm \ No newline at end of file diff --git a/DesignDatabase/Testcases/Equalizer/equalizer_50nm_2018_10_29/Circuit Description/Equalizer_sample_sizing.pptx b/DesignDatabase/Testcases/Equalizer/equalizer_50nm_2018_10_29/Circuit Description/Equalizer_sample_sizing.pptx deleted file mode 100644 index 6cbec5a322..0000000000 Binary files a/DesignDatabase/Testcases/Equalizer/equalizer_50nm_2018_10_29/Circuit Description/Equalizer_sample_sizing.pptx and /dev/null differ diff --git a/DesignDatabase/Testcases/Equalizer/equalizer_50nm_2018_10_29/Netlist/adder.sp b/DesignDatabase/Testcases/Equalizer/equalizer_50nm_2018_10_29/Netlist/adder.sp deleted file mode 100644 index 55c52b6c8e..0000000000 --- a/DesignDatabase/Testcases/Equalizer/equalizer_50nm_2018_10_29/Netlist/adder.sp +++ /dev/null @@ -1,76 +0,0 @@ -// Generated for: spectre -// Generated on: Oct 22 18:15:01 2018 -// Design library name: ALIGN_project -// Design cell name: adder -simulator lang=spectre -global 0 vdd! - -parameters rload=4.5k wn=590n wp=150n vbn=0.5 -include "./model_file_50nm.inc" - -// only one side of adder is shown here in the netlist -//unit 1 -M0 (vout vbn1 0 0) N_50n w=wn l=100n -M1 (vout vbp1 vdd! vdd!) P_50n w=wp l=100n - -// two biasing circuits for each adder to bias PMOS and NMOS separately -Vb01 (n1 0) vsource dc=vbn mag=0 type=dc -R0 (vbn1 n1) resistor r = 66.3e6 -C0 (vin1 vbn1) capacitor c = 2.4e-12 - -Vb02 (n2 0) vsource dc=vbn mag=0 type=dc -R1 (vbp1 n2) resistor r = 66.3e6 -C1 (vin1 vbp1) capacitor c = 2.4e-12 - -//unit 2 -M2 (vout vbn2 0 0) N_50n w=wn l=100n -M3 (vout vbp2 vdd! vdd!) P_50n w=wp l=100n - -Vb03 (n3 0) vsource dc=vbn mag=0 type=dc -R2 (vbn2 n3) resistor r = 66.3e6 -C2 (vin2 vbn2) capacitor c = 2.4e-12 - -Vb04 (n4 0) vsource dc=vbn mag=0 type=dc -R3 (vbp2 n4) resistor r = 66.3e6 -C3 (vin2 vbp2) capacitor c = 2.4e-12 - -//unit 3 -M4 (vout vbn3 0 0) N_50n w=wn l=100n -M5 (vout vbp3 vdd! vdd!) P_50n w=wp l=100n - -Vb05 (n5 0) vsource dc=vbn mag=0 type=dc -R4 (vbn3 n5) resistor r = 66.3e6 -C4 (vin3 vbn3) capacitor c = 2.4e-12 - -Vb06 (n6 0) vsource dc=vbn mag=0 type=dc -R5 (vbp3 n6) resistor r = 66.3e6 -C5 (vin3 vbp3) capacitor c = 2.4e-12 - - -V1 (vdd! 0) vsource dc=1 type=dc - -Vac1 (vin1 0) vsource dc=0 mag=100m type=sine sinedc=0 ampl=100m freq=1G -Vac2 (vin2 0) vsource dc=0 mag=100m*0 type=sine sinedc=0 ampl=100m*0 freq=1G -Vac3 (vin3 0) vsource dc=0 mag=100m*0 type=sine sinedc=0 ampl=100m*0 freq=1G - -Rload (vdd! vout) resistor r=rload -Cload (vout 0) capacitor c=1.44f -simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=27 \ - tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \ - digits=5 cols=80 pivrel=1e-3 sensfile="../psf/sens.output" \ - checklimitdest=psf -tran1 tran stop=5n errpreset=moderate write="spectre.ic" \ - writefinal="spectre.fc" annotate=status maxiters=5 -//finalTimeOP info what=oppoint where=rawfile -dcOp dc write="spectre.dc" maxiters=150 maxsteps=10000 annotate=status -//dcOpInfo info what=oppoint where=rawfile -dc dc param=vbn start=0 stop=1 step=100 oppoint=rawfile maxiters=150 \ -// maxsteps=10000 annotate=status -ac1 ac start=1 stop=20G dec=10 annotate=status -modelParameter info what=models where=rawfile -element info what=inst where=rawfile -outputParameter info what=output where=rawfile -designParamVals info what=parameters where=rawfile -primitives info what=primitives where=rawfile -subckts info what=subckts where=rawfile -saveOptions options save=allpub diff --git a/DesignDatabase/Testcases/Equalizer/equalizer_50nm_2018_10_29/Netlist/ctle.sp b/DesignDatabase/Testcases/Equalizer/equalizer_50nm_2018_10_29/Netlist/ctle.sp deleted file mode 100644 index 054e5e2b2d..0000000000 --- a/DesignDatabase/Testcases/Equalizer/equalizer_50nm_2018_10_29/Netlist/ctle.sp +++ /dev/null @@ -1,49 +0,0 @@ -// Generated for: spectre -// Generated on: Oct 21 12:33:02 2018 -// Design library name: ALIGN_project -// Design cell name: ctle -simulator lang=spectre -global 0 vdd! - -parameters ibias=71u/2 rload=5.8k wcm=912n wdp=880n cs=1.4p rs=1k -include "./model_file_50nm.inc" - -//current mirror -M4 (vmirror vmirror 0 0) N_50n w=wcm l=50n -M3 (net3 vmirror 0 0) N_50n w=wcm l=50n -M2 (net5 vmirror 0 0) N_50n w=wcm l=50n - -//differential pair -M1 (vout1 vin2 net3 0) N_50n w=wdp l=50n -M0 (vout2 vin1 net5 0) N_50n w=wdp l=50n -//variable resistance -Rs (net3 net5) resistor r=rs - -// load resistance and capacitance -R1 (vdd! vout1) resistor r=rload -R0 (vdd! vout2) resistor r=rload -C0 (vout2 0) capacitor c=1.44f -C1 (vout1 0) capacitor c=1.44f - -//variable capacitance -Cs (net3 net5) capacitor c=cs -I5 (vdd! vmirror) isource dc=ibias type=dc -V0 (vdd! 0) vsource dc=1 mag=0 type=dc -V1 (vcm 0) vsource dc=500m mag=0 type=dc -V2 (vdm 0) vsource dc=0 mag=250m type=sine sinedc=0 ampl=10m freq=100K -E2 (vin2 vcm vdm 0) vcvs gain=-.5 type=vcvs -E0 (vin1 vcm vdm 0) vcvs gain=.5 type=vcvs -simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=27 \ - tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \ - digits=5 cols=80 pivrel=1e-3 sensfile="../psf/sens.output" \ - checklimitdest=psf -dcOp dc write="spectre.dc" maxiters=150 maxsteps=10000 annotate=status -dcOpInfo info what=oppoint where=rawfile -ac_analysis ac start=1k stop=10000G dec=10 annotate=status -modelParameter info what=models where=rawfile -element info what=inst where=rawfile -outputParameter info what=output where=rawfile -designParamVals info what=parameters where=rawfile -primitives info what=primitives where=rawfile -subckts info what=subckts where=rawfile -saveOptions options save=allpub diff --git a/DesignDatabase/Testcases/Equalizer/equalizer_50nm_2018_10_29/Netlist/sdc.sp b/DesignDatabase/Testcases/Equalizer/equalizer_50nm_2018_10_29/Netlist/sdc.sp deleted file mode 100644 index 3fb1dbf54c..0000000000 --- a/DesignDatabase/Testcases/Equalizer/equalizer_50nm_2018_10_29/Netlist/sdc.sp +++ /dev/null @@ -1,41 +0,0 @@ -// Generated for: spectre -// Generated on: Oct 28 04:00:58 2018 -// Design library name: ALIGN_project -// Design cell name: sdc -simulator lang=spectre -global 0 vdd! -parameters rbias=60k vbias=1 W=50u cload=10f -include "./model_file_50nm.inc" - -M0 (vd vbias vs 0) N_50n w=W l=100n -R6 (vbias net010) resistor r=rbias -R2 (vchannel 0) resistor r=50 -R1 (vdd! vd) resistor r=55 -R0 (vs 0) resistor r=55 -V2 (net010 0) vsource dc=vbias mag=0 type=dc -V1 (vdd! 0) vsource dc=1 type=dc -C0 (vchannel vbias) capacitor c=2.4p -CL1 (vd 0) capacitor c=cload -CL2 (vs 0) capacitor c=cload - -V3 (vchannel 0) vsource dc=0 mag=250m type=sine sinedc=0 ampl=300m freq=1G -simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=27 \ - tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \ - digits=5 cols=80 pivrel=1e-3 sensfile="../psf/sens.output" \ - checklimitdest=psf -dcOp dc write="spectre.dc" maxiters=150 maxsteps=10000 annotate=status -dcOpInfo info what=oppoint where=rawfile -dc dc param=W start=10u stop=500u step=1000 oppoint=rawfile maxiters=150 \ - maxsteps=10000 annotate=status -ac ac start=1K stop=100G dec=10 annotate=status -tran tran stop=5n write="spectre.ic" writefinal="spectre.fc" \ - annotate=status maxiters=5 -finalTimeOP info what=oppoint where=rawfile -modelParameter info what=models where=rawfile -element info what=inst where=rawfile -outputParameter info what=output where=rawfile -designParamVals info what=parameters where=rawfile -primitives info what=primitives where=rawfile -subckts info what=subckts where=rawfile -save M0:d -saveOptions options save=allpub diff --git a/DesignDatabase/Testcases/Equalizer/equalizer_50nm_2018_10_29/Netlist/vga.sp b/DesignDatabase/Testcases/Equalizer/equalizer_50nm_2018_10_29/Netlist/vga.sp deleted file mode 100644 index e0a5f5ec3a..0000000000 --- a/DesignDatabase/Testcases/Equalizer/equalizer_50nm_2018_10_29/Netlist/vga.sp +++ /dev/null @@ -1,72 +0,0 @@ -// Generated for: spectre -// Generated on: Oct 21 15:41:50 2018 -// Design library name: ALIGN_project -// Design cell name: vga - -simulator lang=spectre -global 0 vdd! -parameters ibias=56.6u rload=1.2k wcm=727n wdp=703n vps=1 b0=1 b1=0 b2=0 -include "./model_file_50nm.inc" - -//current mirror -MCM00 (vmirror vmirror 0 0) N_50n w=wcm l=50n -MCM01 (net3 vmirror 0 0) N_50n w=wcm l=50n - -//differential pair -MDP01 (vout1 vin2 net3 0) N_50n w=wdp l=50n -MDP00 (vout2 vin1 net3 0) N_50n w=wdp l=50n - - -R1 (vdd! vout1) resistor r=rload -R0 (vdd! vout2) resistor r=rload -Cload1 (vout1 0) capacitor c=2.7f -Cload2 (vout2 0) capacitor c=2.7f -//switch -MSW01 (net4 b_0 net4p 0) N_50n w=wcm l=50n -//current mirror -MCM02 (net4p vmirror 0 0) N_50n w=wcm l=50n -//differential pair -MDP03 (vout1 vin2 net4 0) N_50n w=wdp l=50n -MDP02 (vout2 vin1 net4 0) N_50n w=wdp l=50n - -//switch -MSW02 (net5 b_1 net5p 0) N_50n w=wcm l=50n -//current mirror -MCM03 (net5p vmirror 0 0) N_50n w=wcm*2 l=50n -//differential pair -MDP05 (vout1 vin2 net5 0) N_50n w=wdp*2 l=50n -MDP04 (vout2 vin1 net5 0) N_50n w=wdp*2 l=50n - -//switch -MSW03 (net6 b_2 net6p 0) N_50n w=wcm l=50n -//current mirror -MCM04 (net6p vmirror 0 0) N_50n w=wcm*4 l=50n -//differential pair -MDP07 (vout1 vin2 net6 0) N_50n w=wdp*4 l=50n -MDP06 (vout2 vin1 net6 0) N_50n w=wdp*4 l=50n - -V3 (b_0 0) vsource dc=b0 mag=0 type=dc -V4 (b_1 0) vsource dc=b1 mag=0 type=dc -V5 (b_2 0) vsource dc=b2 mag=0 type=dc - - -I5 (vdd! vmirror) isource dc=ibias type=dc -V0 (vdd! 0) vsource dc=vps mag=0 type=dc -V1 (vcm 0) vsource dc=550m mag=0 type=dc -V2 (vdm 0) vsource dc=0 mag=1m type=sine sinedc=0 ampl=10m freq=100K -E2 (vin2 vcm vdm 0) vcvs gain=-.5 type=vcvs -E0 (vin1 vcm vdm 0) vcvs gain=.5 type=vcvs -simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=27 \ - tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \ - digits=5 cols=80 pivrel=1e-3 sensfile="../psf/sens.output" \ - checklimitdest=psf -dcOp dc write="spectre.dc" maxiters=150 maxsteps=10000 annotate=status -dcOpInfo info what=oppoint where=rawfile -ac1 ac start=1k stop=100G dec=10 annotate=status -modelParameter info what=models where=rawfile -element info what=inst where=rawfile -outputParameter info what=output where=rawfile -designParamVals info what=parameters where=rawfile -primitives info what=primitives where=rawfile -subckts info what=subckts where=rawfile -saveOptions options save=allpub diff --git a/DesignDatabase/Testcases/Equalizer/equalizer_7nm_2018_11_20/Circuit Description/Equalizer_sample_sizing_finFET.pptx b/DesignDatabase/Testcases/Equalizer/equalizer_7nm_2018_11_20/Circuit Description/Equalizer_sample_sizing_finFET.pptx deleted file mode 100644 index 667fbaa07b..0000000000 Binary files a/DesignDatabase/Testcases/Equalizer/equalizer_7nm_2018_11_20/Circuit Description/Equalizer_sample_sizing_finFET.pptx and /dev/null differ diff --git a/DesignDatabase/Testcases/Equalizer/equalizer_7nm_2018_11_20/Netlist/adder.sp b/DesignDatabase/Testcases/Equalizer/equalizer_7nm_2018_11_20/Netlist/adder.sp deleted file mode 100644 index 7012d618ad..0000000000 --- a/DesignDatabase/Testcases/Equalizer/equalizer_7nm_2018_11_20/Netlist/adder.sp +++ /dev/null @@ -1,80 +0,0 @@ -// Generated for: spectre -// Design library name: ALIGN_project -// Design cell name: adder -simulator lang=spectre -global 0 vdd! - -parameters rload=550 vbn=0.4 vbp = 0.25 no_of_fin=20 vdd = 0.7 Lmin=7n cload=10f rcoup=2400 ccoup = 50e-15 -include "./save_param.scs" -include "./7nm_TT_160803.pm" - - -// only one side of adder is shown here in the netlist -//unit 1 -M0 (vout vbn1 0 0) nmos_lvt w=no_of_fin*27n l=2*Lmin nfin=no_of_fin -M1 (vout vbp1 vdd! vdd!) pmos_lvt w=no_of_fin*27n l=2*Lmin nfin=no_of_fin - -// two biasing circuits for each adder to bias PMOS and NMOS separately -Vb01 (n1 0) vsource dc=vbn mag=0 type=dc -R0 (vbn1 n1) resistor r = rcoup -C0 (vin1 vbn1) capacitor c = ccoup - -Vb02 (n2 0) vsource dc=vbp mag=0 type=dc -R1 (vbp1 n2) resistor r = rcoup -C1 (vin1 vbp1) capacitor c = ccoup - -//unit 2 -M2 (vout vbn2 0 0) nmos_lvt w=no_of_fin*27n l=2*Lmin nfin=no_of_fin -M3 (vout vbp2 vdd! vdd!) pmos_lvt w=no_of_fin*27n l=2*Lmin nfin=no_of_fin - -Vb03 (n3 0) vsource dc=vbn mag=0 type=dc -R2 (vbn2 n3) resistor r = rcoup -C2 (vin2 vbn2) capacitor c = ccoup - -Vb04 (n4 0) vsource dc=vbp mag=0 type=dc -R3 (vbp2 n4) resistor r = rcoup -C3 (vin2 vbp2) capacitor c = ccoup - -//unit 3 -M4 (vout vbn3 0 0) nmos_lvt w=no_of_fin*27n l=2*Lmin nfin=no_of_fin -M5 (vout vbp3 vdd! vdd!) pmos_lvt w=no_of_fin*27n l=2*Lmin nfin=no_of_fin - -Vb05 (n5 0) vsource dc=vbn mag=0 type=dc -R4 (vbn3 n5) resistor r = rcoup -C4 (vin3 vbn3) capacitor c = ccoup - -Vb06 (n6 0) vsource dc=vbp mag=0 type=dc -R5 (vbp3 n6) resistor r = rcoup -C5 (vin3 vbp3) capacitor c = ccoup - - -V1 (vdd! 0) vsource dc=vdd type=dc - -Vac1 (vin1 0) vsource dc=0 mag=125m type=sine sinedc=0 ampl=125m freq=1G -Vac2 (vin2 0) vsource dc=0 mag=125m*0 type=sine sinedc=0 ampl=125m freq=500MHz -Vac3 (vin3 0) vsource dc=0 mag=125m*0 type=sine sinedc=0 ampl=125m freq=2GHz - -Rload (vdd! vout) resistor r=rload -Cload (vout 0) capacitor c=cload -simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=27 \ - tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \ - digits=5 cols=80 pivrel=1e-3 sensfile="../psf/sens.output" \ - checklimitdest=psf -tran1 tran stop=5n errpreset=moderate write="spectre.ic" \ - writefinal="spectre.fc" annotate=status maxiters=5 -//finalTimeOP info what=oppoint where=rawfile -dcOp dc write="spectre.dc" maxiters=150 maxsteps=10000 annotate=status -//dcOpInfo info what=oppoint where=rawfile -//dc dc param=vbn start=0 stop=1 step=100 oppoint=rawfile maxiters=150 \ -// maxsteps=10000 annotate=status -dc dc param=no_of_fin start=1 stop=100 step=1 oppoint=rawfile maxiters=150 \ - maxsteps=10000 annotate=status - -ac1 ac start=100K stop=1000G dec=10 annotate=status -modelParameter info what=models where=rawfile -element info what=inst where=rawfile -outputParameter info what=output where=rawfile -designParamVals info what=parameters where=rawfile -primitives info what=primitives where=rawfile -subckts info what=subckts where=rawfile -saveOptions options save=allpub diff --git a/DesignDatabase/Testcases/Equalizer/equalizer_7nm_2018_11_20/Netlist/ctle.sp b/DesignDatabase/Testcases/Equalizer/equalizer_7nm_2018_11_20/Netlist/ctle.sp deleted file mode 100644 index 677e391d3d..0000000000 --- a/DesignDatabase/Testcases/Equalizer/equalizer_7nm_2018_11_20/Netlist/ctle.sp +++ /dev/null @@ -1,55 +0,0 @@ -// Generated for: spectre -// Design library name: ALIGN_project -// Design cell name: ctle -simulator lang=spectre -global 0 vdd! - -// here, Rs and Cs are variable resistance and capacitance respectively. -//parameters Lmin=7n W=27n nfin_ncm=16*6 nfin_dp=24*6 cs=600f rs=1200 cload=10f ibias=296u*6 vbias=550m rload=0.2k vdd=0.7 -parameters Lmin=7n W=27n nfin_ncm=120 nfin_dp=144 cs=140f rs=2000 cload=10f ibias=296u*6 vbias=550m rload=0.2k vdd=0.7 - -simulator lang=spice -.include "7nm_TT_160803.pm" -.include "save.scs" -simulator lang=spectre - -//current mirror -M4 (vmirror vmirror 0 0) nmos_lvt w=W*nfin_ncm l=2*Lmin nfin= nfin_ncm -M3 (net3 vmirror 0 0) nmos_lvt w=W*nfin_ncm l=2*Lmin nfin= nfin_ncm -M2 (net5 vmirror 0 0) nmos_lvt w=W*nfin_ncm l=2*Lmin nfin= nfin_ncm - -//differential pair -M1 (vout1 vin2 net3 0) nmos_lvt w=W*nfin_dp l=2*Lmin nfin= nfin_dp -M0 (vout2 vin1 net5 0) nmos_lvt w=W*nfin_dp l=2*Lmin nfin= nfin_dp - -//variable resistance -Rs (net3 net5) resistor r=rs - -// load resistance and capacitance -R1 (vdd! vout1) resistor r=rload -R0 (vdd! vout2) resistor r=rload -C0 (vout2 0) capacitor c=cload -C1 (vout1 0) capacitor c=cload -Cs (net3 net5) capacitor c=cs - -I5 (vdd! vmirror) isource dc=ibias type=dc -V0 (vdd! 0) vsource dc=vdd mag=0 type=dc -V1 (vcm 0) vsource dc=vbias mag=0 type=dc -V2 (vdm 0) vsource dc=0 mag=125m type=sine sinedc=0 ampl=125m freq=1G -E2 (vin2 vcm vdm 0) vcvs gain=-.5 type=vcvs -E0 (vin1 vcm vdm 0) vcvs gain=.5 type=vcvs -simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=27 \ - tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \ - digits=5 cols=80 pivrel=1e-3 sensfile="../psf/sens.output" \ - checklimitdest=psf -dcOp dc write="spectre.dc" maxiters=150 maxsteps=10000 annotate=status -dcOpInfo info what=oppoint where=rawfile -ac_analysis ac start=100k stop=1000G dec=10 annotate=status -tran_analysis tran start=0 stop=5n step=0.0001*5n -modelParameter info what=models where=rawfile -element info what=inst where=rawfile -outputParameter info what=output where=rawfile -designParamVals info what=parameters where=rawfile -primitives info what=primitives where=rawfile -subckts info what=subckts where=rawfile -saveOptions options save=allpub diff --git a/DesignDatabase/Testcases/Equalizer/equalizer_7nm_2018_11_20/Netlist/sdc.sp b/DesignDatabase/Testcases/Equalizer/equalizer_7nm_2018_11_20/Netlist/sdc.sp deleted file mode 100644 index aca4e427e2..0000000000 --- a/DesignDatabase/Testcases/Equalizer/equalizer_7nm_2018_11_20/Netlist/sdc.sp +++ /dev/null @@ -1,45 +0,0 @@ -// Generated for: spectre -// Design library name: ALIGN_project -// Design cell name: sdc -simulator lang=spectre -global 0 vdd! - -parameters rbias=10k vbias=460m cload=10f no_of_fin=512 vdd=0.7 Lmin=7n -include "/home/grads/dharx027/All_research/model_files/nmosedu_50nm/model_file_50nm.inc" -include "./save_param.scs" -include "./7nm_TT_160803.pm" - -// Library name: ALIGN_project_test -// Cell name: sdc -// View name: schematic -M0 (vd vbias vs 0) nmos_lvt w=no_of_fin*27n l=2*Lmin nfin=no_of_fin -R3 (vbias net010) resistor r=rbias -R2 (vchannel 0) resistor r=50 -R1 (vdd! vd) resistor r=55 -R0 (vs 0) resistor r=55 -V2 (net010 0) vsource dc=vbias mag=0 type=dc // bias voltage -V1 (vdd! 0) vsource dc=vdd type=dc // power supply -C0 (vchannel vbias) capacitor c=60e-15 -CL1 (vd 0) capacitor c=cload -CL2 (vs 0) capacitor c=cload - -V3 (vchannel 0) vsource dc=0 mag=200m type=sine sinedc=0 ampl=200m freq=1G -simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=27 \ - tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \ - digits=5 cols=80 pivrel=1e-3 sensfile="../psf/sens.output" \ - checklimitdest=psf -dcOp dc write="spectre.dc" maxiters=150 maxsteps=10000 annotate=status -dcOpInfo info what=oppoint where=rawfile -dc dc param=no_of_fin start=3 stop=300 step=2 oppoint=rawfile maxiters=150 \ - maxsteps=10000 annotate=status -ac1 ac start=1K stop=10000G dec=10 annotate=status -tran tran stop=5n write="spectre.ic" writefinal="spectre.fc" \ - annotate=status maxiters=5 -finalTimeOP info what=oppoint where=rawfile -modelParameter info what=models where=rawfile -element info what=inst where=rawfile -outputParameter info what=output where=rawfile -designParamVals info what=parameters where=rawfile -primitives info what=primitives where=rawfile -subckts info what=subckts where=rawfile -saveOptions options save=allpub diff --git a/DesignDatabase/Testcases/Equalizer/equalizer_7nm_2018_11_20/Netlist/vga.sp b/DesignDatabase/Testcases/Equalizer/equalizer_7nm_2018_11_20/Netlist/vga.sp deleted file mode 100644 index 0eb66e9393..0000000000 --- a/DesignDatabase/Testcases/Equalizer/equalizer_7nm_2018_11_20/Netlist/vga.sp +++ /dev/null @@ -1,74 +0,0 @@ -// Generated for: spectre -// Design library name: ALIGN_project -// Design cell name: vga -simulator lang=spectre -global 0 vdd! -parameters ibias=296u vbias= 0.45 rload=400 nfin_ncm=30 nfin_dp=24 vdd=0.7 b0=vdd b1=vdd b2=vdd Lmin=7n cload=10f W=27n - -simulator lang=spice -.include "7nm_TT_160803.pm" -.include "save.scs" -simulator lang=spectre - -// current mirror -M03 (vmirror vmirror 0 0) nmos_lvt w=W*nfin_ncm l=2*Lmin nfin= nfin_ncm -M02 (net3 vmirror 0 0) nmos_lvt w=W*nfin_ncm l=2*Lmin nfin= nfin_ncm -// differential pair -M01 (vout1 vin2 net3 0) nmos_lvt w=W*nfin_dp l=2*Lmin nfin= nfin_dp -M00 (vout2 vin1 net3 0) nmos_lvt w=W*nfin_dp l=2*Lmin nfin= nfin_dp - -R1 (vdd! vout1) resistor r=rload -R0 (vdd! vout2) resistor r=rload -Cload1 (vout1 0) capacitor c=cload -Cload2 (vout2 0) capacitor c=cload - -// switch -M13 (net4 b_0 net4p 0) nmos_lvt w=W*nfin_ncm l=2*Lmin nfin= nfin_ncm -// current mirror -M12 (net4p vmirror 0 0) nmos_lvt w=W*nfin_ncm l=2*Lmin nfin= nfin_ncm -// differential pair -M11 (vout1 vin2 net4 0) nmos_lvt w=W*nfin_dp l=2*Lmin nfin= nfin_dp -M10 (vout2 vin1 net4 0) nmos_lvt w=W*nfin_dp l=2*Lmin nfin= nfin_dp - -// switch -M23 (net5 b_1 net5p 0) nmos_lvt w=W*nfin_ncm l=2*Lmin nfin= nfin_ncm -// current mirror -M22 (net5p vmirror 0 0) nmos_lvt w=W*nfin_ncm*2 l=2*Lmin nfin= nfin_ncm*2 -// differential pair -M21 (vout1 vin2 net5 0) nmos_lvt w=W*nfin_dp*2 l=2*Lmin nfin= nfin_dp*2 -M20 (vout2 vin1 net5 0) nmos_lvt w=W*nfin_dp*2 l=2*Lmin nfin= nfin_dp*2 - -// switch -M33 (net6 b_2 net6p 0)nmos_lvt w=W*nfin_ncm l=2*Lmin nfin= nfin_ncm -// current mirror -M32 (net6p vmirror 0 0) nmos_lvt w=W*nfin_ncm*4 l=2*Lmin nfin= nfin_ncm*4 -// differential pair -M31 (vout1 vin2 net6 0) nmos_lvt w=W*nfin_dp*4 l=2*Lmin nfin= nfin_dp*4 -M30 (vout2 vin1 net6 0) nmos_lvt w=W*nfin_dp*4 l=2*Lmin nfin= nfin_dp*4 - -V3 (b_0 0) vsource dc=b0 mag=0 type=dc -V4 (b_1 0) vsource dc=b1 mag=0 type=dc -V5 (b_2 0) vsource dc=b2 mag=0 type=dc - - -I5 (vdd! vmirror) isource dc=ibias type=dc -V0 (vdd! 0) vsource dc=vdd mag=0 type=dc -V1 (vcm 0) vsource dc=vbias mag=0 type=dc -V2 (vdm 0) vsource dc=0 mag=1m type=sine sinedc=0 ampl=250m freq=1G -E2 (vin2 vcm vdm 0) vcvs gain=-.5 type=vcvs -E0 (vin1 vcm vdm 0) vcvs gain=.5 type=vcvs -simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=27 \ - tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \ - digits=5 cols=80 pivrel=1e-3 sensfile="../psf/sens.output" \ - checklimitdest=psf -dcOp dc write="spectre.dc" maxiters=150 maxsteps=10000 annotate=status -dcOpInfo info what=oppoint where=rawfile -ac1 ac start=1k stop=100G dec=10 annotate=status -tran1 tran start=0 stop=5n step = 0.0001*5n -modelParameter info what=models where=rawfile -element info what=inst where=rawfile -outputParameter info what=output where=rawfile -designParamVals info what=parameters where=rawfile -primitives info what=primitives where=rawfile -subckts info what=subckts where=rawfile -saveOptions options save=allpub diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/README.md b/DesignDatabase/Testcases/OTA/OTA_topologies/README.md deleted file mode 100644 index c87e7146bd..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/README.md +++ /dev/null @@ -1,19 +0,0 @@ -# OTA topologies - -There are several operational transconductance amplifier (OTA) topologies that can potentially be used in analog design. -This repository aims to act as a one-top-shop by compiling various commonly used OTA topolgies compiled from different literature sources into one location. -The OTA topologies in this directory are specified in SPICE netlist format. - - -## Directory structure - -*OTA topologies* repository has the following directory structure: - -- *full_OTA* directory contains OTA circuits with proper biasing (1390 variations) - - *full_differential_OTA*: contains fully differential OTA topologies - - *single_ended_OTA*: contains single ended OTA topologies -- *generator* directory contains different subcircuits of OTA used to generate the circuits in full_OTA - - *bias*: contains different low frequency analog bias topologies which provide voltage reference to local generators (15 circuits) - - *local_generation*: contains various local current/voltage biasing used for OTA circuits - - *OTA*: contains OTA signal path topologies - - *merge_OTA.py*: utilizes *bias, local_generation, OTA* subcircuits to generate full OTA circuits with proper biasing diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_nmos_cr13_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_nmos_cr13_1.sp deleted file mode 100644 index ac60058cea..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_nmos_cr13_1.sp +++ /dev/null @@ -1,61 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential -* View Name: schematic -* Netlisted on: Sep 11 21:04:32 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos Biasp Vbiasn -*.PININFO Biasp:I Vbiasn:O -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential -xiLG_nmos Biasp LG_Vbiasn LG_nmos -xibCR13_2 Biasn Biasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_nmos_cr13_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_nmos_cr13_2.sp deleted file mode 100644 index ac60058cea..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_nmos_cr13_2.sp +++ /dev/null @@ -1,61 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential -* View Name: schematic -* Netlisted on: Sep 11 21:04:32 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos Biasp Vbiasn -*.PININFO Biasp:I Vbiasn:O -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential -xiLG_nmos Biasp LG_Vbiasn LG_nmos -xibCR13_2 Biasn Biasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_nmos_cr14_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_nmos_cr14_2.sp deleted file mode 100644 index 0f98e39d6e..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_nmos_cr14_2.sp +++ /dev/null @@ -1,62 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential -* View Name: schematic -* Netlisted on: Sep 11 21:04:32 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos Biasp Vbiasn -*.PININFO Biasp:I Vbiasn:O -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR14_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net010 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 Vbiasn net010 res=rK -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential -xiLG_nmos Biasp LG_Vbiasn LG_nmos -xibCR14_2 Biasn Biasp CR14_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_nmos_cr15_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_nmos_cr15_1.sp deleted file mode 100644 index 8282d596cf..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_nmos_cr15_1.sp +++ /dev/null @@ -1,59 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential -* View Name: schematic -* Netlisted on: Sep 11 21:04:32 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos Biasp Vbiasn -*.PININFO Biasp:I Vbiasn:O -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR15_1 Vbiasp -*.PININFO Vbiasp:O -RR1 Vbiasp gnd! res=rK -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential -xiLG_nmos Biasp LG_Vbiasn LG_nmos -xibCR15_1 Biasp CR15_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_nmos_cr16_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_nmos_cr16_1.sp deleted file mode 100644 index aac72a4c50..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_nmos_cr16_1.sp +++ /dev/null @@ -1,60 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential -* View Name: schematic -* Netlisted on: Sep 11 21:04:32 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos Biasp Vbiasn -*.PININFO Biasp:I Vbiasn:O -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR16_1 Vbiasp -*.PININFO Vbiasp:O -RR0 vdd! net6 res=rK -RR1 Vbiasp gnd! res=rK -MM2 Vbiasp Vbiasp net6 vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential -xiLG_nmos Biasp LG_Vbiasn LG_nmos -xibCR16_1 Biasp CR16_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_nmos_cr2_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_nmos_cr2_2.sp deleted file mode 100644 index 19037329d5..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_nmos_cr2_2.sp +++ /dev/null @@ -1,62 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential -* View Name: schematic -* Netlisted on: Sep 11 21:04:32 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos Biasp Vbiasn -*.PININFO Biasp:I Vbiasn:O -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR2_2_wilson Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -RR0 Vbiasn gnd! res=rK -MM2 Vbiasp net12 Vbiasn gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential -xiLG_nmos Biasp LG_Vbiasn LG_nmos -xibCR2_2_wilson Biasn Biasp CR2_2_wilson -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_nmos_cr3_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_nmos_cr3_2.sp deleted file mode 100644 index 9bdaecbb88..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_nmos_cr3_2.sp +++ /dev/null @@ -1,62 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential -* View Name: schematic -* Netlisted on: Sep 11 21:04:32 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos Biasp Vbiasn -*.PININFO Biasp:I Vbiasn:O -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR3_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 net15 gnd! res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential -xiLG_nmos Biasp LG_Vbiasn LG_nmos -xibCR3_2 Biasn Biasp CR3_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_nmos_cr4_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_nmos_cr4_2.sp deleted file mode 100644 index c5da39d1d2..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_nmos_cr4_2.sp +++ /dev/null @@ -1,67 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential -* View Name: schematic -* Netlisted on: Sep 11 21:04:32 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos Biasp Vbiasn -*.PININFO Biasp:I Vbiasn:O -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR4_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM11 net023 net024 Vbiasn gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM8 net025 net010 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM9 net024 net024 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM7 net010 net010 net025 gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net025 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 net024 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net010 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential -xiLG_nmos Biasp LG_Vbiasn LG_nmos -xibCR4_2 Biasn Biasp CR4_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_nmos_cr5_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_nmos_cr5_2.sp deleted file mode 100644 index 669f8d8159..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_nmos_cr5_2.sp +++ /dev/null @@ -1,64 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential -* View Name: schematic -* Netlisted on: Sep 11 21:04:32 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos Biasp Vbiasn -*.PININFO Biasp:I Vbiasn:O -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR5_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM5 net014 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net014 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential -xiLG_nmos Biasp LG_Vbiasn LG_nmos -xibCR5_2 Biasn Biasp CR5_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_nmos_cr6_3.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_nmos_cr6_3.sp deleted file mode 100644 index 4b3448216f..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_nmos_cr6_3.sp +++ /dev/null @@ -1,64 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential -* View Name: schematic -* Netlisted on: Sep 11 21:04:32 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos Biasp Vbiasn -*.PININFO Biasp:I Vbiasn:O -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR6_3 Vbiasn1 Vbiasn2 Vbiasp -*.PININFO Vbiasn1:O Vbiasn2:O Vbiasp:O -MM2 Vbiasp Vbiasn2 Vbiasn1 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn2 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 Vbiasn1 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM5 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn2 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential -xiLG_nmos Biasp LG_Vbiasn LG_nmos -xibCR6_3 Biasn1 Biasn2 Biasp CR6_3 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_nmos_l1_cr11_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_nmos_l1_cr11_1.sp deleted file mode 100644 index 91523d802c..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_nmos_l1_cr11_1.sp +++ /dev/null @@ -1,64 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential -* View Name: schematic -* Netlisted on: Sep 11 21:04:32 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR11_1 Vbiasn -*.PININFO Vbiasn:O -RRF vdd! Vbiasn res=rK -MM1 net9 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net9 net9 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn net9 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR11_1 Biasn CR11_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_nmos_l1_cr12_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_nmos_l1_cr12_1.sp deleted file mode 100644 index 369de7aa80..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_nmos_l1_cr12_1.sp +++ /dev/null @@ -1,64 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential -* View Name: schematic -* Netlisted on: Sep 11 21:04:32 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR12_1 Vbiasn -*.PININFO Vbiasn:O -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 net10 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn net10 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RRF vdd! Vbiasn res=rK -RR0 vdd! net10 res=rK -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR12_1 Biasn CR12_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_nmos_l1_cr13_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_nmos_l1_cr13_1.sp deleted file mode 100644 index ddde4de2ce..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_nmos_l1_cr13_1.sp +++ /dev/null @@ -1,63 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential -* View Name: schematic -* Netlisted on: Sep 11 21:04:32 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR13_2 Biasn Vbiasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_nmos_l1_cr13_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_nmos_l1_cr13_2.sp deleted file mode 100644 index ddde4de2ce..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_nmos_l1_cr13_2.sp +++ /dev/null @@ -1,63 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential -* View Name: schematic -* Netlisted on: Sep 11 21:04:32 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR13_2 Biasn Vbiasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_nmos_l1_cr14_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_nmos_l1_cr14_2.sp deleted file mode 100644 index ee76555c86..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_nmos_l1_cr14_2.sp +++ /dev/null @@ -1,64 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential -* View Name: schematic -* Netlisted on: Sep 11 21:04:32 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR14_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net010 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 Vbiasn net010 res=rK -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR14_2 Biasn Vbiasp CR14_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_nmos_l1_cr1_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_nmos_l1_cr1_1.sp deleted file mode 100644 index ef70e95293..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_nmos_l1_cr1_1.sp +++ /dev/null @@ -1,61 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential -* View Name: schematic -* Netlisted on: Sep 11 21:04:32 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR1_1 Vbiasn -*.PININFO Vbiasn:O -RRF vdd! Vbiasn res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR1_1 Biasn CR1_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_nmos_l1_cr2_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_nmos_l1_cr2_2.sp deleted file mode 100644 index 076a496065..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_nmos_l1_cr2_2.sp +++ /dev/null @@ -1,64 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential -* View Name: schematic -* Netlisted on: Sep 11 21:04:32 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR2_2_wilson Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -RR0 Vbiasn gnd! res=rK -MM2 Vbiasp net12 Vbiasn gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR2_2_wilson Biasn Vbiasp CR2_2_wilson -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_nmos_l1_cr3_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_nmos_l1_cr3_2.sp deleted file mode 100644 index 7d124c9650..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_nmos_l1_cr3_2.sp +++ /dev/null @@ -1,64 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential -* View Name: schematic -* Netlisted on: Sep 11 21:04:32 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR3_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 net15 gnd! res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR3_2 Biasn Vbiasp CR3_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_nmos_l1_cr4_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_nmos_l1_cr4_2.sp deleted file mode 100644 index 885fabf507..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_nmos_l1_cr4_2.sp +++ /dev/null @@ -1,69 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential -* View Name: schematic -* Netlisted on: Sep 11 21:04:32 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR4_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM11 net023 net024 Vbiasn gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM8 net025 net010 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM9 net024 net024 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM7 net010 net010 net025 gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net025 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 net024 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net010 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR4_2 Biasn Vbiasp CR4_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_nmos_l1_cr5_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_nmos_l1_cr5_2.sp deleted file mode 100644 index 11d2ee122b..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_nmos_l1_cr5_2.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential -* View Name: schematic -* Netlisted on: Sep 11 21:04:32 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR5_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM5 net014 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net014 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR5_2 Biasn Vbiasp CR5_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_nmos_l1_cr7_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_nmos_l1_cr7_1.sp deleted file mode 100644 index 1afcb41ea0..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_nmos_l1_cr7_1.sp +++ /dev/null @@ -1,64 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential -* View Name: schematic -* Netlisted on: Sep 11 21:04:32 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR7_1 Vbiasn -*.PININFO Vbiasn:O -RR1 Vbiasn net7 res=rK -RR0 vdd! net7 res=rK -RRF vdd! Vbiasn res=rK -MM1 net7 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR7_1 Biasn CR7_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_nmos_l1_cr9_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_nmos_l1_cr9_1.sp deleted file mode 100644 index b028c6d22a..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_nmos_l1_cr9_1.sp +++ /dev/null @@ -1,62 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential -* View Name: schematic -* Netlisted on: Sep 11 21:04:32 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR9_1 Vbiasn -*.PININFO Vbiasn:O -RR1 net05 gnd! res=rK -RRF vdd! Vbiasn res=rK -MM0 Vbiasn Vbiasn net05 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR9_1 Biasn CR9_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_npmos_cr11_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_npmos_cr11_1.sp deleted file mode 100644 index 87344eddaf..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_npmos_cr11_1.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential -* View Name: schematic -* Netlisted on: Sep 11 21:04:32 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR11_1 Vbiasn -*.PININFO Vbiasn:O -RRF vdd! Vbiasn res=rK -MM1 net9 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net9 net9 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn net9 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR11_1 Biasn CR11_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_npmos_cr12_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_npmos_cr12_1.sp deleted file mode 100644 index b31a69a3f2..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_npmos_cr12_1.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential -* View Name: schematic -* Netlisted on: Sep 11 21:04:32 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR12_1 Vbiasn -*.PININFO Vbiasn:O -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 net10 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn net10 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RRF vdd! Vbiasn res=rK -RR0 vdd! net10 res=rK -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR12_1 Biasn CR12_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_npmos_cr13_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_npmos_cr13_1.sp deleted file mode 100644 index e3724abd80..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_npmos_cr13_1.sp +++ /dev/null @@ -1,65 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential -* View Name: schematic -* Netlisted on: Sep 11 21:04:32 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR13_2 Biasn Vbiasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_npmos_cr13_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_npmos_cr13_2.sp deleted file mode 100644 index e3724abd80..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_npmos_cr13_2.sp +++ /dev/null @@ -1,65 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential -* View Name: schematic -* Netlisted on: Sep 11 21:04:32 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR13_2 Biasn Vbiasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_npmos_cr14_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_npmos_cr14_2.sp deleted file mode 100644 index 36f249c482..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_npmos_cr14_2.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential -* View Name: schematic -* Netlisted on: Sep 11 21:04:32 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR14_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net010 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 Vbiasn net010 res=rK -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR14_2 Biasn Vbiasp CR14_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_npmos_cr1_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_npmos_cr1_1.sp deleted file mode 100644 index ff6615d3fc..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_npmos_cr1_1.sp +++ /dev/null @@ -1,63 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential -* View Name: schematic -* Netlisted on: Sep 11 21:04:32 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR1_1 Vbiasn -*.PININFO Vbiasn:O -RRF vdd! Vbiasn res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR1_1 Biasn CR1_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_npmos_cr2_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_npmos_cr2_2.sp deleted file mode 100644 index be477129ac..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_npmos_cr2_2.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential -* View Name: schematic -* Netlisted on: Sep 11 21:04:32 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR2_2_wilson Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -RR0 Vbiasn gnd! res=rK -MM2 Vbiasp net12 Vbiasn gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR2_2_wilson Biasn Vbiasp CR2_2_wilson -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_npmos_cr3_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_npmos_cr3_2.sp deleted file mode 100644 index ab700a1044..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_npmos_cr3_2.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential -* View Name: schematic -* Netlisted on: Sep 11 21:04:32 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR3_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 net15 gnd! res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR3_2 Biasn Vbiasp CR3_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_npmos_cr4_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_npmos_cr4_2.sp deleted file mode 100644 index 42b7350971..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_npmos_cr4_2.sp +++ /dev/null @@ -1,71 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential -* View Name: schematic -* Netlisted on: Sep 11 21:04:32 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR4_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM11 net023 net024 Vbiasn gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM8 net025 net010 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM9 net024 net024 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM7 net010 net010 net025 gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net025 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 net024 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net010 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR4_2 Biasn Vbiasp CR4_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_npmos_cr5_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_npmos_cr5_2.sp deleted file mode 100644 index e1008e34fd..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_npmos_cr5_2.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential -* View Name: schematic -* Netlisted on: Sep 11 21:04:32 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR5_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM5 net014 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net014 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR5_2 Biasn Vbiasp CR5_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_npmos_cr7_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_npmos_cr7_1.sp deleted file mode 100644 index 41951e8b1e..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_npmos_cr7_1.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential -* View Name: schematic -* Netlisted on: Sep 11 21:04:32 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR7_1 Vbiasn -*.PININFO Vbiasn:O -RR1 Vbiasn net7 res=rK -RR0 vdd! net7 res=rK -RRF vdd! Vbiasn res=rK -MM1 net7 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR7_1 Biasn CR7_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_npmos_cr9_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_npmos_cr9_1.sp deleted file mode 100644 index 6e33e7f11e..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_npmos_cr9_1.sp +++ /dev/null @@ -1,64 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential -* View Name: schematic -* Netlisted on: Sep 11 21:04:32 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR9_1 Vbiasn -*.PININFO Vbiasn:O -RR1 net05 gnd! res=rK -RRF vdd! Vbiasn res=rK -MM0 Vbiasn Vbiasn net05 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR9_1 Biasn CR9_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pmos_cr11_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pmos_cr11_1.sp deleted file mode 100644 index b17daf3725..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pmos_cr11_1.sp +++ /dev/null @@ -1,62 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential -* View Name: schematic -* Netlisted on: Sep 11 21:04:32 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos Biasn Vbiasp -*.PININFO Biasn:I Vbiasp:O -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR11_1 Vbiasn -*.PININFO Vbiasn:O -RRF vdd! Vbiasn res=rK -MM1 net9 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net9 net9 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn net9 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential -xiLG_pmos Biasn LG_Vbiasp LG_pmos -xibCR11_1 Biasn CR11_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pmos_cr12_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pmos_cr12_1.sp deleted file mode 100644 index c313cd3463..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pmos_cr12_1.sp +++ /dev/null @@ -1,62 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential -* View Name: schematic -* Netlisted on: Sep 11 21:04:32 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos Biasn Vbiasp -*.PININFO Biasn:I Vbiasp:O -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR12_1 Vbiasn -*.PININFO Vbiasn:O -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 net10 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn net10 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RRF vdd! Vbiasn res=rK -RR0 vdd! net10 res=rK -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential -xiLG_pmos Biasn LG_Vbiasp LG_pmos -xibCR12_1 Biasn CR12_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pmos_cr13_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pmos_cr13_1.sp deleted file mode 100644 index 1b57be972b..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pmos_cr13_1.sp +++ /dev/null @@ -1,61 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential -* View Name: schematic -* Netlisted on: Sep 11 21:04:32 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos Biasn Vbiasp -*.PININFO Biasn:I Vbiasp:O -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential -xiLG_pmos Biasn LG_Vbiasp LG_pmos -xibCR13_2 Biasn Vbiasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pmos_cr13_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pmos_cr13_2.sp deleted file mode 100644 index 1b57be972b..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pmos_cr13_2.sp +++ /dev/null @@ -1,61 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential -* View Name: schematic -* Netlisted on: Sep 11 21:04:32 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos Biasn Vbiasp -*.PININFO Biasn:I Vbiasp:O -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential -xiLG_pmos Biasn LG_Vbiasp LG_pmos -xibCR13_2 Biasn Vbiasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pmos_cr14_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pmos_cr14_2.sp deleted file mode 100644 index 1c89da7b56..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pmos_cr14_2.sp +++ /dev/null @@ -1,62 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential -* View Name: schematic -* Netlisted on: Sep 11 21:04:32 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos Biasn Vbiasp -*.PININFO Biasn:I Vbiasp:O -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR14_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net010 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 Vbiasn net010 res=rK -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential -xiLG_pmos Biasn LG_Vbiasp LG_pmos -xibCR14_2 Biasn Vbiasp CR14_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pmos_cr1_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pmos_cr1_1.sp deleted file mode 100644 index bc1fc23642..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pmos_cr1_1.sp +++ /dev/null @@ -1,59 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential -* View Name: schematic -* Netlisted on: Sep 11 21:04:32 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos Biasn Vbiasp -*.PININFO Biasn:I Vbiasp:O -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR1_1 Vbiasn -*.PININFO Vbiasn:O -RRF vdd! Vbiasn res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential -xiLG_pmos Biasn LG_Vbiasp LG_pmos -xibCR1_1 Biasn CR1_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pmos_cr2_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pmos_cr2_2.sp deleted file mode 100644 index e9af90ba95..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pmos_cr2_2.sp +++ /dev/null @@ -1,62 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential -* View Name: schematic -* Netlisted on: Sep 11 21:04:32 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos Biasn Vbiasp -*.PININFO Biasn:I Vbiasp:O -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR2_2_wilson Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -RR0 Vbiasn gnd! res=rK -MM2 Vbiasp net12 Vbiasn gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential -xiLG_pmos Biasn LG_Vbiasp LG_pmos -xibCR2_2_wilson Biasn Vbiasp CR2_2_wilson -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pmos_cr3_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pmos_cr3_2.sp deleted file mode 100644 index 4b4af43e4e..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pmos_cr3_2.sp +++ /dev/null @@ -1,62 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential -* View Name: schematic -* Netlisted on: Sep 11 21:04:32 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos Biasn Vbiasp -*.PININFO Biasn:I Vbiasp:O -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR3_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 net15 gnd! res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential -xiLG_pmos Biasn LG_Vbiasp LG_pmos -xibCR3_2 Biasn Vbiasp CR3_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pmos_cr4_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pmos_cr4_2.sp deleted file mode 100644 index 7113fa3c1e..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pmos_cr4_2.sp +++ /dev/null @@ -1,67 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential -* View Name: schematic -* Netlisted on: Sep 11 21:04:32 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos Biasn Vbiasp -*.PININFO Biasn:I Vbiasp:O -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR4_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM11 net023 net024 Vbiasn gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM8 net025 net010 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM9 net024 net024 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM7 net010 net010 net025 gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net025 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 net024 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net010 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential -xiLG_pmos Biasn LG_Vbiasp LG_pmos -xibCR4_2 Biasn Vbiasp CR4_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pmos_cr5_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pmos_cr5_2.sp deleted file mode 100644 index 253932a9e1..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pmos_cr5_2.sp +++ /dev/null @@ -1,64 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential -* View Name: schematic -* Netlisted on: Sep 11 21:04:32 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos Biasn Vbiasp -*.PININFO Biasn:I Vbiasp:O -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR5_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM5 net014 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net014 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential -xiLG_pmos Biasn LG_Vbiasp LG_pmos -xibCR5_2 Biasn Vbiasp CR5_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pmos_cr7_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pmos_cr7_1.sp deleted file mode 100644 index ffb0a5ee61..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pmos_cr7_1.sp +++ /dev/null @@ -1,62 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential -* View Name: schematic -* Netlisted on: Sep 11 21:04:32 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos Biasn Vbiasp -*.PININFO Biasn:I Vbiasp:O -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR7_1 Vbiasn -*.PININFO Vbiasn:O -RR1 Vbiasn net7 res=rK -RR0 vdd! net7 res=rK -RRF vdd! Vbiasn res=rK -MM1 net7 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential -xiLG_pmos Biasn LG_Vbiasp LG_pmos -xibCR7_1 Biasn CR7_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pmos_cr9_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pmos_cr9_1.sp deleted file mode 100644 index 34a360f5f8..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pmos_cr9_1.sp +++ /dev/null @@ -1,60 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential -* View Name: schematic -* Netlisted on: Sep 11 21:04:32 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos Biasn Vbiasp -*.PININFO Biasn:I Vbiasp:O -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR9_1 Vbiasn -*.PININFO Vbiasn:O -RR1 net05 gnd! res=rK -RRF vdd! Vbiasn res=rK -MM0 Vbiasn Vbiasn net05 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential -xiLG_pmos Biasn LG_Vbiasp LG_pmos -xibCR9_1 Biasn CR9_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pmos_l1_cr13_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pmos_l1_cr13_1.sp deleted file mode 100644 index b59ee18585..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pmos_l1_cr13_1.sp +++ /dev/null @@ -1,63 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential -* View Name: schematic -* Netlisted on: Sep 11 21:04:32 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR13_2 Biasn Biasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pmos_l1_cr13_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pmos_l1_cr13_2.sp deleted file mode 100644 index b59ee18585..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pmos_l1_cr13_2.sp +++ /dev/null @@ -1,63 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential -* View Name: schematic -* Netlisted on: Sep 11 21:04:32 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR13_2 Biasn Biasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pmos_l1_cr14_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pmos_l1_cr14_2.sp deleted file mode 100644 index 620d1fa151..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pmos_l1_cr14_2.sp +++ /dev/null @@ -1,64 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential -* View Name: schematic -* Netlisted on: Sep 11 21:04:32 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR14_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net010 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 Vbiasn net010 res=rK -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR14_2 Biasn Biasp CR14_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pmos_l1_cr15_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pmos_l1_cr15_1.sp deleted file mode 100644 index b727b042ec..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pmos_l1_cr15_1.sp +++ /dev/null @@ -1,61 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential -* View Name: schematic -* Netlisted on: Sep 11 21:04:32 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR15_1 Vbiasp -*.PININFO Vbiasp:O -RR1 Vbiasp gnd! res=rK -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR15_1 Biasp CR15_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pmos_l1_cr16_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pmos_l1_cr16_1.sp deleted file mode 100644 index cb1d5a3981..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pmos_l1_cr16_1.sp +++ /dev/null @@ -1,62 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential -* View Name: schematic -* Netlisted on: Sep 11 21:04:32 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR16_1 Vbiasp -*.PININFO Vbiasp:O -RR0 vdd! net6 res=rK -RR1 Vbiasp gnd! res=rK -MM2 Vbiasp Vbiasp net6 vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR16_1 Biasp CR16_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pmos_l1_cr2_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pmos_l1_cr2_2.sp deleted file mode 100644 index 2d9a115596..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pmos_l1_cr2_2.sp +++ /dev/null @@ -1,64 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential -* View Name: schematic -* Netlisted on: Sep 11 21:04:32 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR2_2_wilson Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -RR0 Vbiasn gnd! res=rK -MM2 Vbiasp net12 Vbiasn gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR2_2_wilson Biasn Biasp CR2_2_wilson -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pmos_l1_cr3_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pmos_l1_cr3_2.sp deleted file mode 100644 index eb1f7874d5..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pmos_l1_cr3_2.sp +++ /dev/null @@ -1,64 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential -* View Name: schematic -* Netlisted on: Sep 11 21:04:32 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR3_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 net15 gnd! res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR3_2 Biasn Biasp CR3_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pmos_l1_cr4_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pmos_l1_cr4_2.sp deleted file mode 100644 index fcd6253600..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pmos_l1_cr4_2.sp +++ /dev/null @@ -1,69 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential -* View Name: schematic -* Netlisted on: Sep 11 21:04:32 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR4_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM11 net023 net024 Vbiasn gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM8 net025 net010 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM9 net024 net024 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM7 net010 net010 net025 gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net025 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 net024 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net010 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR4_2 Biasn Biasp CR4_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pmos_l1_cr5_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pmos_l1_cr5_2.sp deleted file mode 100644 index 39f7b90039..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pmos_l1_cr5_2.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential -* View Name: schematic -* Netlisted on: Sep 11 21:04:32 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR5_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM5 net014 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net014 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR5_2 Biasn Biasp CR5_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pmos_l1_cr6_3.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pmos_l1_cr6_3.sp deleted file mode 100644 index 1ef13f1627..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pmos_l1_cr6_3.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential -* View Name: schematic -* Netlisted on: Sep 11 21:04:32 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR6_3 Vbiasn1 Vbiasn2 Vbiasp -*.PININFO Vbiasn1:O Vbiasn2:O Vbiasp:O -MM2 Vbiasp Vbiasn2 Vbiasn1 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn2 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 Vbiasn1 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM5 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn2 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR6_3 Biasn1 Biasn2 Biasp CR6_3 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pnmos_4_cr13_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pnmos_4_cr13_1.sp deleted file mode 100644 index bcfc985335..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pnmos_4_cr13_1.sp +++ /dev/null @@ -1,65 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential -* View Name: schematic -* Netlisted on: Sep 11 21:04:32 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR13_2 Biasn Biasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pnmos_4_cr13_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pnmos_4_cr13_2.sp deleted file mode 100644 index bcfc985335..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pnmos_4_cr13_2.sp +++ /dev/null @@ -1,65 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential -* View Name: schematic -* Netlisted on: Sep 11 21:04:32 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR13_2 Biasn Biasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pnmos_4_cr14_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pnmos_4_cr14_2.sp deleted file mode 100644 index e3ad2c976b..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pnmos_4_cr14_2.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential -* View Name: schematic -* Netlisted on: Sep 11 21:04:32 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR14_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net010 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 Vbiasn net010 res=rK -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR14_2 Biasn Biasp CR14_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pnmos_4_cr15_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pnmos_4_cr15_1.sp deleted file mode 100644 index a7eda684d7..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pnmos_4_cr15_1.sp +++ /dev/null @@ -1,63 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential -* View Name: schematic -* Netlisted on: Sep 11 21:04:32 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR15_1 Vbiasp -*.PININFO Vbiasp:O -RR1 Vbiasp gnd! res=rK -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR15_1 Biasp CR15_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pnmos_4_cr16_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pnmos_4_cr16_1.sp deleted file mode 100644 index 3cd94bb9af..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pnmos_4_cr16_1.sp +++ /dev/null @@ -1,64 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential -* View Name: schematic -* Netlisted on: Sep 11 21:04:32 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR16_1 Vbiasp -*.PININFO Vbiasp:O -RR0 vdd! net6 res=rK -RR1 Vbiasp gnd! res=rK -MM2 Vbiasp Vbiasp net6 vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR16_1 Biasp CR16_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pnmos_4_cr2_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pnmos_4_cr2_2.sp deleted file mode 100644 index 4cd33b6034..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pnmos_4_cr2_2.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential -* View Name: schematic -* Netlisted on: Sep 11 21:04:32 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR2_2_wilson Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -RR0 Vbiasn gnd! res=rK -MM2 Vbiasp net12 Vbiasn gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR2_2_wilson Biasn Biasp CR2_2_wilson -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pnmos_4_cr3_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pnmos_4_cr3_2.sp deleted file mode 100644 index 47d74ff196..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pnmos_4_cr3_2.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential -* View Name: schematic -* Netlisted on: Sep 11 21:04:32 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR3_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 net15 gnd! res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR3_2 Biasn Biasp CR3_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pnmos_4_cr4_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pnmos_4_cr4_2.sp deleted file mode 100644 index 33c2b51489..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pnmos_4_cr4_2.sp +++ /dev/null @@ -1,71 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential -* View Name: schematic -* Netlisted on: Sep 11 21:04:32 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR4_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM11 net023 net024 Vbiasn gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM8 net025 net010 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM9 net024 net024 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM7 net010 net010 net025 gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net025 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 net024 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net010 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR4_2 Biasn Biasp CR4_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pnmos_4_cr5_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pnmos_4_cr5_2.sp deleted file mode 100644 index 23fc4c6cbd..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pnmos_4_cr5_2.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential -* View Name: schematic -* Netlisted on: Sep 11 21:04:32 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR5_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM5 net014 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net014 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR5_2 Biasn Biasp CR5_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pnmos_4_cr6_3.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pnmos_4_cr6_3.sp deleted file mode 100644 index c088d2313d..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pnmos_4_cr6_3.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential -* View Name: schematic -* Netlisted on: Sep 11 21:04:32 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR6_3 Vbiasn1 Vbiasn2 Vbiasp -*.PININFO Vbiasn1:O Vbiasn2:O Vbiasp:O -MM2 Vbiasp Vbiasn2 Vbiasn1 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn2 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 Vbiasn1 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM5 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn2 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR6_3 Biasn1 Biasn2 Biasp CR6_3 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pnmos_cr13_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pnmos_cr13_1.sp deleted file mode 100644 index f8f28454f6..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pnmos_cr13_1.sp +++ /dev/null @@ -1,65 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential -* View Name: schematic -* Netlisted on: Sep 11 21:04:32 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR13_2 Biasn Biasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pnmos_cr13_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pnmos_cr13_2.sp deleted file mode 100644 index f8f28454f6..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pnmos_cr13_2.sp +++ /dev/null @@ -1,65 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential -* View Name: schematic -* Netlisted on: Sep 11 21:04:32 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR13_2 Biasn Biasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pnmos_cr14_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pnmos_cr14_2.sp deleted file mode 100644 index 4325caab3d..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pnmos_cr14_2.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential -* View Name: schematic -* Netlisted on: Sep 11 21:04:32 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR14_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net010 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 Vbiasn net010 res=rK -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR14_2 Biasn Biasp CR14_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pnmos_cr15_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pnmos_cr15_1.sp deleted file mode 100644 index 447900f24b..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pnmos_cr15_1.sp +++ /dev/null @@ -1,63 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential -* View Name: schematic -* Netlisted on: Sep 11 21:04:32 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR15_1 Vbiasp -*.PININFO Vbiasp:O -RR1 Vbiasp gnd! res=rK -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR15_1 Biasp CR15_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pnmos_cr16_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pnmos_cr16_1.sp deleted file mode 100644 index bfaeb2aaf8..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pnmos_cr16_1.sp +++ /dev/null @@ -1,64 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential -* View Name: schematic -* Netlisted on: Sep 11 21:04:32 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR16_1 Vbiasp -*.PININFO Vbiasp:O -RR0 vdd! net6 res=rK -RR1 Vbiasp gnd! res=rK -MM2 Vbiasp Vbiasp net6 vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR16_1 Biasp CR16_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pnmos_cr2_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pnmos_cr2_2.sp deleted file mode 100644 index 04ba389a87..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pnmos_cr2_2.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential -* View Name: schematic -* Netlisted on: Sep 11 21:04:32 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR2_2_wilson Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -RR0 Vbiasn gnd! res=rK -MM2 Vbiasp net12 Vbiasn gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR2_2_wilson Biasn Biasp CR2_2_wilson -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pnmos_cr3_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pnmos_cr3_2.sp deleted file mode 100644 index 1a54c76a3d..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pnmos_cr3_2.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential -* View Name: schematic -* Netlisted on: Sep 11 21:04:32 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR3_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 net15 gnd! res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR3_2 Biasn Biasp CR3_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pnmos_cr4_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pnmos_cr4_2.sp deleted file mode 100644 index acaee2f5ad..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pnmos_cr4_2.sp +++ /dev/null @@ -1,71 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential -* View Name: schematic -* Netlisted on: Sep 11 21:04:32 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR4_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM11 net023 net024 Vbiasn gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM8 net025 net010 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM9 net024 net024 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM7 net010 net010 net025 gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net025 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 net024 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net010 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR4_2 Biasn Biasp CR4_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pnmos_cr5_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pnmos_cr5_2.sp deleted file mode 100644 index 2ee3d5585b..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pnmos_cr5_2.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential -* View Name: schematic -* Netlisted on: Sep 11 21:04:32 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR5_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM5 net014 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net014 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR5_2 Biasn Biasp CR5_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pnmos_cr6_3.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pnmos_cr6_3.sp deleted file mode 100644 index 28570adbdf..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_LG_pnmos_cr6_3.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential -* View Name: schematic -* Netlisted on: Sep 11 21:04:32 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR6_3 Vbiasn1 Vbiasn2 Vbiasp -*.PININFO Vbiasn1:O Vbiasn2:O Vbiasp:O -MM2 Vbiasp Vbiasn2 Vbiasn1 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn2 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 Vbiasn1 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM5 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn2 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR6_3 Biasn1 Biasn2 Biasp CR6_3 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_LG_load_biasp_LV_cr11_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_LG_load_biasp_LV_cr11_1.sp deleted file mode 100644 index 943bb1e7d7..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_LG_load_biasp_LV_cr11_1.sp +++ /dev/null @@ -1,65 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_cascode -* View Name: schematic -* Netlisted on: Sep 11 21:04:46 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_cascode -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_cascode Vbiasn Vbiasp1 Vbiasp2 Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vbiasp1:I Vbiasp2:I Vinn:I Vinp:I Voutn:O Voutp:O -MM3 Voutn Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutp Vbiasp2 net22 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn Vbiasp2 net21 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net21 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net22 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasp_LV Biasn Vbiasp2 -*.PININFO Biasn:I Vbiasp2:O -MM0 Vbiasp2 Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net8 Vbiasp2 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp2 Vbiasp2 net8 vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR11_1 Vbiasn -*.PININFO Vbiasn:O -RRF vdd! Vbiasn res=rK -MM1 net9 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net9 net9 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn net9 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp1 LG_Vbiasp2 Vinn Vinp Voutn Voutp fully_differential_cascode -xiLG_load_biasp_LV Biasn LG_Vbiasp2 LG_load_biasp_LV -xibCR11_1 Biasn CR11_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_LG_load_biasp_LV_cr12_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_LG_load_biasp_LV_cr12_1.sp deleted file mode 100644 index 198c76cd92..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_LG_load_biasp_LV_cr12_1.sp +++ /dev/null @@ -1,65 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_cascode -* View Name: schematic -* Netlisted on: Sep 11 21:04:46 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_cascode -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_cascode Vbiasn Vbiasp1 Vbiasp2 Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vbiasp1:I Vbiasp2:I Vinn:I Vinp:I Voutn:O Voutp:O -MM3 Voutn Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutp Vbiasp2 net22 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn Vbiasp2 net21 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net21 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net22 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasp_LV Biasn Vbiasp2 -*.PININFO Biasn:I Vbiasp2:O -MM0 Vbiasp2 Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net8 Vbiasp2 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp2 Vbiasp2 net8 vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR12_1 Vbiasn -*.PININFO Vbiasn:O -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 net10 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn net10 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RRF vdd! Vbiasn res=rK -RR0 vdd! net10 res=rK -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp1 LG_Vbiasp2 Vinn Vinp Voutn Voutp fully_differential_cascode -xiLG_load_biasp_LV Biasn LG_Vbiasp2 LG_load_biasp_LV -xibCR12_1 Biasn CR12_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_LG_load_biasp_LV_cr13_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_LG_load_biasp_LV_cr13_1.sp deleted file mode 100644 index 11a0c56aaf..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_LG_load_biasp_LV_cr13_1.sp +++ /dev/null @@ -1,64 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_cascode -* View Name: schematic -* Netlisted on: Sep 11 21:04:46 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_cascode -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_cascode Vbiasn Vbiasp1 Vbiasp2 Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vbiasp1:I Vbiasp2:I Vinn:I Vinp:I Voutn:O Voutp:O -MM3 Voutn Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutp Vbiasp2 net22 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn Vbiasp2 net21 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net21 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net22 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasp_LV Biasn Vbiasp2 -*.PININFO Biasn:I Vbiasp2:O -MM0 Vbiasp2 Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net8 Vbiasp2 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp2 Vbiasp2 net8 vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp1 LG_Vbiasp2 Vinn Vinp Voutn Voutp fully_differential_cascode -xiLG_load_biasp_LV Biasn LG_Vbiasp2 LG_load_biasp_LV -xibCR13_2 Biasn Vbiasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_LG_load_biasp_LV_cr13_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_LG_load_biasp_LV_cr13_2.sp deleted file mode 100644 index 11a0c56aaf..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_LG_load_biasp_LV_cr13_2.sp +++ /dev/null @@ -1,64 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_cascode -* View Name: schematic -* Netlisted on: Sep 11 21:04:46 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_cascode -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_cascode Vbiasn Vbiasp1 Vbiasp2 Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vbiasp1:I Vbiasp2:I Vinn:I Vinp:I Voutn:O Voutp:O -MM3 Voutn Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutp Vbiasp2 net22 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn Vbiasp2 net21 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net21 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net22 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasp_LV Biasn Vbiasp2 -*.PININFO Biasn:I Vbiasp2:O -MM0 Vbiasp2 Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net8 Vbiasp2 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp2 Vbiasp2 net8 vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp1 LG_Vbiasp2 Vinn Vinp Voutn Voutp fully_differential_cascode -xiLG_load_biasp_LV Biasn LG_Vbiasp2 LG_load_biasp_LV -xibCR13_2 Biasn Vbiasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_LG_load_biasp_LV_cr14_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_LG_load_biasp_LV_cr14_2.sp deleted file mode 100644 index 801de176fe..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_LG_load_biasp_LV_cr14_2.sp +++ /dev/null @@ -1,65 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_cascode -* View Name: schematic -* Netlisted on: Sep 11 21:04:46 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_cascode -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_cascode Vbiasn Vbiasp1 Vbiasp2 Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vbiasp1:I Vbiasp2:I Vinn:I Vinp:I Voutn:O Voutp:O -MM3 Voutn Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutp Vbiasp2 net22 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn Vbiasp2 net21 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net21 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net22 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasp_LV Biasn Vbiasp2 -*.PININFO Biasn:I Vbiasp2:O -MM0 Vbiasp2 Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net8 Vbiasp2 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp2 Vbiasp2 net8 vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR14_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net010 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 Vbiasn net010 res=rK -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp1 LG_Vbiasp2 Vinn Vinp Voutn Voutp fully_differential_cascode -xiLG_load_biasp_LV Biasn LG_Vbiasp2 LG_load_biasp_LV -xibCR14_2 Biasn Vbiasp CR14_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_LG_load_biasp_LV_cr1_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_LG_load_biasp_LV_cr1_1.sp deleted file mode 100644 index 943c743126..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_LG_load_biasp_LV_cr1_1.sp +++ /dev/null @@ -1,62 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_cascode -* View Name: schematic -* Netlisted on: Sep 11 21:04:46 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_cascode -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_cascode Vbiasn Vbiasp1 Vbiasp2 Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vbiasp1:I Vbiasp2:I Vinn:I Vinp:I Voutn:O Voutp:O -MM3 Voutn Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutp Vbiasp2 net22 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn Vbiasp2 net21 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net21 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net22 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasp_LV Biasn Vbiasp2 -*.PININFO Biasn:I Vbiasp2:O -MM0 Vbiasp2 Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net8 Vbiasp2 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp2 Vbiasp2 net8 vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR1_1 Vbiasn -*.PININFO Vbiasn:O -RRF vdd! Vbiasn res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp1 LG_Vbiasp2 Vinn Vinp Voutn Voutp fully_differential_cascode -xiLG_load_biasp_LV Biasn LG_Vbiasp2 LG_load_biasp_LV -xibCR1_1 Biasn CR1_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_LG_load_biasp_LV_cr2_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_LG_load_biasp_LV_cr2_2.sp deleted file mode 100644 index 1ef8b23008..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_LG_load_biasp_LV_cr2_2.sp +++ /dev/null @@ -1,65 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_cascode -* View Name: schematic -* Netlisted on: Sep 11 21:04:46 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_cascode -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_cascode Vbiasn Vbiasp1 Vbiasp2 Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vbiasp1:I Vbiasp2:I Vinn:I Vinp:I Voutn:O Voutp:O -MM3 Voutn Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutp Vbiasp2 net22 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn Vbiasp2 net21 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net21 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net22 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasp_LV Biasn Vbiasp2 -*.PININFO Biasn:I Vbiasp2:O -MM0 Vbiasp2 Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net8 Vbiasp2 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp2 Vbiasp2 net8 vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR2_2_wilson Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -RR0 Vbiasn gnd! res=rK -MM2 Vbiasp net12 Vbiasn gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp1 LG_Vbiasp2 Vinn Vinp Voutn Voutp fully_differential_cascode -xiLG_load_biasp_LV Biasn LG_Vbiasp2 LG_load_biasp_LV -xibCR2_2_wilson Biasn Vbiasp CR2_2_wilson -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_LG_load_biasp_LV_cr3_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_LG_load_biasp_LV_cr3_2.sp deleted file mode 100644 index 8b7cd0abf8..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_LG_load_biasp_LV_cr3_2.sp +++ /dev/null @@ -1,65 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_cascode -* View Name: schematic -* Netlisted on: Sep 11 21:04:46 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_cascode -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_cascode Vbiasn Vbiasp1 Vbiasp2 Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vbiasp1:I Vbiasp2:I Vinn:I Vinp:I Voutn:O Voutp:O -MM3 Voutn Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutp Vbiasp2 net22 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn Vbiasp2 net21 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net21 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net22 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasp_LV Biasn Vbiasp2 -*.PININFO Biasn:I Vbiasp2:O -MM0 Vbiasp2 Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net8 Vbiasp2 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp2 Vbiasp2 net8 vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR3_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 net15 gnd! res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp1 LG_Vbiasp2 Vinn Vinp Voutn Voutp fully_differential_cascode -xiLG_load_biasp_LV Biasn LG_Vbiasp2 LG_load_biasp_LV -xibCR3_2 Biasn Vbiasp CR3_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_LG_load_biasp_LV_cr4_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_LG_load_biasp_LV_cr4_2.sp deleted file mode 100644 index 86f641eb42..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_LG_load_biasp_LV_cr4_2.sp +++ /dev/null @@ -1,70 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_cascode -* View Name: schematic -* Netlisted on: Sep 11 21:04:46 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_cascode -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_cascode Vbiasn Vbiasp1 Vbiasp2 Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vbiasp1:I Vbiasp2:I Vinn:I Vinp:I Voutn:O Voutp:O -MM3 Voutn Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutp Vbiasp2 net22 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn Vbiasp2 net21 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net21 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net22 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasp_LV Biasn Vbiasp2 -*.PININFO Biasn:I Vbiasp2:O -MM0 Vbiasp2 Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net8 Vbiasp2 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp2 Vbiasp2 net8 vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR4_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM11 net023 net024 Vbiasn gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM8 net025 net010 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM9 net024 net024 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM7 net010 net010 net025 gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net025 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 net024 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net010 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp1 LG_Vbiasp2 Vinn Vinp Voutn Voutp fully_differential_cascode -xiLG_load_biasp_LV Biasn LG_Vbiasp2 LG_load_biasp_LV -xibCR4_2 Biasn Vbiasp CR4_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_LG_load_biasp_LV_cr5_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_LG_load_biasp_LV_cr5_2.sp deleted file mode 100644 index 3a6ebd68bd..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_LG_load_biasp_LV_cr5_2.sp +++ /dev/null @@ -1,67 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_cascode -* View Name: schematic -* Netlisted on: Sep 11 21:04:46 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_cascode -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_cascode Vbiasn Vbiasp1 Vbiasp2 Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vbiasp1:I Vbiasp2:I Vinn:I Vinp:I Voutn:O Voutp:O -MM3 Voutn Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutp Vbiasp2 net22 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn Vbiasp2 net21 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net21 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net22 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasp_LV Biasn Vbiasp2 -*.PININFO Biasn:I Vbiasp2:O -MM0 Vbiasp2 Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net8 Vbiasp2 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp2 Vbiasp2 net8 vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR5_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM5 net014 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net014 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp1 LG_Vbiasp2 Vinn Vinp Voutn Voutp fully_differential_cascode -xiLG_load_biasp_LV Biasn LG_Vbiasp2 LG_load_biasp_LV -xibCR5_2 Biasn Vbiasp CR5_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_LG_load_biasp_LV_cr7_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_LG_load_biasp_LV_cr7_1.sp deleted file mode 100644 index 2d565efb66..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_LG_load_biasp_LV_cr7_1.sp +++ /dev/null @@ -1,65 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_cascode -* View Name: schematic -* Netlisted on: Sep 11 21:04:46 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_cascode -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_cascode Vbiasn Vbiasp1 Vbiasp2 Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vbiasp1:I Vbiasp2:I Vinn:I Vinp:I Voutn:O Voutp:O -MM3 Voutn Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutp Vbiasp2 net22 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn Vbiasp2 net21 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net21 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net22 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasp_LV Biasn Vbiasp2 -*.PININFO Biasn:I Vbiasp2:O -MM0 Vbiasp2 Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net8 Vbiasp2 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp2 Vbiasp2 net8 vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR7_1 Vbiasn -*.PININFO Vbiasn:O -RR1 Vbiasn net7 res=rK -RR0 vdd! net7 res=rK -RRF vdd! Vbiasn res=rK -MM1 net7 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp1 LG_Vbiasp2 Vinn Vinp Voutn Voutp fully_differential_cascode -xiLG_load_biasp_LV Biasn LG_Vbiasp2 LG_load_biasp_LV -xibCR7_1 Biasn CR7_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_LG_load_biasp_LV_cr9_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_LG_load_biasp_LV_cr9_1.sp deleted file mode 100644 index d8c0dafead..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_LG_load_biasp_LV_cr9_1.sp +++ /dev/null @@ -1,63 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_cascode -* View Name: schematic -* Netlisted on: Sep 11 21:04:46 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_cascode -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_cascode Vbiasn Vbiasp1 Vbiasp2 Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vbiasp1:I Vbiasp2:I Vinn:I Vinp:I Voutn:O Voutp:O -MM3 Voutn Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutp Vbiasp2 net22 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn Vbiasp2 net21 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net21 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net22 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasp_LV Biasn Vbiasp2 -*.PININFO Biasn:I Vbiasp2:O -MM0 Vbiasp2 Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net8 Vbiasp2 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp2 Vbiasp2 net8 vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR9_1 Vbiasn -*.PININFO Vbiasn:O -RR1 net05 gnd! res=rK -RRF vdd! Vbiasn res=rK -MM0 Vbiasn Vbiasn net05 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp1 LG_Vbiasp2 Vinn Vinp Voutn Voutp fully_differential_cascode -xiLG_load_biasp_LV Biasn LG_Vbiasp2 LG_load_biasp_LV -xibCR9_1 Biasn CR9_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_LG_load_biasp_cr11_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_LG_load_biasp_cr11_1.sp deleted file mode 100644 index 0c55df93b1..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_LG_load_biasp_cr11_1.sp +++ /dev/null @@ -1,65 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_cascode -* View Name: schematic -* Netlisted on: Sep 11 21:04:46 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_cascode -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_cascode Vbiasn Vbiasp1 Vbiasp2 Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vbiasp1:I Vbiasp2:I Vinn:I Vinp:I Voutn:O Voutp:O -MM3 Voutn Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutp Vbiasp2 net22 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn Vbiasp2 net21 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net21 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net22 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasp Biasn Vbiasp1 Vbiasp2 -*.PININFO Biasn:I Vbiasp1:O Vbiasp2:O -MM0 Vbiasp2 Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp2 Vbiasp2 Vbiasp1 vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp1 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR11_1 Vbiasn -*.PININFO Vbiasn:O -RRF vdd! Vbiasn res=rK -MM1 net9 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net9 net9 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn net9 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp1 LG_Vbiasp2 Vinn Vinp Voutn Voutp fully_differential_cascode -xiLG_load_biasp Biasn LG_Vbiasp1 LG_Vbiasp2 LG_load_biasp -xibCR11_1 Biasn CR11_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_LG_load_biasp_cr12_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_LG_load_biasp_cr12_1.sp deleted file mode 100644 index c5e8ef3512..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_LG_load_biasp_cr12_1.sp +++ /dev/null @@ -1,65 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_cascode -* View Name: schematic -* Netlisted on: Sep 11 21:04:46 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_cascode -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_cascode Vbiasn Vbiasp1 Vbiasp2 Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vbiasp1:I Vbiasp2:I Vinn:I Vinp:I Voutn:O Voutp:O -MM3 Voutn Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutp Vbiasp2 net22 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn Vbiasp2 net21 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net21 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net22 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasp Biasn Vbiasp1 Vbiasp2 -*.PININFO Biasn:I Vbiasp1:O Vbiasp2:O -MM0 Vbiasp2 Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp2 Vbiasp2 Vbiasp1 vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp1 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR12_1 Vbiasn -*.PININFO Vbiasn:O -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 net10 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn net10 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RRF vdd! Vbiasn res=rK -RR0 vdd! net10 res=rK -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp1 LG_Vbiasp2 Vinn Vinp Voutn Voutp fully_differential_cascode -xiLG_load_biasp Biasn LG_Vbiasp1 LG_Vbiasp2 LG_load_biasp -xibCR12_1 Biasn CR12_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_LG_load_biasp_cr13_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_LG_load_biasp_cr13_1.sp deleted file mode 100644 index e49508f150..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_LG_load_biasp_cr13_1.sp +++ /dev/null @@ -1,64 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_cascode -* View Name: schematic -* Netlisted on: Sep 11 21:04:46 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_cascode -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_cascode Vbiasn Vbiasp1 Vbiasp2 Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vbiasp1:I Vbiasp2:I Vinn:I Vinp:I Voutn:O Voutp:O -MM3 Voutn Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutp Vbiasp2 net22 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn Vbiasp2 net21 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net21 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net22 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasp Biasn Vbiasp1 Vbiasp2 -*.PININFO Biasn:I Vbiasp1:O Vbiasp2:O -MM0 Vbiasp2 Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp2 Vbiasp2 Vbiasp1 vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp1 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp1 LG_Vbiasp2 Vinn Vinp Voutn Voutp fully_differential_cascode -xiLG_load_biasp Biasn LG_Vbiasp1 LG_Vbiasp2 LG_load_biasp -xibCR13_2 Biasn Vbiasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_LG_load_biasp_cr13_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_LG_load_biasp_cr13_2.sp deleted file mode 100644 index e49508f150..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_LG_load_biasp_cr13_2.sp +++ /dev/null @@ -1,64 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_cascode -* View Name: schematic -* Netlisted on: Sep 11 21:04:46 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_cascode -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_cascode Vbiasn Vbiasp1 Vbiasp2 Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vbiasp1:I Vbiasp2:I Vinn:I Vinp:I Voutn:O Voutp:O -MM3 Voutn Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutp Vbiasp2 net22 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn Vbiasp2 net21 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net21 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net22 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasp Biasn Vbiasp1 Vbiasp2 -*.PININFO Biasn:I Vbiasp1:O Vbiasp2:O -MM0 Vbiasp2 Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp2 Vbiasp2 Vbiasp1 vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp1 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp1 LG_Vbiasp2 Vinn Vinp Voutn Voutp fully_differential_cascode -xiLG_load_biasp Biasn LG_Vbiasp1 LG_Vbiasp2 LG_load_biasp -xibCR13_2 Biasn Vbiasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_LG_load_biasp_cr14_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_LG_load_biasp_cr14_2.sp deleted file mode 100644 index 1d185d373e..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_LG_load_biasp_cr14_2.sp +++ /dev/null @@ -1,65 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_cascode -* View Name: schematic -* Netlisted on: Sep 11 21:04:46 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_cascode -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_cascode Vbiasn Vbiasp1 Vbiasp2 Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vbiasp1:I Vbiasp2:I Vinn:I Vinp:I Voutn:O Voutp:O -MM3 Voutn Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutp Vbiasp2 net22 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn Vbiasp2 net21 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net21 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net22 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasp Biasn Vbiasp1 Vbiasp2 -*.PININFO Biasn:I Vbiasp1:O Vbiasp2:O -MM0 Vbiasp2 Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp2 Vbiasp2 Vbiasp1 vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp1 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR14_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net010 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 Vbiasn net010 res=rK -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp1 LG_Vbiasp2 Vinn Vinp Voutn Voutp fully_differential_cascode -xiLG_load_biasp Biasn LG_Vbiasp1 LG_Vbiasp2 LG_load_biasp -xibCR14_2 Biasn Vbiasp CR14_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_LG_load_biasp_cr1_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_LG_load_biasp_cr1_1.sp deleted file mode 100644 index 1691f095df..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_LG_load_biasp_cr1_1.sp +++ /dev/null @@ -1,62 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_cascode -* View Name: schematic -* Netlisted on: Sep 11 21:04:46 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_cascode -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_cascode Vbiasn Vbiasp1 Vbiasp2 Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vbiasp1:I Vbiasp2:I Vinn:I Vinp:I Voutn:O Voutp:O -MM3 Voutn Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutp Vbiasp2 net22 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn Vbiasp2 net21 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net21 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net22 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasp Biasn Vbiasp1 Vbiasp2 -*.PININFO Biasn:I Vbiasp1:O Vbiasp2:O -MM0 Vbiasp2 Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp2 Vbiasp2 Vbiasp1 vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp1 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR1_1 Vbiasn -*.PININFO Vbiasn:O -RRF vdd! Vbiasn res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp1 LG_Vbiasp2 Vinn Vinp Voutn Voutp fully_differential_cascode -xiLG_load_biasp Biasn LG_Vbiasp1 LG_Vbiasp2 LG_load_biasp -xibCR1_1 Biasn CR1_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_LG_load_biasp_cr2_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_LG_load_biasp_cr2_2.sp deleted file mode 100644 index fb8f73b53a..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_LG_load_biasp_cr2_2.sp +++ /dev/null @@ -1,65 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_cascode -* View Name: schematic -* Netlisted on: Sep 11 21:04:46 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_cascode -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_cascode Vbiasn Vbiasp1 Vbiasp2 Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vbiasp1:I Vbiasp2:I Vinn:I Vinp:I Voutn:O Voutp:O -MM3 Voutn Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutp Vbiasp2 net22 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn Vbiasp2 net21 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net21 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net22 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasp Biasn Vbiasp1 Vbiasp2 -*.PININFO Biasn:I Vbiasp1:O Vbiasp2:O -MM0 Vbiasp2 Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp2 Vbiasp2 Vbiasp1 vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp1 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR2_2_wilson Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -RR0 Vbiasn gnd! res=rK -MM2 Vbiasp net12 Vbiasn gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp1 LG_Vbiasp2 Vinn Vinp Voutn Voutp fully_differential_cascode -xiLG_load_biasp Biasn LG_Vbiasp1 LG_Vbiasp2 LG_load_biasp -xibCR2_2_wilson Biasn Vbiasp CR2_2_wilson -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_LG_load_biasp_cr3_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_LG_load_biasp_cr3_2.sp deleted file mode 100644 index 63dccc70e0..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_LG_load_biasp_cr3_2.sp +++ /dev/null @@ -1,65 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_cascode -* View Name: schematic -* Netlisted on: Sep 11 21:04:46 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_cascode -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_cascode Vbiasn Vbiasp1 Vbiasp2 Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vbiasp1:I Vbiasp2:I Vinn:I Vinp:I Voutn:O Voutp:O -MM3 Voutn Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutp Vbiasp2 net22 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn Vbiasp2 net21 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net21 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net22 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasp Biasn Vbiasp1 Vbiasp2 -*.PININFO Biasn:I Vbiasp1:O Vbiasp2:O -MM0 Vbiasp2 Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp2 Vbiasp2 Vbiasp1 vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp1 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR3_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 net15 gnd! res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp1 LG_Vbiasp2 Vinn Vinp Voutn Voutp fully_differential_cascode -xiLG_load_biasp Biasn LG_Vbiasp1 LG_Vbiasp2 LG_load_biasp -xibCR3_2 Biasn Vbiasp CR3_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_LG_load_biasp_cr4_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_LG_load_biasp_cr4_2.sp deleted file mode 100644 index bb762d0852..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_LG_load_biasp_cr4_2.sp +++ /dev/null @@ -1,70 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_cascode -* View Name: schematic -* Netlisted on: Sep 11 21:04:46 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_cascode -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_cascode Vbiasn Vbiasp1 Vbiasp2 Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vbiasp1:I Vbiasp2:I Vinn:I Vinp:I Voutn:O Voutp:O -MM3 Voutn Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutp Vbiasp2 net22 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn Vbiasp2 net21 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net21 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net22 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasp Biasn Vbiasp1 Vbiasp2 -*.PININFO Biasn:I Vbiasp1:O Vbiasp2:O -MM0 Vbiasp2 Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp2 Vbiasp2 Vbiasp1 vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp1 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR4_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM11 net023 net024 Vbiasn gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM8 net025 net010 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM9 net024 net024 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM7 net010 net010 net025 gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net025 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 net024 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net010 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp1 LG_Vbiasp2 Vinn Vinp Voutn Voutp fully_differential_cascode -xiLG_load_biasp Biasn LG_Vbiasp1 LG_Vbiasp2 LG_load_biasp -xibCR4_2 Biasn Vbiasp CR4_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_LG_load_biasp_cr5_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_LG_load_biasp_cr5_2.sp deleted file mode 100644 index a23ecb58c7..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_LG_load_biasp_cr5_2.sp +++ /dev/null @@ -1,67 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_cascode -* View Name: schematic -* Netlisted on: Sep 11 21:04:46 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_cascode -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_cascode Vbiasn Vbiasp1 Vbiasp2 Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vbiasp1:I Vbiasp2:I Vinn:I Vinp:I Voutn:O Voutp:O -MM3 Voutn Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutp Vbiasp2 net22 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn Vbiasp2 net21 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net21 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net22 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasp Biasn Vbiasp1 Vbiasp2 -*.PININFO Biasn:I Vbiasp1:O Vbiasp2:O -MM0 Vbiasp2 Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp2 Vbiasp2 Vbiasp1 vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp1 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR5_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM5 net014 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net014 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp1 LG_Vbiasp2 Vinn Vinp Voutn Voutp fully_differential_cascode -xiLG_load_biasp Biasn LG_Vbiasp1 LG_Vbiasp2 LG_load_biasp -xibCR5_2 Biasn Vbiasp CR5_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_LG_load_biasp_cr7_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_LG_load_biasp_cr7_1.sp deleted file mode 100644 index 857148d88b..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_LG_load_biasp_cr7_1.sp +++ /dev/null @@ -1,65 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_cascode -* View Name: schematic -* Netlisted on: Sep 11 21:04:46 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_cascode -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_cascode Vbiasn Vbiasp1 Vbiasp2 Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vbiasp1:I Vbiasp2:I Vinn:I Vinp:I Voutn:O Voutp:O -MM3 Voutn Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutp Vbiasp2 net22 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn Vbiasp2 net21 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net21 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net22 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasp Biasn Vbiasp1 Vbiasp2 -*.PININFO Biasn:I Vbiasp1:O Vbiasp2:O -MM0 Vbiasp2 Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp2 Vbiasp2 Vbiasp1 vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp1 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR7_1 Vbiasn -*.PININFO Vbiasn:O -RR1 Vbiasn net7 res=rK -RR0 vdd! net7 res=rK -RRF vdd! Vbiasn res=rK -MM1 net7 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp1 LG_Vbiasp2 Vinn Vinp Voutn Voutp fully_differential_cascode -xiLG_load_biasp Biasn LG_Vbiasp1 LG_Vbiasp2 LG_load_biasp -xibCR7_1 Biasn CR7_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_LG_load_biasp_cr9_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_LG_load_biasp_cr9_1.sp deleted file mode 100644 index ab6f1a426f..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_LG_load_biasp_cr9_1.sp +++ /dev/null @@ -1,63 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_cascode -* View Name: schematic -* Netlisted on: Sep 11 21:04:46 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_cascode -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_cascode Vbiasn Vbiasp1 Vbiasp2 Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vbiasp1:I Vbiasp2:I Vinn:I Vinp:I Voutn:O Voutp:O -MM3 Voutn Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutp Vbiasp2 net22 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn Vbiasp2 net21 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net21 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net22 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasp Biasn Vbiasp1 Vbiasp2 -*.PININFO Biasn:I Vbiasp1:O Vbiasp2:O -MM0 Vbiasp2 Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp2 Vbiasp2 Vbiasp1 vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp1 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR9_1 Vbiasn -*.PININFO Vbiasn:O -RR1 net05 gnd! res=rK -RRF vdd! Vbiasn res=rK -MM0 Vbiasn Vbiasn net05 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp1 LG_Vbiasp2 Vinn Vinp Voutn Voutp fully_differential_cascode -xiLG_load_biasp Biasn LG_Vbiasp1 LG_Vbiasp2 LG_load_biasp -xibCR9_1 Biasn CR9_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_pmos_LG_load_biasn_LV_cr13_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_pmos_LG_load_biasn_LV_cr13_1.sp deleted file mode 100644 index 5aa7ee7f3f..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_pmos_LG_load_biasn_LV_cr13_1.sp +++ /dev/null @@ -1,65 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_cascode_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:05:09 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_cascode_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_cascode_pmos Vbiasn1 Vbiasn2 Vbiasp Vinn Vinp -+ Voutp1 Voutp2 -*.PININFO Vbiasp:I Vinn:I Vinp:I Vbiasn1:O Vbiasn2:O Voutp1:O Voutp2:O -MM1 Voutp2 Vbiasn2 net17 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp1 Vbiasn2 net18 gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net18 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net17 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM5 net13 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 Voutp1 Vinn net13 net20 pmos_rvt w=WA l=LA nfin=nA -MM6 Voutp2 Vinp net13 net20 pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasn_LV Vbiasn2 Biasp -*.PININFO Biasp:I Vbiasn2:O -MM13 net9 Vbiasn2 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM15 Vbiasn2 Vbiasn2 net9 gnd! nmos_rvt w=WA l=LA nfin=nA -MM14 Vbiasn2 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn1 LG_Vbiasn2 LG_Vbiasp Vinn Vinp fully_differential_cascode_pmos -xiLG_load_biasn_LV Biasp LG_Vbiasn2 LG_load_biasn_LV -xibCR13_2 Biasn Biasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_pmos_LG_load_biasn_LV_cr13_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_pmos_LG_load_biasn_LV_cr13_2.sp deleted file mode 100644 index 5aa7ee7f3f..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_pmos_LG_load_biasn_LV_cr13_2.sp +++ /dev/null @@ -1,65 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_cascode_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:05:09 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_cascode_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_cascode_pmos Vbiasn1 Vbiasn2 Vbiasp Vinn Vinp -+ Voutp1 Voutp2 -*.PININFO Vbiasp:I Vinn:I Vinp:I Vbiasn1:O Vbiasn2:O Voutp1:O Voutp2:O -MM1 Voutp2 Vbiasn2 net17 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp1 Vbiasn2 net18 gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net18 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net17 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM5 net13 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 Voutp1 Vinn net13 net20 pmos_rvt w=WA l=LA nfin=nA -MM6 Voutp2 Vinp net13 net20 pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasn_LV Vbiasn2 Biasp -*.PININFO Biasp:I Vbiasn2:O -MM13 net9 Vbiasn2 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM15 Vbiasn2 Vbiasn2 net9 gnd! nmos_rvt w=WA l=LA nfin=nA -MM14 Vbiasn2 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn1 LG_Vbiasn2 LG_Vbiasp Vinn Vinp fully_differential_cascode_pmos -xiLG_load_biasn_LV Biasp LG_Vbiasn2 LG_load_biasn_LV -xibCR13_2 Biasn Biasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_pmos_LG_load_biasn_LV_cr14_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_pmos_LG_load_biasn_LV_cr14_2.sp deleted file mode 100644 index 4f4031a6a1..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_pmos_LG_load_biasn_LV_cr14_2.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_cascode_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:05:09 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_cascode_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_cascode_pmos Vbiasn1 Vbiasn2 Vbiasp Vinn Vinp -+ Voutp1 Voutp2 -*.PININFO Vbiasp:I Vinn:I Vinp:I Vbiasn1:O Vbiasn2:O Voutp1:O Voutp2:O -MM1 Voutp2 Vbiasn2 net17 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp1 Vbiasn2 net18 gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net18 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net17 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM5 net13 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 Voutp1 Vinn net13 net20 pmos_rvt w=WA l=LA nfin=nA -MM6 Voutp2 Vinp net13 net20 pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasn_LV Vbiasn2 Biasp -*.PININFO Biasp:I Vbiasn2:O -MM13 net9 Vbiasn2 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM15 Vbiasn2 Vbiasn2 net9 gnd! nmos_rvt w=WA l=LA nfin=nA -MM14 Vbiasn2 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR14_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net010 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 Vbiasn net010 res=rK -.ENDS - - -xiota LG_Vbiasn1 LG_Vbiasn2 LG_Vbiasp Vinn Vinp fully_differential_cascode_pmos -xiLG_load_biasn_LV Biasp LG_Vbiasn2 LG_load_biasn_LV -xibCR14_2 Biasn Biasp CR14_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_pmos_LG_load_biasn_LV_cr15_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_pmos_LG_load_biasn_LV_cr15_1.sp deleted file mode 100644 index fafa6b1666..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_pmos_LG_load_biasn_LV_cr15_1.sp +++ /dev/null @@ -1,63 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_cascode_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:05:09 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_cascode_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_cascode_pmos Vbiasn1 Vbiasn2 Vbiasp Vinn Vinp -+ Voutp1 Voutp2 -*.PININFO Vbiasp:I Vinn:I Vinp:I Vbiasn1:O Vbiasn2:O Voutp1:O Voutp2:O -MM1 Voutp2 Vbiasn2 net17 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp1 Vbiasn2 net18 gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net18 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net17 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM5 net13 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 Voutp1 Vinn net13 net20 pmos_rvt w=WA l=LA nfin=nA -MM6 Voutp2 Vinp net13 net20 pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasn_LV Vbiasn2 Biasp -*.PININFO Biasp:I Vbiasn2:O -MM13 net9 Vbiasn2 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM15 Vbiasn2 Vbiasn2 net9 gnd! nmos_rvt w=WA l=LA nfin=nA -MM14 Vbiasn2 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR15_1 Vbiasp -*.PININFO Vbiasp:O -RR1 Vbiasp gnd! res=rK -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn1 LG_Vbiasn2 LG_Vbiasp Vinn Vinp fully_differential_cascode_pmos -xiLG_load_biasn_LV Biasp LG_Vbiasn2 LG_load_biasn_LV -xibCR15_1 Biasp CR15_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_pmos_LG_load_biasn_LV_cr16_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_pmos_LG_load_biasn_LV_cr16_1.sp deleted file mode 100644 index 95deed1eda..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_pmos_LG_load_biasn_LV_cr16_1.sp +++ /dev/null @@ -1,64 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_cascode_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:05:09 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_cascode_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_cascode_pmos Vbiasn1 Vbiasn2 Vbiasp Vinn Vinp -+ Voutp1 Voutp2 -*.PININFO Vbiasp:I Vinn:I Vinp:I Vbiasn1:O Vbiasn2:O Voutp1:O Voutp2:O -MM1 Voutp2 Vbiasn2 net17 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp1 Vbiasn2 net18 gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net18 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net17 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM5 net13 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 Voutp1 Vinn net13 net20 pmos_rvt w=WA l=LA nfin=nA -MM6 Voutp2 Vinp net13 net20 pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasn_LV Vbiasn2 Biasp -*.PININFO Biasp:I Vbiasn2:O -MM13 net9 Vbiasn2 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM15 Vbiasn2 Vbiasn2 net9 gnd! nmos_rvt w=WA l=LA nfin=nA -MM14 Vbiasn2 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR16_1 Vbiasp -*.PININFO Vbiasp:O -RR0 vdd! net6 res=rK -RR1 Vbiasp gnd! res=rK -MM2 Vbiasp Vbiasp net6 vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn1 LG_Vbiasn2 LG_Vbiasp Vinn Vinp fully_differential_cascode_pmos -xiLG_load_biasn_LV Biasp LG_Vbiasn2 LG_load_biasn_LV -xibCR16_1 Biasp CR16_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_pmos_LG_load_biasn_LV_cr2_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_pmos_LG_load_biasn_LV_cr2_2.sp deleted file mode 100644 index 9182122efc..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_pmos_LG_load_biasn_LV_cr2_2.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_cascode_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:05:09 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_cascode_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_cascode_pmos Vbiasn1 Vbiasn2 Vbiasp Vinn Vinp -+ Voutp1 Voutp2 -*.PININFO Vbiasp:I Vinn:I Vinp:I Vbiasn1:O Vbiasn2:O Voutp1:O Voutp2:O -MM1 Voutp2 Vbiasn2 net17 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp1 Vbiasn2 net18 gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net18 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net17 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM5 net13 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 Voutp1 Vinn net13 net20 pmos_rvt w=WA l=LA nfin=nA -MM6 Voutp2 Vinp net13 net20 pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasn_LV Vbiasn2 Biasp -*.PININFO Biasp:I Vbiasn2:O -MM13 net9 Vbiasn2 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM15 Vbiasn2 Vbiasn2 net9 gnd! nmos_rvt w=WA l=LA nfin=nA -MM14 Vbiasn2 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR2_2_wilson Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -RR0 Vbiasn gnd! res=rK -MM2 Vbiasp net12 Vbiasn gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn1 LG_Vbiasn2 LG_Vbiasp Vinn Vinp fully_differential_cascode_pmos -xiLG_load_biasn_LV Biasp LG_Vbiasn2 LG_load_biasn_LV -xibCR2_2_wilson Biasn Biasp CR2_2_wilson -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_pmos_LG_load_biasn_LV_cr3_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_pmos_LG_load_biasn_LV_cr3_2.sp deleted file mode 100644 index 87192bec27..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_pmos_LG_load_biasn_LV_cr3_2.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_cascode_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:05:09 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_cascode_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_cascode_pmos Vbiasn1 Vbiasn2 Vbiasp Vinn Vinp -+ Voutp1 Voutp2 -*.PININFO Vbiasp:I Vinn:I Vinp:I Vbiasn1:O Vbiasn2:O Voutp1:O Voutp2:O -MM1 Voutp2 Vbiasn2 net17 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp1 Vbiasn2 net18 gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net18 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net17 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM5 net13 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 Voutp1 Vinn net13 net20 pmos_rvt w=WA l=LA nfin=nA -MM6 Voutp2 Vinp net13 net20 pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasn_LV Vbiasn2 Biasp -*.PININFO Biasp:I Vbiasn2:O -MM13 net9 Vbiasn2 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM15 Vbiasn2 Vbiasn2 net9 gnd! nmos_rvt w=WA l=LA nfin=nA -MM14 Vbiasn2 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR3_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 net15 gnd! res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn1 LG_Vbiasn2 LG_Vbiasp Vinn Vinp fully_differential_cascode_pmos -xiLG_load_biasn_LV Biasp LG_Vbiasn2 LG_load_biasn_LV -xibCR3_2 Biasn Biasp CR3_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_pmos_LG_load_biasn_LV_cr4_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_pmos_LG_load_biasn_LV_cr4_2.sp deleted file mode 100644 index 22e0bd6ad7..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_pmos_LG_load_biasn_LV_cr4_2.sp +++ /dev/null @@ -1,71 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_cascode_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:05:09 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_cascode_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_cascode_pmos Vbiasn1 Vbiasn2 Vbiasp Vinn Vinp -+ Voutp1 Voutp2 -*.PININFO Vbiasp:I Vinn:I Vinp:I Vbiasn1:O Vbiasn2:O Voutp1:O Voutp2:O -MM1 Voutp2 Vbiasn2 net17 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp1 Vbiasn2 net18 gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net18 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net17 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM5 net13 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 Voutp1 Vinn net13 net20 pmos_rvt w=WA l=LA nfin=nA -MM6 Voutp2 Vinp net13 net20 pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasn_LV Vbiasn2 Biasp -*.PININFO Biasp:I Vbiasn2:O -MM13 net9 Vbiasn2 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM15 Vbiasn2 Vbiasn2 net9 gnd! nmos_rvt w=WA l=LA nfin=nA -MM14 Vbiasn2 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR4_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM11 net023 net024 Vbiasn gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM8 net025 net010 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM9 net024 net024 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM7 net010 net010 net025 gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net025 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 net024 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net010 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn1 LG_Vbiasn2 LG_Vbiasp Vinn Vinp fully_differential_cascode_pmos -xiLG_load_biasn_LV Biasp LG_Vbiasn2 LG_load_biasn_LV -xibCR4_2 Biasn Biasp CR4_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_pmos_LG_load_biasn_LV_cr5_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_pmos_LG_load_biasn_LV_cr5_2.sp deleted file mode 100644 index 7649cf7640..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_pmos_LG_load_biasn_LV_cr5_2.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_cascode_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:05:09 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_cascode_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_cascode_pmos Vbiasn1 Vbiasn2 Vbiasp Vinn Vinp -+ Voutp1 Voutp2 -*.PININFO Vbiasp:I Vinn:I Vinp:I Vbiasn1:O Vbiasn2:O Voutp1:O Voutp2:O -MM1 Voutp2 Vbiasn2 net17 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp1 Vbiasn2 net18 gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net18 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net17 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM5 net13 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 Voutp1 Vinn net13 net20 pmos_rvt w=WA l=LA nfin=nA -MM6 Voutp2 Vinp net13 net20 pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasn_LV Vbiasn2 Biasp -*.PININFO Biasp:I Vbiasn2:O -MM13 net9 Vbiasn2 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM15 Vbiasn2 Vbiasn2 net9 gnd! nmos_rvt w=WA l=LA nfin=nA -MM14 Vbiasn2 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR5_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM5 net014 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net014 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn1 LG_Vbiasn2 LG_Vbiasp Vinn Vinp fully_differential_cascode_pmos -xiLG_load_biasn_LV Biasp LG_Vbiasn2 LG_load_biasn_LV -xibCR5_2 Biasn Biasp CR5_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_pmos_LG_load_biasn_LV_cr6_3.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_pmos_LG_load_biasn_LV_cr6_3.sp deleted file mode 100644 index f2b90afd13..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_pmos_LG_load_biasn_LV_cr6_3.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_cascode_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:05:09 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_cascode_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_cascode_pmos Vbiasn1 Vbiasn2 Vbiasp Vinn Vinp -+ Voutp1 Voutp2 -*.PININFO Vbiasp:I Vinn:I Vinp:I Vbiasn1:O Vbiasn2:O Voutp1:O Voutp2:O -MM1 Voutp2 Vbiasn2 net17 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp1 Vbiasn2 net18 gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net18 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net17 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM5 net13 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 Voutp1 Vinn net13 net20 pmos_rvt w=WA l=LA nfin=nA -MM6 Voutp2 Vinp net13 net20 pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasn_LV Vbiasn2 Biasp -*.PININFO Biasp:I Vbiasn2:O -MM13 net9 Vbiasn2 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM15 Vbiasn2 Vbiasn2 net9 gnd! nmos_rvt w=WA l=LA nfin=nA -MM14 Vbiasn2 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR6_3 Vbiasn1 Vbiasn2 Vbiasp -*.PININFO Vbiasn1:O Vbiasn2:O Vbiasp:O -MM2 Vbiasp Vbiasn2 Vbiasn1 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn2 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 Vbiasn1 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM5 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn2 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn1 LG_Vbiasn2 LG_Vbiasp Vinn Vinp fully_differential_cascode_pmos -xiLG_load_biasn_LV Biasp LG_Vbiasn2 LG_load_biasn_LV -xibCR6_3 Biasn1 Biasn2 Biasp CR6_3 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_pmos_LG_load_biasn_cr13_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_pmos_LG_load_biasn_cr13_1.sp deleted file mode 100644 index 13f28c7c0a..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_pmos_LG_load_biasn_cr13_1.sp +++ /dev/null @@ -1,65 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_cascode_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:05:09 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_cascode_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_cascode_pmos Vbiasn1 Vbiasn2 Vbiasp Vinn Vinp -+ Voutp1 Voutp2 -*.PININFO Vbiasp:I Vinn:I Vinp:I Vbiasn1:O Vbiasn2:O Voutp1:O Voutp2:O -MM1 Voutp2 Vbiasn2 net17 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp1 Vbiasn2 net18 gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net18 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net17 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM5 net13 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 Voutp1 Vinn net13 net20 pmos_rvt w=WA l=LA nfin=nA -MM6 Voutp2 Vinp net13 net20 pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasn Vbiasn1 Vbiasn2 Biasp -*.PININFO Biasp:I Vbiasn1:O Vbiasn2:O -MM15 Vbiasn2 Vbiasn2 Vbiasn1 gnd! nmos_rvt w=WA l=LA nfin=nA -MM13 Vbiasn1 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM14 Vbiasn2 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn1 LG_Vbiasn2 LG_Vbiasp Vinn Vinp fully_differential_cascode_pmos -xiLG_load_biasn Biasp LG_Vbiasn1 LG_Vbiasn2 LG_load_biasn -xibCR13_2 Biasn Biasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_pmos_LG_load_biasn_cr13_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_pmos_LG_load_biasn_cr13_2.sp deleted file mode 100644 index 13f28c7c0a..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_pmos_LG_load_biasn_cr13_2.sp +++ /dev/null @@ -1,65 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_cascode_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:05:09 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_cascode_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_cascode_pmos Vbiasn1 Vbiasn2 Vbiasp Vinn Vinp -+ Voutp1 Voutp2 -*.PININFO Vbiasp:I Vinn:I Vinp:I Vbiasn1:O Vbiasn2:O Voutp1:O Voutp2:O -MM1 Voutp2 Vbiasn2 net17 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp1 Vbiasn2 net18 gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net18 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net17 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM5 net13 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 Voutp1 Vinn net13 net20 pmos_rvt w=WA l=LA nfin=nA -MM6 Voutp2 Vinp net13 net20 pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasn Vbiasn1 Vbiasn2 Biasp -*.PININFO Biasp:I Vbiasn1:O Vbiasn2:O -MM15 Vbiasn2 Vbiasn2 Vbiasn1 gnd! nmos_rvt w=WA l=LA nfin=nA -MM13 Vbiasn1 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM14 Vbiasn2 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn1 LG_Vbiasn2 LG_Vbiasp Vinn Vinp fully_differential_cascode_pmos -xiLG_load_biasn Biasp LG_Vbiasn1 LG_Vbiasn2 LG_load_biasn -xibCR13_2 Biasn Biasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_pmos_LG_load_biasn_cr14_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_pmos_LG_load_biasn_cr14_2.sp deleted file mode 100644 index ccc4561762..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_pmos_LG_load_biasn_cr14_2.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_cascode_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:05:09 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_cascode_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_cascode_pmos Vbiasn1 Vbiasn2 Vbiasp Vinn Vinp -+ Voutp1 Voutp2 -*.PININFO Vbiasp:I Vinn:I Vinp:I Vbiasn1:O Vbiasn2:O Voutp1:O Voutp2:O -MM1 Voutp2 Vbiasn2 net17 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp1 Vbiasn2 net18 gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net18 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net17 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM5 net13 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 Voutp1 Vinn net13 net20 pmos_rvt w=WA l=LA nfin=nA -MM6 Voutp2 Vinp net13 net20 pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasn Vbiasn1 Vbiasn2 Biasp -*.PININFO Biasp:I Vbiasn1:O Vbiasn2:O -MM15 Vbiasn2 Vbiasn2 Vbiasn1 gnd! nmos_rvt w=WA l=LA nfin=nA -MM13 Vbiasn1 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM14 Vbiasn2 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR14_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net010 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 Vbiasn net010 res=rK -.ENDS - - -xiota LG_Vbiasn1 LG_Vbiasn2 LG_Vbiasp Vinn Vinp fully_differential_cascode_pmos -xiLG_load_biasn Biasp LG_Vbiasn1 LG_Vbiasn2 LG_load_biasn -xibCR14_2 Biasn Biasp CR14_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_pmos_LG_load_biasn_cr15_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_pmos_LG_load_biasn_cr15_1.sp deleted file mode 100644 index cbab5595c2..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_pmos_LG_load_biasn_cr15_1.sp +++ /dev/null @@ -1,63 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_cascode_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:05:09 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_cascode_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_cascode_pmos Vbiasn1 Vbiasn2 Vbiasp Vinn Vinp -+ Voutp1 Voutp2 -*.PININFO Vbiasp:I Vinn:I Vinp:I Vbiasn1:O Vbiasn2:O Voutp1:O Voutp2:O -MM1 Voutp2 Vbiasn2 net17 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp1 Vbiasn2 net18 gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net18 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net17 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM5 net13 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 Voutp1 Vinn net13 net20 pmos_rvt w=WA l=LA nfin=nA -MM6 Voutp2 Vinp net13 net20 pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasn Vbiasn1 Vbiasn2 Biasp -*.PININFO Biasp:I Vbiasn1:O Vbiasn2:O -MM15 Vbiasn2 Vbiasn2 Vbiasn1 gnd! nmos_rvt w=WA l=LA nfin=nA -MM13 Vbiasn1 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM14 Vbiasn2 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR15_1 Vbiasp -*.PININFO Vbiasp:O -RR1 Vbiasp gnd! res=rK -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn1 LG_Vbiasn2 LG_Vbiasp Vinn Vinp fully_differential_cascode_pmos -xiLG_load_biasn Biasp LG_Vbiasn1 LG_Vbiasn2 LG_load_biasn -xibCR15_1 Biasp CR15_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_pmos_LG_load_biasn_cr16_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_pmos_LG_load_biasn_cr16_1.sp deleted file mode 100644 index ef8b615e69..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_pmos_LG_load_biasn_cr16_1.sp +++ /dev/null @@ -1,64 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_cascode_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:05:09 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_cascode_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_cascode_pmos Vbiasn1 Vbiasn2 Vbiasp Vinn Vinp -+ Voutp1 Voutp2 -*.PININFO Vbiasp:I Vinn:I Vinp:I Vbiasn1:O Vbiasn2:O Voutp1:O Voutp2:O -MM1 Voutp2 Vbiasn2 net17 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp1 Vbiasn2 net18 gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net18 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net17 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM5 net13 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 Voutp1 Vinn net13 net20 pmos_rvt w=WA l=LA nfin=nA -MM6 Voutp2 Vinp net13 net20 pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasn Vbiasn1 Vbiasn2 Biasp -*.PININFO Biasp:I Vbiasn1:O Vbiasn2:O -MM15 Vbiasn2 Vbiasn2 Vbiasn1 gnd! nmos_rvt w=WA l=LA nfin=nA -MM13 Vbiasn1 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM14 Vbiasn2 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR16_1 Vbiasp -*.PININFO Vbiasp:O -RR0 vdd! net6 res=rK -RR1 Vbiasp gnd! res=rK -MM2 Vbiasp Vbiasp net6 vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn1 LG_Vbiasn2 LG_Vbiasp Vinn Vinp fully_differential_cascode_pmos -xiLG_load_biasn Biasp LG_Vbiasn1 LG_Vbiasn2 LG_load_biasn -xibCR16_1 Biasp CR16_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_pmos_LG_load_biasn_cr2_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_pmos_LG_load_biasn_cr2_2.sp deleted file mode 100644 index 317c4bc47f..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_pmos_LG_load_biasn_cr2_2.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_cascode_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:05:09 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_cascode_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_cascode_pmos Vbiasn1 Vbiasn2 Vbiasp Vinn Vinp -+ Voutp1 Voutp2 -*.PININFO Vbiasp:I Vinn:I Vinp:I Vbiasn1:O Vbiasn2:O Voutp1:O Voutp2:O -MM1 Voutp2 Vbiasn2 net17 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp1 Vbiasn2 net18 gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net18 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net17 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM5 net13 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 Voutp1 Vinn net13 net20 pmos_rvt w=WA l=LA nfin=nA -MM6 Voutp2 Vinp net13 net20 pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasn Vbiasn1 Vbiasn2 Biasp -*.PININFO Biasp:I Vbiasn1:O Vbiasn2:O -MM15 Vbiasn2 Vbiasn2 Vbiasn1 gnd! nmos_rvt w=WA l=LA nfin=nA -MM13 Vbiasn1 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM14 Vbiasn2 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR2_2_wilson Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -RR0 Vbiasn gnd! res=rK -MM2 Vbiasp net12 Vbiasn gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn1 LG_Vbiasn2 LG_Vbiasp Vinn Vinp fully_differential_cascode_pmos -xiLG_load_biasn Biasp LG_Vbiasn1 LG_Vbiasn2 LG_load_biasn -xibCR2_2_wilson Biasn Biasp CR2_2_wilson -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_pmos_LG_load_biasn_cr3_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_pmos_LG_load_biasn_cr3_2.sp deleted file mode 100644 index 9556001ab0..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_pmos_LG_load_biasn_cr3_2.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_cascode_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:05:09 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_cascode_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_cascode_pmos Vbiasn1 Vbiasn2 Vbiasp Vinn Vinp -+ Voutp1 Voutp2 -*.PININFO Vbiasp:I Vinn:I Vinp:I Vbiasn1:O Vbiasn2:O Voutp1:O Voutp2:O -MM1 Voutp2 Vbiasn2 net17 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp1 Vbiasn2 net18 gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net18 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net17 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM5 net13 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 Voutp1 Vinn net13 net20 pmos_rvt w=WA l=LA nfin=nA -MM6 Voutp2 Vinp net13 net20 pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasn Vbiasn1 Vbiasn2 Biasp -*.PININFO Biasp:I Vbiasn1:O Vbiasn2:O -MM15 Vbiasn2 Vbiasn2 Vbiasn1 gnd! nmos_rvt w=WA l=LA nfin=nA -MM13 Vbiasn1 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM14 Vbiasn2 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR3_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 net15 gnd! res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn1 LG_Vbiasn2 LG_Vbiasp Vinn Vinp fully_differential_cascode_pmos -xiLG_load_biasn Biasp LG_Vbiasn1 LG_Vbiasn2 LG_load_biasn -xibCR3_2 Biasn Biasp CR3_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_pmos_LG_load_biasn_cr4_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_pmos_LG_load_biasn_cr4_2.sp deleted file mode 100644 index 1a38c7e50e..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_pmos_LG_load_biasn_cr4_2.sp +++ /dev/null @@ -1,71 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_cascode_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:05:09 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_cascode_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_cascode_pmos Vbiasn1 Vbiasn2 Vbiasp Vinn Vinp -+ Voutp1 Voutp2 -*.PININFO Vbiasp:I Vinn:I Vinp:I Vbiasn1:O Vbiasn2:O Voutp1:O Voutp2:O -MM1 Voutp2 Vbiasn2 net17 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp1 Vbiasn2 net18 gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net18 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net17 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM5 net13 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 Voutp1 Vinn net13 net20 pmos_rvt w=WA l=LA nfin=nA -MM6 Voutp2 Vinp net13 net20 pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasn Vbiasn1 Vbiasn2 Biasp -*.PININFO Biasp:I Vbiasn1:O Vbiasn2:O -MM15 Vbiasn2 Vbiasn2 Vbiasn1 gnd! nmos_rvt w=WA l=LA nfin=nA -MM13 Vbiasn1 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM14 Vbiasn2 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR4_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM11 net023 net024 Vbiasn gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM8 net025 net010 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM9 net024 net024 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM7 net010 net010 net025 gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net025 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 net024 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net010 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn1 LG_Vbiasn2 LG_Vbiasp Vinn Vinp fully_differential_cascode_pmos -xiLG_load_biasn Biasp LG_Vbiasn1 LG_Vbiasn2 LG_load_biasn -xibCR4_2 Biasn Biasp CR4_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_pmos_LG_load_biasn_cr5_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_pmos_LG_load_biasn_cr5_2.sp deleted file mode 100644 index 564db590fd..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_pmos_LG_load_biasn_cr5_2.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_cascode_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:05:09 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_cascode_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_cascode_pmos Vbiasn1 Vbiasn2 Vbiasp Vinn Vinp -+ Voutp1 Voutp2 -*.PININFO Vbiasp:I Vinn:I Vinp:I Vbiasn1:O Vbiasn2:O Voutp1:O Voutp2:O -MM1 Voutp2 Vbiasn2 net17 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp1 Vbiasn2 net18 gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net18 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net17 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM5 net13 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 Voutp1 Vinn net13 net20 pmos_rvt w=WA l=LA nfin=nA -MM6 Voutp2 Vinp net13 net20 pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasn Vbiasn1 Vbiasn2 Biasp -*.PININFO Biasp:I Vbiasn1:O Vbiasn2:O -MM15 Vbiasn2 Vbiasn2 Vbiasn1 gnd! nmos_rvt w=WA l=LA nfin=nA -MM13 Vbiasn1 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM14 Vbiasn2 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR5_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM5 net014 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net014 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn1 LG_Vbiasn2 LG_Vbiasp Vinn Vinp fully_differential_cascode_pmos -xiLG_load_biasn Biasp LG_Vbiasn1 LG_Vbiasn2 LG_load_biasn -xibCR5_2 Biasn Biasp CR5_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_pmos_LG_load_biasn_cr6_3.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_pmos_LG_load_biasn_cr6_3.sp deleted file mode 100644 index 3e68b3f131..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_cascode_pmos_LG_load_biasn_cr6_3.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_cascode_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:05:09 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_cascode_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_cascode_pmos Vbiasn1 Vbiasn2 Vbiasp Vinn Vinp -+ Voutp1 Voutp2 -*.PININFO Vbiasp:I Vinn:I Vinp:I Vbiasn1:O Vbiasn2:O Voutp1:O Voutp2:O -MM1 Voutp2 Vbiasn2 net17 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp1 Vbiasn2 net18 gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net18 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net17 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM5 net13 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 Voutp1 Vinn net13 net20 pmos_rvt w=WA l=LA nfin=nA -MM6 Voutp2 Vinp net13 net20 pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasn Vbiasn1 Vbiasn2 Biasp -*.PININFO Biasp:I Vbiasn1:O Vbiasn2:O -MM15 Vbiasn2 Vbiasn2 Vbiasn1 gnd! nmos_rvt w=WA l=LA nfin=nA -MM13 Vbiasn1 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM14 Vbiasn2 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR6_3 Vbiasn1 Vbiasn2 Vbiasp -*.PININFO Vbiasn1:O Vbiasn2:O Vbiasp:O -MM2 Vbiasp Vbiasn2 Vbiasn1 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn2 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 Vbiasn1 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM5 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn2 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn1 LG_Vbiasn2 LG_Vbiasp Vinn Vinp fully_differential_cascode_pmos -xiLG_load_biasn Biasp LG_Vbiasn1 LG_Vbiasn2 LG_load_biasn -xibCR6_3 Biasn1 Biasn2 Biasp CR6_3 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_nmos_cr13_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_nmos_cr13_1.sp deleted file mode 100644 index 8db562ac51..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_nmos_cr13_1.sp +++ /dev/null @@ -1,82 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_gain_boosting -* View Name: schematic -* Netlisted on: Sep 11 21:05:36 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vinn Vinp Voutn Voutp -*.PININFO Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_gain_boosting -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_gain_boosting Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Vbiasp:O Voutn:O Voutp:O -MM8 Voutn net22 net23 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp net19 net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net23 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net21 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn net24 net25 vdd pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net20 net12 vdd pmos_rvt w=WA l=LA nfin=nA -MM1 net25 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -XI3 net12 net25 net24 net20 / fully_differential -XI1 net23 net21 net19 net22 / fully_differential -.ENDS - - -.SUBCKT LG_nmos Biasp Vbiasn -*.PININFO Biasp:I Vbiasn:O -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_gain_boosting -xiLG_nmos Biasp LG_Vbiasn LG_nmos -xibCR13_2 Biasn Biasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_nmos_cr13_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_nmos_cr13_2.sp deleted file mode 100644 index 8db562ac51..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_nmos_cr13_2.sp +++ /dev/null @@ -1,82 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_gain_boosting -* View Name: schematic -* Netlisted on: Sep 11 21:05:36 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vinn Vinp Voutn Voutp -*.PININFO Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_gain_boosting -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_gain_boosting Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Vbiasp:O Voutn:O Voutp:O -MM8 Voutn net22 net23 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp net19 net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net23 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net21 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn net24 net25 vdd pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net20 net12 vdd pmos_rvt w=WA l=LA nfin=nA -MM1 net25 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -XI3 net12 net25 net24 net20 / fully_differential -XI1 net23 net21 net19 net22 / fully_differential -.ENDS - - -.SUBCKT LG_nmos Biasp Vbiasn -*.PININFO Biasp:I Vbiasn:O -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_gain_boosting -xiLG_nmos Biasp LG_Vbiasn LG_nmos -xibCR13_2 Biasn Biasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_nmos_cr14_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_nmos_cr14_2.sp deleted file mode 100644 index e7738c6ec6..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_nmos_cr14_2.sp +++ /dev/null @@ -1,83 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_gain_boosting -* View Name: schematic -* Netlisted on: Sep 11 21:05:36 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vinn Vinp Voutn Voutp -*.PININFO Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_gain_boosting -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_gain_boosting Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Vbiasp:O Voutn:O Voutp:O -MM8 Voutn net22 net23 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp net19 net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net23 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net21 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn net24 net25 vdd pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net20 net12 vdd pmos_rvt w=WA l=LA nfin=nA -MM1 net25 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -XI3 net12 net25 net24 net20 / fully_differential -XI1 net23 net21 net19 net22 / fully_differential -.ENDS - - -.SUBCKT LG_nmos Biasp Vbiasn -*.PININFO Biasp:I Vbiasn:O -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR14_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net010 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 Vbiasn net010 res=rK -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_gain_boosting -xiLG_nmos Biasp LG_Vbiasn LG_nmos -xibCR14_2 Biasn Biasp CR14_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_nmos_cr15_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_nmos_cr15_1.sp deleted file mode 100644 index 6df188e43c..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_nmos_cr15_1.sp +++ /dev/null @@ -1,80 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_gain_boosting -* View Name: schematic -* Netlisted on: Sep 11 21:05:36 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vinn Vinp Voutn Voutp -*.PININFO Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_gain_boosting -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_gain_boosting Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Vbiasp:O Voutn:O Voutp:O -MM8 Voutn net22 net23 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp net19 net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net23 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net21 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn net24 net25 vdd pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net20 net12 vdd pmos_rvt w=WA l=LA nfin=nA -MM1 net25 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -XI3 net12 net25 net24 net20 / fully_differential -XI1 net23 net21 net19 net22 / fully_differential -.ENDS - - -.SUBCKT LG_nmos Biasp Vbiasn -*.PININFO Biasp:I Vbiasn:O -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR15_1 Vbiasp -*.PININFO Vbiasp:O -RR1 Vbiasp gnd! res=rK -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_gain_boosting -xiLG_nmos Biasp LG_Vbiasn LG_nmos -xibCR15_1 Biasp CR15_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_nmos_cr16_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_nmos_cr16_1.sp deleted file mode 100644 index f2899a4a17..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_nmos_cr16_1.sp +++ /dev/null @@ -1,81 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_gain_boosting -* View Name: schematic -* Netlisted on: Sep 11 21:05:36 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vinn Vinp Voutn Voutp -*.PININFO Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_gain_boosting -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_gain_boosting Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Vbiasp:O Voutn:O Voutp:O -MM8 Voutn net22 net23 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp net19 net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net23 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net21 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn net24 net25 vdd pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net20 net12 vdd pmos_rvt w=WA l=LA nfin=nA -MM1 net25 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -XI3 net12 net25 net24 net20 / fully_differential -XI1 net23 net21 net19 net22 / fully_differential -.ENDS - - -.SUBCKT LG_nmos Biasp Vbiasn -*.PININFO Biasp:I Vbiasn:O -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR16_1 Vbiasp -*.PININFO Vbiasp:O -RR0 vdd! net6 res=rK -RR1 Vbiasp gnd! res=rK -MM2 Vbiasp Vbiasp net6 vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_gain_boosting -xiLG_nmos Biasp LG_Vbiasn LG_nmos -xibCR16_1 Biasp CR16_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_nmos_cr2_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_nmos_cr2_2.sp deleted file mode 100644 index b8376ea8ed..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_nmos_cr2_2.sp +++ /dev/null @@ -1,83 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_gain_boosting -* View Name: schematic -* Netlisted on: Sep 11 21:05:36 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vinn Vinp Voutn Voutp -*.PININFO Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_gain_boosting -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_gain_boosting Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Vbiasp:O Voutn:O Voutp:O -MM8 Voutn net22 net23 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp net19 net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net23 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net21 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn net24 net25 vdd pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net20 net12 vdd pmos_rvt w=WA l=LA nfin=nA -MM1 net25 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -XI3 net12 net25 net24 net20 / fully_differential -XI1 net23 net21 net19 net22 / fully_differential -.ENDS - - -.SUBCKT LG_nmos Biasp Vbiasn -*.PININFO Biasp:I Vbiasn:O -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR2_2_wilson Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -RR0 Vbiasn gnd! res=rK -MM2 Vbiasp net12 Vbiasn gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_gain_boosting -xiLG_nmos Biasp LG_Vbiasn LG_nmos -xibCR2_2_wilson Biasn Biasp CR2_2_wilson -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_nmos_cr3_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_nmos_cr3_2.sp deleted file mode 100644 index 75e9fd02cd..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_nmos_cr3_2.sp +++ /dev/null @@ -1,83 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_gain_boosting -* View Name: schematic -* Netlisted on: Sep 11 21:05:36 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vinn Vinp Voutn Voutp -*.PININFO Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_gain_boosting -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_gain_boosting Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Vbiasp:O Voutn:O Voutp:O -MM8 Voutn net22 net23 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp net19 net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net23 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net21 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn net24 net25 vdd pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net20 net12 vdd pmos_rvt w=WA l=LA nfin=nA -MM1 net25 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -XI3 net12 net25 net24 net20 / fully_differential -XI1 net23 net21 net19 net22 / fully_differential -.ENDS - - -.SUBCKT LG_nmos Biasp Vbiasn -*.PININFO Biasp:I Vbiasn:O -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR3_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 net15 gnd! res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_gain_boosting -xiLG_nmos Biasp LG_Vbiasn LG_nmos -xibCR3_2 Biasn Biasp CR3_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_nmos_cr4_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_nmos_cr4_2.sp deleted file mode 100644 index 7e616a4e41..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_nmos_cr4_2.sp +++ /dev/null @@ -1,88 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_gain_boosting -* View Name: schematic -* Netlisted on: Sep 11 21:05:36 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vinn Vinp Voutn Voutp -*.PININFO Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_gain_boosting -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_gain_boosting Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Vbiasp:O Voutn:O Voutp:O -MM8 Voutn net22 net23 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp net19 net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net23 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net21 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn net24 net25 vdd pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net20 net12 vdd pmos_rvt w=WA l=LA nfin=nA -MM1 net25 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -XI3 net12 net25 net24 net20 / fully_differential -XI1 net23 net21 net19 net22 / fully_differential -.ENDS - - -.SUBCKT LG_nmos Biasp Vbiasn -*.PININFO Biasp:I Vbiasn:O -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR4_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM11 net023 net024 Vbiasn gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM8 net025 net010 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM9 net024 net024 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM7 net010 net010 net025 gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net025 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 net024 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net010 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_gain_boosting -xiLG_nmos Biasp LG_Vbiasn LG_nmos -xibCR4_2 Biasn Biasp CR4_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_nmos_cr5_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_nmos_cr5_2.sp deleted file mode 100644 index 6306956cdc..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_nmos_cr5_2.sp +++ /dev/null @@ -1,85 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_gain_boosting -* View Name: schematic -* Netlisted on: Sep 11 21:05:36 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vinn Vinp Voutn Voutp -*.PININFO Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_gain_boosting -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_gain_boosting Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Vbiasp:O Voutn:O Voutp:O -MM8 Voutn net22 net23 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp net19 net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net23 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net21 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn net24 net25 vdd pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net20 net12 vdd pmos_rvt w=WA l=LA nfin=nA -MM1 net25 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -XI3 net12 net25 net24 net20 / fully_differential -XI1 net23 net21 net19 net22 / fully_differential -.ENDS - - -.SUBCKT LG_nmos Biasp Vbiasn -*.PININFO Biasp:I Vbiasn:O -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR5_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM5 net014 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net014 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_gain_boosting -xiLG_nmos Biasp LG_Vbiasn LG_nmos -xibCR5_2 Biasn Biasp CR5_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_nmos_cr6_3.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_nmos_cr6_3.sp deleted file mode 100644 index 899dadac26..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_nmos_cr6_3.sp +++ /dev/null @@ -1,85 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_gain_boosting -* View Name: schematic -* Netlisted on: Sep 11 21:05:36 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vinn Vinp Voutn Voutp -*.PININFO Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_gain_boosting -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_gain_boosting Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Vbiasp:O Voutn:O Voutp:O -MM8 Voutn net22 net23 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp net19 net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net23 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net21 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn net24 net25 vdd pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net20 net12 vdd pmos_rvt w=WA l=LA nfin=nA -MM1 net25 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -XI3 net12 net25 net24 net20 / fully_differential -XI1 net23 net21 net19 net22 / fully_differential -.ENDS - - -.SUBCKT LG_nmos Biasp Vbiasn -*.PININFO Biasp:I Vbiasn:O -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR6_3 Vbiasn1 Vbiasn2 Vbiasp -*.PININFO Vbiasn1:O Vbiasn2:O Vbiasp:O -MM2 Vbiasp Vbiasn2 Vbiasn1 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn2 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 Vbiasn1 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM5 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn2 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_gain_boosting -xiLG_nmos Biasp LG_Vbiasn LG_nmos -xibCR6_3 Biasn1 Biasn2 Biasp CR6_3 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_nmos_l1_cr11_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_nmos_l1_cr11_1.sp deleted file mode 100644 index e147e5f693..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_nmos_l1_cr11_1.sp +++ /dev/null @@ -1,85 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_gain_boosting -* View Name: schematic -* Netlisted on: Sep 11 21:05:36 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vinn Vinp Voutn Voutp -*.PININFO Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_gain_boosting -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_gain_boosting Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Vbiasp:O Voutn:O Voutp:O -MM8 Voutn net22 net23 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp net19 net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net23 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net21 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn net24 net25 vdd pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net20 net12 vdd pmos_rvt w=WA l=LA nfin=nA -MM1 net25 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -XI3 net12 net25 net24 net20 / fully_differential -XI1 net23 net21 net19 net22 / fully_differential -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR11_1 Vbiasn -*.PININFO Vbiasn:O -RRF vdd! Vbiasn res=rK -MM1 net9 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net9 net9 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn net9 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_gain_boosting -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR11_1 Biasn CR11_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_nmos_l1_cr12_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_nmos_l1_cr12_1.sp deleted file mode 100644 index 1846e63b99..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_nmos_l1_cr12_1.sp +++ /dev/null @@ -1,85 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_gain_boosting -* View Name: schematic -* Netlisted on: Sep 11 21:05:36 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vinn Vinp Voutn Voutp -*.PININFO Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_gain_boosting -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_gain_boosting Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Vbiasp:O Voutn:O Voutp:O -MM8 Voutn net22 net23 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp net19 net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net23 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net21 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn net24 net25 vdd pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net20 net12 vdd pmos_rvt w=WA l=LA nfin=nA -MM1 net25 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -XI3 net12 net25 net24 net20 / fully_differential -XI1 net23 net21 net19 net22 / fully_differential -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR12_1 Vbiasn -*.PININFO Vbiasn:O -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 net10 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn net10 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RRF vdd! Vbiasn res=rK -RR0 vdd! net10 res=rK -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_gain_boosting -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR12_1 Biasn CR12_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_nmos_l1_cr13_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_nmos_l1_cr13_1.sp deleted file mode 100644 index c467945d26..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_nmos_l1_cr13_1.sp +++ /dev/null @@ -1,84 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_gain_boosting -* View Name: schematic -* Netlisted on: Sep 11 21:05:36 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vinn Vinp Voutn Voutp -*.PININFO Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_gain_boosting -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_gain_boosting Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Vbiasp:O Voutn:O Voutp:O -MM8 Voutn net22 net23 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp net19 net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net23 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net21 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn net24 net25 vdd pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net20 net12 vdd pmos_rvt w=WA l=LA nfin=nA -MM1 net25 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -XI3 net12 net25 net24 net20 / fully_differential -XI1 net23 net21 net19 net22 / fully_differential -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_gain_boosting -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR13_2 Biasn Vbiasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_nmos_l1_cr13_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_nmos_l1_cr13_2.sp deleted file mode 100644 index c467945d26..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_nmos_l1_cr13_2.sp +++ /dev/null @@ -1,84 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_gain_boosting -* View Name: schematic -* Netlisted on: Sep 11 21:05:36 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vinn Vinp Voutn Voutp -*.PININFO Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_gain_boosting -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_gain_boosting Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Vbiasp:O Voutn:O Voutp:O -MM8 Voutn net22 net23 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp net19 net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net23 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net21 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn net24 net25 vdd pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net20 net12 vdd pmos_rvt w=WA l=LA nfin=nA -MM1 net25 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -XI3 net12 net25 net24 net20 / fully_differential -XI1 net23 net21 net19 net22 / fully_differential -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_gain_boosting -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR13_2 Biasn Vbiasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_nmos_l1_cr14_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_nmos_l1_cr14_2.sp deleted file mode 100644 index 313bdadcf5..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_nmos_l1_cr14_2.sp +++ /dev/null @@ -1,85 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_gain_boosting -* View Name: schematic -* Netlisted on: Sep 11 21:05:36 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vinn Vinp Voutn Voutp -*.PININFO Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_gain_boosting -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_gain_boosting Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Vbiasp:O Voutn:O Voutp:O -MM8 Voutn net22 net23 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp net19 net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net23 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net21 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn net24 net25 vdd pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net20 net12 vdd pmos_rvt w=WA l=LA nfin=nA -MM1 net25 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -XI3 net12 net25 net24 net20 / fully_differential -XI1 net23 net21 net19 net22 / fully_differential -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR14_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net010 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 Vbiasn net010 res=rK -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_gain_boosting -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR14_2 Biasn Vbiasp CR14_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_nmos_l1_cr1_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_nmos_l1_cr1_1.sp deleted file mode 100644 index ae1e89cfee..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_nmos_l1_cr1_1.sp +++ /dev/null @@ -1,82 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_gain_boosting -* View Name: schematic -* Netlisted on: Sep 11 21:05:36 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vinn Vinp Voutn Voutp -*.PININFO Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_gain_boosting -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_gain_boosting Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Vbiasp:O Voutn:O Voutp:O -MM8 Voutn net22 net23 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp net19 net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net23 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net21 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn net24 net25 vdd pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net20 net12 vdd pmos_rvt w=WA l=LA nfin=nA -MM1 net25 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -XI3 net12 net25 net24 net20 / fully_differential -XI1 net23 net21 net19 net22 / fully_differential -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR1_1 Vbiasn -*.PININFO Vbiasn:O -RRF vdd! Vbiasn res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_gain_boosting -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR1_1 Biasn CR1_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_nmos_l1_cr2_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_nmos_l1_cr2_2.sp deleted file mode 100644 index 4faedf8506..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_nmos_l1_cr2_2.sp +++ /dev/null @@ -1,85 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_gain_boosting -* View Name: schematic -* Netlisted on: Sep 11 21:05:36 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vinn Vinp Voutn Voutp -*.PININFO Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_gain_boosting -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_gain_boosting Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Vbiasp:O Voutn:O Voutp:O -MM8 Voutn net22 net23 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp net19 net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net23 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net21 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn net24 net25 vdd pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net20 net12 vdd pmos_rvt w=WA l=LA nfin=nA -MM1 net25 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -XI3 net12 net25 net24 net20 / fully_differential -XI1 net23 net21 net19 net22 / fully_differential -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR2_2_wilson Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -RR0 Vbiasn gnd! res=rK -MM2 Vbiasp net12 Vbiasn gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_gain_boosting -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR2_2_wilson Biasn Vbiasp CR2_2_wilson -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_nmos_l1_cr3_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_nmos_l1_cr3_2.sp deleted file mode 100644 index b9f9bc8c2c..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_nmos_l1_cr3_2.sp +++ /dev/null @@ -1,85 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_gain_boosting -* View Name: schematic -* Netlisted on: Sep 11 21:05:36 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vinn Vinp Voutn Voutp -*.PININFO Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_gain_boosting -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_gain_boosting Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Vbiasp:O Voutn:O Voutp:O -MM8 Voutn net22 net23 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp net19 net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net23 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net21 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn net24 net25 vdd pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net20 net12 vdd pmos_rvt w=WA l=LA nfin=nA -MM1 net25 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -XI3 net12 net25 net24 net20 / fully_differential -XI1 net23 net21 net19 net22 / fully_differential -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR3_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 net15 gnd! res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_gain_boosting -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR3_2 Biasn Vbiasp CR3_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_nmos_l1_cr4_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_nmos_l1_cr4_2.sp deleted file mode 100644 index 5d88858b21..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_nmos_l1_cr4_2.sp +++ /dev/null @@ -1,90 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_gain_boosting -* View Name: schematic -* Netlisted on: Sep 11 21:05:36 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vinn Vinp Voutn Voutp -*.PININFO Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_gain_boosting -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_gain_boosting Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Vbiasp:O Voutn:O Voutp:O -MM8 Voutn net22 net23 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp net19 net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net23 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net21 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn net24 net25 vdd pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net20 net12 vdd pmos_rvt w=WA l=LA nfin=nA -MM1 net25 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -XI3 net12 net25 net24 net20 / fully_differential -XI1 net23 net21 net19 net22 / fully_differential -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR4_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM11 net023 net024 Vbiasn gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM8 net025 net010 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM9 net024 net024 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM7 net010 net010 net025 gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net025 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 net024 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net010 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_gain_boosting -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR4_2 Biasn Vbiasp CR4_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_nmos_l1_cr5_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_nmos_l1_cr5_2.sp deleted file mode 100644 index 046e4f9cf7..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_nmos_l1_cr5_2.sp +++ /dev/null @@ -1,87 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_gain_boosting -* View Name: schematic -* Netlisted on: Sep 11 21:05:36 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vinn Vinp Voutn Voutp -*.PININFO Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_gain_boosting -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_gain_boosting Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Vbiasp:O Voutn:O Voutp:O -MM8 Voutn net22 net23 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp net19 net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net23 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net21 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn net24 net25 vdd pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net20 net12 vdd pmos_rvt w=WA l=LA nfin=nA -MM1 net25 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -XI3 net12 net25 net24 net20 / fully_differential -XI1 net23 net21 net19 net22 / fully_differential -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR5_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM5 net014 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net014 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_gain_boosting -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR5_2 Biasn Vbiasp CR5_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_nmos_l1_cr7_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_nmos_l1_cr7_1.sp deleted file mode 100644 index f1ff4352db..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_nmos_l1_cr7_1.sp +++ /dev/null @@ -1,85 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_gain_boosting -* View Name: schematic -* Netlisted on: Sep 11 21:05:36 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vinn Vinp Voutn Voutp -*.PININFO Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_gain_boosting -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_gain_boosting Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Vbiasp:O Voutn:O Voutp:O -MM8 Voutn net22 net23 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp net19 net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net23 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net21 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn net24 net25 vdd pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net20 net12 vdd pmos_rvt w=WA l=LA nfin=nA -MM1 net25 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -XI3 net12 net25 net24 net20 / fully_differential -XI1 net23 net21 net19 net22 / fully_differential -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR7_1 Vbiasn -*.PININFO Vbiasn:O -RR1 Vbiasn net7 res=rK -RR0 vdd! net7 res=rK -RRF vdd! Vbiasn res=rK -MM1 net7 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_gain_boosting -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR7_1 Biasn CR7_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_nmos_l1_cr9_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_nmos_l1_cr9_1.sp deleted file mode 100644 index 2f7ec11ad8..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_nmos_l1_cr9_1.sp +++ /dev/null @@ -1,83 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_gain_boosting -* View Name: schematic -* Netlisted on: Sep 11 21:05:36 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vinn Vinp Voutn Voutp -*.PININFO Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_gain_boosting -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_gain_boosting Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Vbiasp:O Voutn:O Voutp:O -MM8 Voutn net22 net23 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp net19 net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net23 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net21 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn net24 net25 vdd pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net20 net12 vdd pmos_rvt w=WA l=LA nfin=nA -MM1 net25 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -XI3 net12 net25 net24 net20 / fully_differential -XI1 net23 net21 net19 net22 / fully_differential -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR9_1 Vbiasn -*.PININFO Vbiasn:O -RR1 net05 gnd! res=rK -RRF vdd! Vbiasn res=rK -MM0 Vbiasn Vbiasn net05 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_gain_boosting -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR9_1 Biasn CR9_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_npmos_cr11_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_npmos_cr11_1.sp deleted file mode 100644 index 56057a744e..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_npmos_cr11_1.sp +++ /dev/null @@ -1,87 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_gain_boosting -* View Name: schematic -* Netlisted on: Sep 11 21:05:36 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vinn Vinp Voutn Voutp -*.PININFO Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_gain_boosting -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_gain_boosting Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Vbiasp:O Voutn:O Voutp:O -MM8 Voutn net22 net23 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp net19 net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net23 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net21 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn net24 net25 vdd pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net20 net12 vdd pmos_rvt w=WA l=LA nfin=nA -MM1 net25 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -XI3 net12 net25 net24 net20 / fully_differential -XI1 net23 net21 net19 net22 / fully_differential -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR11_1 Vbiasn -*.PININFO Vbiasn:O -RRF vdd! Vbiasn res=rK -MM1 net9 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net9 net9 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn net9 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_gain_boosting -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR11_1 Biasn CR11_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_npmos_cr12_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_npmos_cr12_1.sp deleted file mode 100644 index c7e5c60a57..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_npmos_cr12_1.sp +++ /dev/null @@ -1,87 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_gain_boosting -* View Name: schematic -* Netlisted on: Sep 11 21:05:36 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vinn Vinp Voutn Voutp -*.PININFO Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_gain_boosting -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_gain_boosting Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Vbiasp:O Voutn:O Voutp:O -MM8 Voutn net22 net23 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp net19 net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net23 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net21 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn net24 net25 vdd pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net20 net12 vdd pmos_rvt w=WA l=LA nfin=nA -MM1 net25 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -XI3 net12 net25 net24 net20 / fully_differential -XI1 net23 net21 net19 net22 / fully_differential -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR12_1 Vbiasn -*.PININFO Vbiasn:O -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 net10 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn net10 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RRF vdd! Vbiasn res=rK -RR0 vdd! net10 res=rK -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_gain_boosting -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR12_1 Biasn CR12_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_npmos_cr13_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_npmos_cr13_1.sp deleted file mode 100644 index dd4808608e..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_npmos_cr13_1.sp +++ /dev/null @@ -1,86 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_gain_boosting -* View Name: schematic -* Netlisted on: Sep 11 21:05:36 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vinn Vinp Voutn Voutp -*.PININFO Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_gain_boosting -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_gain_boosting Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Vbiasp:O Voutn:O Voutp:O -MM8 Voutn net22 net23 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp net19 net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net23 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net21 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn net24 net25 vdd pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net20 net12 vdd pmos_rvt w=WA l=LA nfin=nA -MM1 net25 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -XI3 net12 net25 net24 net20 / fully_differential -XI1 net23 net21 net19 net22 / fully_differential -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_gain_boosting -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR13_2 Biasn Vbiasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_npmos_cr13_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_npmos_cr13_2.sp deleted file mode 100644 index dd4808608e..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_npmos_cr13_2.sp +++ /dev/null @@ -1,86 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_gain_boosting -* View Name: schematic -* Netlisted on: Sep 11 21:05:36 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vinn Vinp Voutn Voutp -*.PININFO Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_gain_boosting -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_gain_boosting Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Vbiasp:O Voutn:O Voutp:O -MM8 Voutn net22 net23 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp net19 net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net23 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net21 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn net24 net25 vdd pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net20 net12 vdd pmos_rvt w=WA l=LA nfin=nA -MM1 net25 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -XI3 net12 net25 net24 net20 / fully_differential -XI1 net23 net21 net19 net22 / fully_differential -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_gain_boosting -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR13_2 Biasn Vbiasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_npmos_cr14_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_npmos_cr14_2.sp deleted file mode 100644 index b9876dd5cd..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_npmos_cr14_2.sp +++ /dev/null @@ -1,87 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_gain_boosting -* View Name: schematic -* Netlisted on: Sep 11 21:05:36 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vinn Vinp Voutn Voutp -*.PININFO Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_gain_boosting -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_gain_boosting Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Vbiasp:O Voutn:O Voutp:O -MM8 Voutn net22 net23 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp net19 net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net23 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net21 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn net24 net25 vdd pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net20 net12 vdd pmos_rvt w=WA l=LA nfin=nA -MM1 net25 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -XI3 net12 net25 net24 net20 / fully_differential -XI1 net23 net21 net19 net22 / fully_differential -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR14_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net010 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 Vbiasn net010 res=rK -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_gain_boosting -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR14_2 Biasn Vbiasp CR14_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_npmos_cr1_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_npmos_cr1_1.sp deleted file mode 100644 index 67e80d08f4..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_npmos_cr1_1.sp +++ /dev/null @@ -1,84 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_gain_boosting -* View Name: schematic -* Netlisted on: Sep 11 21:05:36 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vinn Vinp Voutn Voutp -*.PININFO Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_gain_boosting -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_gain_boosting Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Vbiasp:O Voutn:O Voutp:O -MM8 Voutn net22 net23 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp net19 net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net23 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net21 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn net24 net25 vdd pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net20 net12 vdd pmos_rvt w=WA l=LA nfin=nA -MM1 net25 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -XI3 net12 net25 net24 net20 / fully_differential -XI1 net23 net21 net19 net22 / fully_differential -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR1_1 Vbiasn -*.PININFO Vbiasn:O -RRF vdd! Vbiasn res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_gain_boosting -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR1_1 Biasn CR1_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_npmos_cr2_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_npmos_cr2_2.sp deleted file mode 100644 index b828abdd3b..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_npmos_cr2_2.sp +++ /dev/null @@ -1,87 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_gain_boosting -* View Name: schematic -* Netlisted on: Sep 11 21:05:36 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vinn Vinp Voutn Voutp -*.PININFO Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_gain_boosting -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_gain_boosting Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Vbiasp:O Voutn:O Voutp:O -MM8 Voutn net22 net23 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp net19 net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net23 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net21 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn net24 net25 vdd pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net20 net12 vdd pmos_rvt w=WA l=LA nfin=nA -MM1 net25 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -XI3 net12 net25 net24 net20 / fully_differential -XI1 net23 net21 net19 net22 / fully_differential -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR2_2_wilson Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -RR0 Vbiasn gnd! res=rK -MM2 Vbiasp net12 Vbiasn gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_gain_boosting -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR2_2_wilson Biasn Vbiasp CR2_2_wilson -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_npmos_cr3_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_npmos_cr3_2.sp deleted file mode 100644 index 33d1cba496..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_npmos_cr3_2.sp +++ /dev/null @@ -1,87 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_gain_boosting -* View Name: schematic -* Netlisted on: Sep 11 21:05:36 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vinn Vinp Voutn Voutp -*.PININFO Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_gain_boosting -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_gain_boosting Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Vbiasp:O Voutn:O Voutp:O -MM8 Voutn net22 net23 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp net19 net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net23 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net21 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn net24 net25 vdd pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net20 net12 vdd pmos_rvt w=WA l=LA nfin=nA -MM1 net25 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -XI3 net12 net25 net24 net20 / fully_differential -XI1 net23 net21 net19 net22 / fully_differential -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR3_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 net15 gnd! res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_gain_boosting -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR3_2 Biasn Vbiasp CR3_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_npmos_cr4_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_npmos_cr4_2.sp deleted file mode 100644 index 0478be4fde..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_npmos_cr4_2.sp +++ /dev/null @@ -1,92 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_gain_boosting -* View Name: schematic -* Netlisted on: Sep 11 21:05:36 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vinn Vinp Voutn Voutp -*.PININFO Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_gain_boosting -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_gain_boosting Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Vbiasp:O Voutn:O Voutp:O -MM8 Voutn net22 net23 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp net19 net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net23 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net21 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn net24 net25 vdd pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net20 net12 vdd pmos_rvt w=WA l=LA nfin=nA -MM1 net25 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -XI3 net12 net25 net24 net20 / fully_differential -XI1 net23 net21 net19 net22 / fully_differential -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR4_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM11 net023 net024 Vbiasn gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM8 net025 net010 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM9 net024 net024 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM7 net010 net010 net025 gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net025 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 net024 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net010 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_gain_boosting -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR4_2 Biasn Vbiasp CR4_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_npmos_cr5_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_npmos_cr5_2.sp deleted file mode 100644 index a9ebf76ec6..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_npmos_cr5_2.sp +++ /dev/null @@ -1,89 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_gain_boosting -* View Name: schematic -* Netlisted on: Sep 11 21:05:36 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vinn Vinp Voutn Voutp -*.PININFO Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_gain_boosting -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_gain_boosting Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Vbiasp:O Voutn:O Voutp:O -MM8 Voutn net22 net23 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp net19 net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net23 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net21 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn net24 net25 vdd pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net20 net12 vdd pmos_rvt w=WA l=LA nfin=nA -MM1 net25 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -XI3 net12 net25 net24 net20 / fully_differential -XI1 net23 net21 net19 net22 / fully_differential -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR5_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM5 net014 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net014 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_gain_boosting -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR5_2 Biasn Vbiasp CR5_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_npmos_cr7_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_npmos_cr7_1.sp deleted file mode 100644 index d77ef6191a..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_npmos_cr7_1.sp +++ /dev/null @@ -1,87 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_gain_boosting -* View Name: schematic -* Netlisted on: Sep 11 21:05:36 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vinn Vinp Voutn Voutp -*.PININFO Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_gain_boosting -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_gain_boosting Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Vbiasp:O Voutn:O Voutp:O -MM8 Voutn net22 net23 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp net19 net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net23 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net21 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn net24 net25 vdd pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net20 net12 vdd pmos_rvt w=WA l=LA nfin=nA -MM1 net25 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -XI3 net12 net25 net24 net20 / fully_differential -XI1 net23 net21 net19 net22 / fully_differential -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR7_1 Vbiasn -*.PININFO Vbiasn:O -RR1 Vbiasn net7 res=rK -RR0 vdd! net7 res=rK -RRF vdd! Vbiasn res=rK -MM1 net7 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_gain_boosting -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR7_1 Biasn CR7_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_npmos_cr9_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_npmos_cr9_1.sp deleted file mode 100644 index bd10ddeca5..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_npmos_cr9_1.sp +++ /dev/null @@ -1,85 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_gain_boosting -* View Name: schematic -* Netlisted on: Sep 11 21:05:36 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vinn Vinp Voutn Voutp -*.PININFO Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_gain_boosting -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_gain_boosting Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Vbiasp:O Voutn:O Voutp:O -MM8 Voutn net22 net23 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp net19 net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net23 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net21 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn net24 net25 vdd pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net20 net12 vdd pmos_rvt w=WA l=LA nfin=nA -MM1 net25 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -XI3 net12 net25 net24 net20 / fully_differential -XI1 net23 net21 net19 net22 / fully_differential -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR9_1 Vbiasn -*.PININFO Vbiasn:O -RR1 net05 gnd! res=rK -RRF vdd! Vbiasn res=rK -MM0 Vbiasn Vbiasn net05 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_gain_boosting -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR9_1 Biasn CR9_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pmos_cr11_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pmos_cr11_1.sp deleted file mode 100644 index 99e131ed5e..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pmos_cr11_1.sp +++ /dev/null @@ -1,83 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_gain_boosting -* View Name: schematic -* Netlisted on: Sep 11 21:05:36 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vinn Vinp Voutn Voutp -*.PININFO Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_gain_boosting -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_gain_boosting Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Vbiasp:O Voutn:O Voutp:O -MM8 Voutn net22 net23 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp net19 net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net23 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net21 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn net24 net25 vdd pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net20 net12 vdd pmos_rvt w=WA l=LA nfin=nA -MM1 net25 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -XI3 net12 net25 net24 net20 / fully_differential -XI1 net23 net21 net19 net22 / fully_differential -.ENDS - - -.SUBCKT LG_pmos Biasn Vbiasp -*.PININFO Biasn:I Vbiasp:O -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR11_1 Vbiasn -*.PININFO Vbiasn:O -RRF vdd! Vbiasn res=rK -MM1 net9 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net9 net9 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn net9 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_gain_boosting -xiLG_pmos Biasn LG_Vbiasp LG_pmos -xibCR11_1 Biasn CR11_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pmos_cr12_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pmos_cr12_1.sp deleted file mode 100644 index 4c162c2489..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pmos_cr12_1.sp +++ /dev/null @@ -1,83 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_gain_boosting -* View Name: schematic -* Netlisted on: Sep 11 21:05:36 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vinn Vinp Voutn Voutp -*.PININFO Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_gain_boosting -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_gain_boosting Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Vbiasp:O Voutn:O Voutp:O -MM8 Voutn net22 net23 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp net19 net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net23 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net21 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn net24 net25 vdd pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net20 net12 vdd pmos_rvt w=WA l=LA nfin=nA -MM1 net25 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -XI3 net12 net25 net24 net20 / fully_differential -XI1 net23 net21 net19 net22 / fully_differential -.ENDS - - -.SUBCKT LG_pmos Biasn Vbiasp -*.PININFO Biasn:I Vbiasp:O -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR12_1 Vbiasn -*.PININFO Vbiasn:O -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 net10 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn net10 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RRF vdd! Vbiasn res=rK -RR0 vdd! net10 res=rK -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_gain_boosting -xiLG_pmos Biasn LG_Vbiasp LG_pmos -xibCR12_1 Biasn CR12_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pmos_cr13_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pmos_cr13_1.sp deleted file mode 100644 index 1ba759d298..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pmos_cr13_1.sp +++ /dev/null @@ -1,82 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_gain_boosting -* View Name: schematic -* Netlisted on: Sep 11 21:05:36 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vinn Vinp Voutn Voutp -*.PININFO Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_gain_boosting -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_gain_boosting Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Vbiasp:O Voutn:O Voutp:O -MM8 Voutn net22 net23 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp net19 net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net23 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net21 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn net24 net25 vdd pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net20 net12 vdd pmos_rvt w=WA l=LA nfin=nA -MM1 net25 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -XI3 net12 net25 net24 net20 / fully_differential -XI1 net23 net21 net19 net22 / fully_differential -.ENDS - - -.SUBCKT LG_pmos Biasn Vbiasp -*.PININFO Biasn:I Vbiasp:O -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_gain_boosting -xiLG_pmos Biasn LG_Vbiasp LG_pmos -xibCR13_2 Biasn Vbiasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pmos_cr13_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pmos_cr13_2.sp deleted file mode 100644 index 1ba759d298..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pmos_cr13_2.sp +++ /dev/null @@ -1,82 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_gain_boosting -* View Name: schematic -* Netlisted on: Sep 11 21:05:36 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vinn Vinp Voutn Voutp -*.PININFO Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_gain_boosting -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_gain_boosting Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Vbiasp:O Voutn:O Voutp:O -MM8 Voutn net22 net23 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp net19 net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net23 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net21 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn net24 net25 vdd pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net20 net12 vdd pmos_rvt w=WA l=LA nfin=nA -MM1 net25 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -XI3 net12 net25 net24 net20 / fully_differential -XI1 net23 net21 net19 net22 / fully_differential -.ENDS - - -.SUBCKT LG_pmos Biasn Vbiasp -*.PININFO Biasn:I Vbiasp:O -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_gain_boosting -xiLG_pmos Biasn LG_Vbiasp LG_pmos -xibCR13_2 Biasn Vbiasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pmos_cr14_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pmos_cr14_2.sp deleted file mode 100644 index adbfb7a4af..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pmos_cr14_2.sp +++ /dev/null @@ -1,83 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_gain_boosting -* View Name: schematic -* Netlisted on: Sep 11 21:05:36 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vinn Vinp Voutn Voutp -*.PININFO Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_gain_boosting -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_gain_boosting Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Vbiasp:O Voutn:O Voutp:O -MM8 Voutn net22 net23 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp net19 net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net23 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net21 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn net24 net25 vdd pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net20 net12 vdd pmos_rvt w=WA l=LA nfin=nA -MM1 net25 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -XI3 net12 net25 net24 net20 / fully_differential -XI1 net23 net21 net19 net22 / fully_differential -.ENDS - - -.SUBCKT LG_pmos Biasn Vbiasp -*.PININFO Biasn:I Vbiasp:O -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR14_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net010 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 Vbiasn net010 res=rK -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_gain_boosting -xiLG_pmos Biasn LG_Vbiasp LG_pmos -xibCR14_2 Biasn Vbiasp CR14_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pmos_cr1_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pmos_cr1_1.sp deleted file mode 100644 index 5d7532423f..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pmos_cr1_1.sp +++ /dev/null @@ -1,80 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_gain_boosting -* View Name: schematic -* Netlisted on: Sep 11 21:05:36 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vinn Vinp Voutn Voutp -*.PININFO Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_gain_boosting -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_gain_boosting Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Vbiasp:O Voutn:O Voutp:O -MM8 Voutn net22 net23 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp net19 net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net23 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net21 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn net24 net25 vdd pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net20 net12 vdd pmos_rvt w=WA l=LA nfin=nA -MM1 net25 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -XI3 net12 net25 net24 net20 / fully_differential -XI1 net23 net21 net19 net22 / fully_differential -.ENDS - - -.SUBCKT LG_pmos Biasn Vbiasp -*.PININFO Biasn:I Vbiasp:O -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR1_1 Vbiasn -*.PININFO Vbiasn:O -RRF vdd! Vbiasn res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_gain_boosting -xiLG_pmos Biasn LG_Vbiasp LG_pmos -xibCR1_1 Biasn CR1_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pmos_cr2_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pmos_cr2_2.sp deleted file mode 100644 index 6c04cea2c1..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pmos_cr2_2.sp +++ /dev/null @@ -1,83 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_gain_boosting -* View Name: schematic -* Netlisted on: Sep 11 21:05:36 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vinn Vinp Voutn Voutp -*.PININFO Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_gain_boosting -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_gain_boosting Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Vbiasp:O Voutn:O Voutp:O -MM8 Voutn net22 net23 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp net19 net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net23 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net21 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn net24 net25 vdd pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net20 net12 vdd pmos_rvt w=WA l=LA nfin=nA -MM1 net25 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -XI3 net12 net25 net24 net20 / fully_differential -XI1 net23 net21 net19 net22 / fully_differential -.ENDS - - -.SUBCKT LG_pmos Biasn Vbiasp -*.PININFO Biasn:I Vbiasp:O -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR2_2_wilson Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -RR0 Vbiasn gnd! res=rK -MM2 Vbiasp net12 Vbiasn gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_gain_boosting -xiLG_pmos Biasn LG_Vbiasp LG_pmos -xibCR2_2_wilson Biasn Vbiasp CR2_2_wilson -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pmos_cr3_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pmos_cr3_2.sp deleted file mode 100644 index 51446d6ad9..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pmos_cr3_2.sp +++ /dev/null @@ -1,83 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_gain_boosting -* View Name: schematic -* Netlisted on: Sep 11 21:05:36 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vinn Vinp Voutn Voutp -*.PININFO Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_gain_boosting -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_gain_boosting Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Vbiasp:O Voutn:O Voutp:O -MM8 Voutn net22 net23 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp net19 net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net23 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net21 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn net24 net25 vdd pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net20 net12 vdd pmos_rvt w=WA l=LA nfin=nA -MM1 net25 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -XI3 net12 net25 net24 net20 / fully_differential -XI1 net23 net21 net19 net22 / fully_differential -.ENDS - - -.SUBCKT LG_pmos Biasn Vbiasp -*.PININFO Biasn:I Vbiasp:O -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR3_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 net15 gnd! res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_gain_boosting -xiLG_pmos Biasn LG_Vbiasp LG_pmos -xibCR3_2 Biasn Vbiasp CR3_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pmos_cr4_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pmos_cr4_2.sp deleted file mode 100644 index b03dd8ab54..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pmos_cr4_2.sp +++ /dev/null @@ -1,88 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_gain_boosting -* View Name: schematic -* Netlisted on: Sep 11 21:05:36 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vinn Vinp Voutn Voutp -*.PININFO Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_gain_boosting -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_gain_boosting Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Vbiasp:O Voutn:O Voutp:O -MM8 Voutn net22 net23 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp net19 net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net23 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net21 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn net24 net25 vdd pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net20 net12 vdd pmos_rvt w=WA l=LA nfin=nA -MM1 net25 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -XI3 net12 net25 net24 net20 / fully_differential -XI1 net23 net21 net19 net22 / fully_differential -.ENDS - - -.SUBCKT LG_pmos Biasn Vbiasp -*.PININFO Biasn:I Vbiasp:O -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR4_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM11 net023 net024 Vbiasn gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM8 net025 net010 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM9 net024 net024 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM7 net010 net010 net025 gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net025 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 net024 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net010 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_gain_boosting -xiLG_pmos Biasn LG_Vbiasp LG_pmos -xibCR4_2 Biasn Vbiasp CR4_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pmos_cr5_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pmos_cr5_2.sp deleted file mode 100644 index b5a7f44f22..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pmos_cr5_2.sp +++ /dev/null @@ -1,85 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_gain_boosting -* View Name: schematic -* Netlisted on: Sep 11 21:05:36 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vinn Vinp Voutn Voutp -*.PININFO Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_gain_boosting -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_gain_boosting Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Vbiasp:O Voutn:O Voutp:O -MM8 Voutn net22 net23 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp net19 net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net23 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net21 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn net24 net25 vdd pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net20 net12 vdd pmos_rvt w=WA l=LA nfin=nA -MM1 net25 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -XI3 net12 net25 net24 net20 / fully_differential -XI1 net23 net21 net19 net22 / fully_differential -.ENDS - - -.SUBCKT LG_pmos Biasn Vbiasp -*.PININFO Biasn:I Vbiasp:O -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR5_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM5 net014 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net014 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_gain_boosting -xiLG_pmos Biasn LG_Vbiasp LG_pmos -xibCR5_2 Biasn Vbiasp CR5_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pmos_cr7_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pmos_cr7_1.sp deleted file mode 100644 index bae815df8b..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pmos_cr7_1.sp +++ /dev/null @@ -1,83 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_gain_boosting -* View Name: schematic -* Netlisted on: Sep 11 21:05:36 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vinn Vinp Voutn Voutp -*.PININFO Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_gain_boosting -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_gain_boosting Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Vbiasp:O Voutn:O Voutp:O -MM8 Voutn net22 net23 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp net19 net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net23 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net21 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn net24 net25 vdd pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net20 net12 vdd pmos_rvt w=WA l=LA nfin=nA -MM1 net25 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -XI3 net12 net25 net24 net20 / fully_differential -XI1 net23 net21 net19 net22 / fully_differential -.ENDS - - -.SUBCKT LG_pmos Biasn Vbiasp -*.PININFO Biasn:I Vbiasp:O -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR7_1 Vbiasn -*.PININFO Vbiasn:O -RR1 Vbiasn net7 res=rK -RR0 vdd! net7 res=rK -RRF vdd! Vbiasn res=rK -MM1 net7 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_gain_boosting -xiLG_pmos Biasn LG_Vbiasp LG_pmos -xibCR7_1 Biasn CR7_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pmos_cr9_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pmos_cr9_1.sp deleted file mode 100644 index e3bf124230..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pmos_cr9_1.sp +++ /dev/null @@ -1,81 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_gain_boosting -* View Name: schematic -* Netlisted on: Sep 11 21:05:36 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vinn Vinp Voutn Voutp -*.PININFO Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_gain_boosting -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_gain_boosting Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Vbiasp:O Voutn:O Voutp:O -MM8 Voutn net22 net23 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp net19 net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net23 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net21 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn net24 net25 vdd pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net20 net12 vdd pmos_rvt w=WA l=LA nfin=nA -MM1 net25 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -XI3 net12 net25 net24 net20 / fully_differential -XI1 net23 net21 net19 net22 / fully_differential -.ENDS - - -.SUBCKT LG_pmos Biasn Vbiasp -*.PININFO Biasn:I Vbiasp:O -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR9_1 Vbiasn -*.PININFO Vbiasn:O -RR1 net05 gnd! res=rK -RRF vdd! Vbiasn res=rK -MM0 Vbiasn Vbiasn net05 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_gain_boosting -xiLG_pmos Biasn LG_Vbiasp LG_pmos -xibCR9_1 Biasn CR9_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pmos_l1_cr13_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pmos_l1_cr13_1.sp deleted file mode 100644 index c0626feedf..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pmos_l1_cr13_1.sp +++ /dev/null @@ -1,84 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_gain_boosting -* View Name: schematic -* Netlisted on: Sep 11 21:05:36 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vinn Vinp Voutn Voutp -*.PININFO Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_gain_boosting -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_gain_boosting Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Vbiasp:O Voutn:O Voutp:O -MM8 Voutn net22 net23 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp net19 net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net23 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net21 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn net24 net25 vdd pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net20 net12 vdd pmos_rvt w=WA l=LA nfin=nA -MM1 net25 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -XI3 net12 net25 net24 net20 / fully_differential -XI1 net23 net21 net19 net22 / fully_differential -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_gain_boosting -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR13_2 Biasn Biasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pmos_l1_cr13_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pmos_l1_cr13_2.sp deleted file mode 100644 index c0626feedf..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pmos_l1_cr13_2.sp +++ /dev/null @@ -1,84 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_gain_boosting -* View Name: schematic -* Netlisted on: Sep 11 21:05:36 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vinn Vinp Voutn Voutp -*.PININFO Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_gain_boosting -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_gain_boosting Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Vbiasp:O Voutn:O Voutp:O -MM8 Voutn net22 net23 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp net19 net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net23 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net21 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn net24 net25 vdd pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net20 net12 vdd pmos_rvt w=WA l=LA nfin=nA -MM1 net25 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -XI3 net12 net25 net24 net20 / fully_differential -XI1 net23 net21 net19 net22 / fully_differential -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_gain_boosting -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR13_2 Biasn Biasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pmos_l1_cr14_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pmos_l1_cr14_2.sp deleted file mode 100644 index 332c96b8f4..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pmos_l1_cr14_2.sp +++ /dev/null @@ -1,85 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_gain_boosting -* View Name: schematic -* Netlisted on: Sep 11 21:05:36 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vinn Vinp Voutn Voutp -*.PININFO Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_gain_boosting -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_gain_boosting Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Vbiasp:O Voutn:O Voutp:O -MM8 Voutn net22 net23 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp net19 net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net23 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net21 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn net24 net25 vdd pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net20 net12 vdd pmos_rvt w=WA l=LA nfin=nA -MM1 net25 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -XI3 net12 net25 net24 net20 / fully_differential -XI1 net23 net21 net19 net22 / fully_differential -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR14_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net010 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 Vbiasn net010 res=rK -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_gain_boosting -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR14_2 Biasn Biasp CR14_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pmos_l1_cr15_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pmos_l1_cr15_1.sp deleted file mode 100644 index d0f75328bf..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pmos_l1_cr15_1.sp +++ /dev/null @@ -1,82 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_gain_boosting -* View Name: schematic -* Netlisted on: Sep 11 21:05:36 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vinn Vinp Voutn Voutp -*.PININFO Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_gain_boosting -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_gain_boosting Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Vbiasp:O Voutn:O Voutp:O -MM8 Voutn net22 net23 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp net19 net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net23 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net21 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn net24 net25 vdd pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net20 net12 vdd pmos_rvt w=WA l=LA nfin=nA -MM1 net25 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -XI3 net12 net25 net24 net20 / fully_differential -XI1 net23 net21 net19 net22 / fully_differential -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR15_1 Vbiasp -*.PININFO Vbiasp:O -RR1 Vbiasp gnd! res=rK -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_gain_boosting -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR15_1 Biasp CR15_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pmos_l1_cr16_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pmos_l1_cr16_1.sp deleted file mode 100644 index 7b3805f2f8..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pmos_l1_cr16_1.sp +++ /dev/null @@ -1,83 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_gain_boosting -* View Name: schematic -* Netlisted on: Sep 11 21:05:36 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vinn Vinp Voutn Voutp -*.PININFO Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_gain_boosting -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_gain_boosting Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Vbiasp:O Voutn:O Voutp:O -MM8 Voutn net22 net23 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp net19 net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net23 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net21 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn net24 net25 vdd pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net20 net12 vdd pmos_rvt w=WA l=LA nfin=nA -MM1 net25 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -XI3 net12 net25 net24 net20 / fully_differential -XI1 net23 net21 net19 net22 / fully_differential -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR16_1 Vbiasp -*.PININFO Vbiasp:O -RR0 vdd! net6 res=rK -RR1 Vbiasp gnd! res=rK -MM2 Vbiasp Vbiasp net6 vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_gain_boosting -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR16_1 Biasp CR16_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pmos_l1_cr2_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pmos_l1_cr2_2.sp deleted file mode 100644 index d6cc9083f2..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pmos_l1_cr2_2.sp +++ /dev/null @@ -1,85 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_gain_boosting -* View Name: schematic -* Netlisted on: Sep 11 21:05:36 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vinn Vinp Voutn Voutp -*.PININFO Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_gain_boosting -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_gain_boosting Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Vbiasp:O Voutn:O Voutp:O -MM8 Voutn net22 net23 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp net19 net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net23 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net21 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn net24 net25 vdd pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net20 net12 vdd pmos_rvt w=WA l=LA nfin=nA -MM1 net25 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -XI3 net12 net25 net24 net20 / fully_differential -XI1 net23 net21 net19 net22 / fully_differential -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR2_2_wilson Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -RR0 Vbiasn gnd! res=rK -MM2 Vbiasp net12 Vbiasn gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_gain_boosting -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR2_2_wilson Biasn Biasp CR2_2_wilson -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pmos_l1_cr3_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pmos_l1_cr3_2.sp deleted file mode 100644 index 9be1f398cd..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pmos_l1_cr3_2.sp +++ /dev/null @@ -1,85 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_gain_boosting -* View Name: schematic -* Netlisted on: Sep 11 21:05:36 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vinn Vinp Voutn Voutp -*.PININFO Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_gain_boosting -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_gain_boosting Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Vbiasp:O Voutn:O Voutp:O -MM8 Voutn net22 net23 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp net19 net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net23 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net21 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn net24 net25 vdd pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net20 net12 vdd pmos_rvt w=WA l=LA nfin=nA -MM1 net25 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -XI3 net12 net25 net24 net20 / fully_differential -XI1 net23 net21 net19 net22 / fully_differential -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR3_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 net15 gnd! res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_gain_boosting -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR3_2 Biasn Biasp CR3_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pmos_l1_cr4_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pmos_l1_cr4_2.sp deleted file mode 100644 index 7aec2ea705..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pmos_l1_cr4_2.sp +++ /dev/null @@ -1,90 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_gain_boosting -* View Name: schematic -* Netlisted on: Sep 11 21:05:36 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vinn Vinp Voutn Voutp -*.PININFO Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_gain_boosting -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_gain_boosting Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Vbiasp:O Voutn:O Voutp:O -MM8 Voutn net22 net23 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp net19 net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net23 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net21 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn net24 net25 vdd pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net20 net12 vdd pmos_rvt w=WA l=LA nfin=nA -MM1 net25 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -XI3 net12 net25 net24 net20 / fully_differential -XI1 net23 net21 net19 net22 / fully_differential -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR4_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM11 net023 net024 Vbiasn gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM8 net025 net010 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM9 net024 net024 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM7 net010 net010 net025 gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net025 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 net024 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net010 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_gain_boosting -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR4_2 Biasn Biasp CR4_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pmos_l1_cr5_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pmos_l1_cr5_2.sp deleted file mode 100644 index 6f7d365fac..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pmos_l1_cr5_2.sp +++ /dev/null @@ -1,87 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_gain_boosting -* View Name: schematic -* Netlisted on: Sep 11 21:05:36 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vinn Vinp Voutn Voutp -*.PININFO Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_gain_boosting -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_gain_boosting Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Vbiasp:O Voutn:O Voutp:O -MM8 Voutn net22 net23 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp net19 net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net23 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net21 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn net24 net25 vdd pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net20 net12 vdd pmos_rvt w=WA l=LA nfin=nA -MM1 net25 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -XI3 net12 net25 net24 net20 / fully_differential -XI1 net23 net21 net19 net22 / fully_differential -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR5_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM5 net014 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net014 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_gain_boosting -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR5_2 Biasn Biasp CR5_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pmos_l1_cr6_3.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pmos_l1_cr6_3.sp deleted file mode 100644 index 534e0618ff..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pmos_l1_cr6_3.sp +++ /dev/null @@ -1,87 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_gain_boosting -* View Name: schematic -* Netlisted on: Sep 11 21:05:36 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vinn Vinp Voutn Voutp -*.PININFO Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_gain_boosting -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_gain_boosting Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Vbiasp:O Voutn:O Voutp:O -MM8 Voutn net22 net23 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp net19 net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net23 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net21 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn net24 net25 vdd pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net20 net12 vdd pmos_rvt w=WA l=LA nfin=nA -MM1 net25 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -XI3 net12 net25 net24 net20 / fully_differential -XI1 net23 net21 net19 net22 / fully_differential -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR6_3 Vbiasn1 Vbiasn2 Vbiasp -*.PININFO Vbiasn1:O Vbiasn2:O Vbiasp:O -MM2 Vbiasp Vbiasn2 Vbiasn1 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn2 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 Vbiasn1 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM5 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn2 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_gain_boosting -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR6_3 Biasn1 Biasn2 Biasp CR6_3 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pnmos_4_cr13_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pnmos_4_cr13_1.sp deleted file mode 100644 index 1654debd7d..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pnmos_4_cr13_1.sp +++ /dev/null @@ -1,86 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_gain_boosting -* View Name: schematic -* Netlisted on: Sep 11 21:05:36 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vinn Vinp Voutn Voutp -*.PININFO Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_gain_boosting -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_gain_boosting Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Vbiasp:O Voutn:O Voutp:O -MM8 Voutn net22 net23 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp net19 net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net23 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net21 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn net24 net25 vdd pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net20 net12 vdd pmos_rvt w=WA l=LA nfin=nA -MM1 net25 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -XI3 net12 net25 net24 net20 / fully_differential -XI1 net23 net21 net19 net22 / fully_differential -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_gain_boosting -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR13_2 Biasn Biasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pnmos_4_cr13_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pnmos_4_cr13_2.sp deleted file mode 100644 index 1654debd7d..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pnmos_4_cr13_2.sp +++ /dev/null @@ -1,86 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_gain_boosting -* View Name: schematic -* Netlisted on: Sep 11 21:05:36 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vinn Vinp Voutn Voutp -*.PININFO Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_gain_boosting -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_gain_boosting Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Vbiasp:O Voutn:O Voutp:O -MM8 Voutn net22 net23 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp net19 net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net23 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net21 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn net24 net25 vdd pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net20 net12 vdd pmos_rvt w=WA l=LA nfin=nA -MM1 net25 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -XI3 net12 net25 net24 net20 / fully_differential -XI1 net23 net21 net19 net22 / fully_differential -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_gain_boosting -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR13_2 Biasn Biasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pnmos_4_cr14_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pnmos_4_cr14_2.sp deleted file mode 100644 index 0df88c900f..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pnmos_4_cr14_2.sp +++ /dev/null @@ -1,87 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_gain_boosting -* View Name: schematic -* Netlisted on: Sep 11 21:05:36 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vinn Vinp Voutn Voutp -*.PININFO Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_gain_boosting -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_gain_boosting Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Vbiasp:O Voutn:O Voutp:O -MM8 Voutn net22 net23 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp net19 net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net23 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net21 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn net24 net25 vdd pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net20 net12 vdd pmos_rvt w=WA l=LA nfin=nA -MM1 net25 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -XI3 net12 net25 net24 net20 / fully_differential -XI1 net23 net21 net19 net22 / fully_differential -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR14_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net010 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 Vbiasn net010 res=rK -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_gain_boosting -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR14_2 Biasn Biasp CR14_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pnmos_4_cr15_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pnmos_4_cr15_1.sp deleted file mode 100644 index 85f545aeef..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pnmos_4_cr15_1.sp +++ /dev/null @@ -1,84 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_gain_boosting -* View Name: schematic -* Netlisted on: Sep 11 21:05:36 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vinn Vinp Voutn Voutp -*.PININFO Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_gain_boosting -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_gain_boosting Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Vbiasp:O Voutn:O Voutp:O -MM8 Voutn net22 net23 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp net19 net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net23 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net21 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn net24 net25 vdd pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net20 net12 vdd pmos_rvt w=WA l=LA nfin=nA -MM1 net25 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -XI3 net12 net25 net24 net20 / fully_differential -XI1 net23 net21 net19 net22 / fully_differential -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR15_1 Vbiasp -*.PININFO Vbiasp:O -RR1 Vbiasp gnd! res=rK -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_gain_boosting -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR15_1 Biasp CR15_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pnmos_4_cr16_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pnmos_4_cr16_1.sp deleted file mode 100644 index 374bb89730..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pnmos_4_cr16_1.sp +++ /dev/null @@ -1,85 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_gain_boosting -* View Name: schematic -* Netlisted on: Sep 11 21:05:36 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vinn Vinp Voutn Voutp -*.PININFO Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_gain_boosting -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_gain_boosting Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Vbiasp:O Voutn:O Voutp:O -MM8 Voutn net22 net23 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp net19 net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net23 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net21 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn net24 net25 vdd pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net20 net12 vdd pmos_rvt w=WA l=LA nfin=nA -MM1 net25 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -XI3 net12 net25 net24 net20 / fully_differential -XI1 net23 net21 net19 net22 / fully_differential -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR16_1 Vbiasp -*.PININFO Vbiasp:O -RR0 vdd! net6 res=rK -RR1 Vbiasp gnd! res=rK -MM2 Vbiasp Vbiasp net6 vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_gain_boosting -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR16_1 Biasp CR16_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pnmos_4_cr2_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pnmos_4_cr2_2.sp deleted file mode 100644 index f8ed0f2664..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pnmos_4_cr2_2.sp +++ /dev/null @@ -1,87 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_gain_boosting -* View Name: schematic -* Netlisted on: Sep 11 21:05:36 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vinn Vinp Voutn Voutp -*.PININFO Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_gain_boosting -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_gain_boosting Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Vbiasp:O Voutn:O Voutp:O -MM8 Voutn net22 net23 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp net19 net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net23 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net21 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn net24 net25 vdd pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net20 net12 vdd pmos_rvt w=WA l=LA nfin=nA -MM1 net25 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -XI3 net12 net25 net24 net20 / fully_differential -XI1 net23 net21 net19 net22 / fully_differential -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR2_2_wilson Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -RR0 Vbiasn gnd! res=rK -MM2 Vbiasp net12 Vbiasn gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_gain_boosting -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR2_2_wilson Biasn Biasp CR2_2_wilson -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pnmos_4_cr3_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pnmos_4_cr3_2.sp deleted file mode 100644 index 2838769e57..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pnmos_4_cr3_2.sp +++ /dev/null @@ -1,87 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_gain_boosting -* View Name: schematic -* Netlisted on: Sep 11 21:05:36 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vinn Vinp Voutn Voutp -*.PININFO Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_gain_boosting -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_gain_boosting Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Vbiasp:O Voutn:O Voutp:O -MM8 Voutn net22 net23 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp net19 net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net23 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net21 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn net24 net25 vdd pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net20 net12 vdd pmos_rvt w=WA l=LA nfin=nA -MM1 net25 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -XI3 net12 net25 net24 net20 / fully_differential -XI1 net23 net21 net19 net22 / fully_differential -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR3_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 net15 gnd! res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_gain_boosting -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR3_2 Biasn Biasp CR3_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pnmos_4_cr4_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pnmos_4_cr4_2.sp deleted file mode 100644 index 21eb13cc1d..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pnmos_4_cr4_2.sp +++ /dev/null @@ -1,92 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_gain_boosting -* View Name: schematic -* Netlisted on: Sep 11 21:05:36 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vinn Vinp Voutn Voutp -*.PININFO Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_gain_boosting -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_gain_boosting Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Vbiasp:O Voutn:O Voutp:O -MM8 Voutn net22 net23 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp net19 net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net23 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net21 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn net24 net25 vdd pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net20 net12 vdd pmos_rvt w=WA l=LA nfin=nA -MM1 net25 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -XI3 net12 net25 net24 net20 / fully_differential -XI1 net23 net21 net19 net22 / fully_differential -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR4_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM11 net023 net024 Vbiasn gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM8 net025 net010 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM9 net024 net024 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM7 net010 net010 net025 gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net025 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 net024 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net010 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_gain_boosting -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR4_2 Biasn Biasp CR4_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pnmos_4_cr5_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pnmos_4_cr5_2.sp deleted file mode 100644 index 3c305f25a0..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pnmos_4_cr5_2.sp +++ /dev/null @@ -1,89 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_gain_boosting -* View Name: schematic -* Netlisted on: Sep 11 21:05:36 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vinn Vinp Voutn Voutp -*.PININFO Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_gain_boosting -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_gain_boosting Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Vbiasp:O Voutn:O Voutp:O -MM8 Voutn net22 net23 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp net19 net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net23 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net21 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn net24 net25 vdd pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net20 net12 vdd pmos_rvt w=WA l=LA nfin=nA -MM1 net25 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -XI3 net12 net25 net24 net20 / fully_differential -XI1 net23 net21 net19 net22 / fully_differential -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR5_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM5 net014 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net014 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_gain_boosting -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR5_2 Biasn Biasp CR5_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pnmos_4_cr6_3.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pnmos_4_cr6_3.sp deleted file mode 100644 index b5350ae384..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pnmos_4_cr6_3.sp +++ /dev/null @@ -1,89 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_gain_boosting -* View Name: schematic -* Netlisted on: Sep 11 21:05:36 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vinn Vinp Voutn Voutp -*.PININFO Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_gain_boosting -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_gain_boosting Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Vbiasp:O Voutn:O Voutp:O -MM8 Voutn net22 net23 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp net19 net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net23 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net21 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn net24 net25 vdd pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net20 net12 vdd pmos_rvt w=WA l=LA nfin=nA -MM1 net25 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -XI3 net12 net25 net24 net20 / fully_differential -XI1 net23 net21 net19 net22 / fully_differential -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR6_3 Vbiasn1 Vbiasn2 Vbiasp -*.PININFO Vbiasn1:O Vbiasn2:O Vbiasp:O -MM2 Vbiasp Vbiasn2 Vbiasn1 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn2 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 Vbiasn1 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM5 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn2 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_gain_boosting -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR6_3 Biasn1 Biasn2 Biasp CR6_3 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pnmos_cr13_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pnmos_cr13_1.sp deleted file mode 100644 index 5c6b28c18a..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pnmos_cr13_1.sp +++ /dev/null @@ -1,86 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_gain_boosting -* View Name: schematic -* Netlisted on: Sep 11 21:05:36 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vinn Vinp Voutn Voutp -*.PININFO Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_gain_boosting -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_gain_boosting Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Vbiasp:O Voutn:O Voutp:O -MM8 Voutn net22 net23 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp net19 net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net23 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net21 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn net24 net25 vdd pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net20 net12 vdd pmos_rvt w=WA l=LA nfin=nA -MM1 net25 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -XI3 net12 net25 net24 net20 / fully_differential -XI1 net23 net21 net19 net22 / fully_differential -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_gain_boosting -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR13_2 Biasn Biasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pnmos_cr13_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pnmos_cr13_2.sp deleted file mode 100644 index 5c6b28c18a..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pnmos_cr13_2.sp +++ /dev/null @@ -1,86 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_gain_boosting -* View Name: schematic -* Netlisted on: Sep 11 21:05:36 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vinn Vinp Voutn Voutp -*.PININFO Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_gain_boosting -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_gain_boosting Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Vbiasp:O Voutn:O Voutp:O -MM8 Voutn net22 net23 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp net19 net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net23 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net21 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn net24 net25 vdd pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net20 net12 vdd pmos_rvt w=WA l=LA nfin=nA -MM1 net25 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -XI3 net12 net25 net24 net20 / fully_differential -XI1 net23 net21 net19 net22 / fully_differential -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_gain_boosting -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR13_2 Biasn Biasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pnmos_cr14_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pnmos_cr14_2.sp deleted file mode 100644 index 99caba9232..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pnmos_cr14_2.sp +++ /dev/null @@ -1,87 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_gain_boosting -* View Name: schematic -* Netlisted on: Sep 11 21:05:36 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vinn Vinp Voutn Voutp -*.PININFO Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_gain_boosting -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_gain_boosting Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Vbiasp:O Voutn:O Voutp:O -MM8 Voutn net22 net23 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp net19 net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net23 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net21 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn net24 net25 vdd pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net20 net12 vdd pmos_rvt w=WA l=LA nfin=nA -MM1 net25 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -XI3 net12 net25 net24 net20 / fully_differential -XI1 net23 net21 net19 net22 / fully_differential -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR14_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net010 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 Vbiasn net010 res=rK -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_gain_boosting -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR14_2 Biasn Biasp CR14_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pnmos_cr15_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pnmos_cr15_1.sp deleted file mode 100644 index ce9d73988c..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pnmos_cr15_1.sp +++ /dev/null @@ -1,84 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_gain_boosting -* View Name: schematic -* Netlisted on: Sep 11 21:05:36 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vinn Vinp Voutn Voutp -*.PININFO Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_gain_boosting -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_gain_boosting Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Vbiasp:O Voutn:O Voutp:O -MM8 Voutn net22 net23 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp net19 net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net23 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net21 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn net24 net25 vdd pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net20 net12 vdd pmos_rvt w=WA l=LA nfin=nA -MM1 net25 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -XI3 net12 net25 net24 net20 / fully_differential -XI1 net23 net21 net19 net22 / fully_differential -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR15_1 Vbiasp -*.PININFO Vbiasp:O -RR1 Vbiasp gnd! res=rK -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_gain_boosting -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR15_1 Biasp CR15_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pnmos_cr16_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pnmos_cr16_1.sp deleted file mode 100644 index 2fa6b46e61..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pnmos_cr16_1.sp +++ /dev/null @@ -1,85 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_gain_boosting -* View Name: schematic -* Netlisted on: Sep 11 21:05:36 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vinn Vinp Voutn Voutp -*.PININFO Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_gain_boosting -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_gain_boosting Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Vbiasp:O Voutn:O Voutp:O -MM8 Voutn net22 net23 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp net19 net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net23 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net21 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn net24 net25 vdd pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net20 net12 vdd pmos_rvt w=WA l=LA nfin=nA -MM1 net25 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -XI3 net12 net25 net24 net20 / fully_differential -XI1 net23 net21 net19 net22 / fully_differential -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR16_1 Vbiasp -*.PININFO Vbiasp:O -RR0 vdd! net6 res=rK -RR1 Vbiasp gnd! res=rK -MM2 Vbiasp Vbiasp net6 vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_gain_boosting -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR16_1 Biasp CR16_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pnmos_cr2_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pnmos_cr2_2.sp deleted file mode 100644 index a49a64c434..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pnmos_cr2_2.sp +++ /dev/null @@ -1,87 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_gain_boosting -* View Name: schematic -* Netlisted on: Sep 11 21:05:36 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vinn Vinp Voutn Voutp -*.PININFO Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_gain_boosting -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_gain_boosting Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Vbiasp:O Voutn:O Voutp:O -MM8 Voutn net22 net23 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp net19 net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net23 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net21 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn net24 net25 vdd pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net20 net12 vdd pmos_rvt w=WA l=LA nfin=nA -MM1 net25 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -XI3 net12 net25 net24 net20 / fully_differential -XI1 net23 net21 net19 net22 / fully_differential -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR2_2_wilson Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -RR0 Vbiasn gnd! res=rK -MM2 Vbiasp net12 Vbiasn gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_gain_boosting -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR2_2_wilson Biasn Biasp CR2_2_wilson -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pnmos_cr3_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pnmos_cr3_2.sp deleted file mode 100644 index 1e076873fb..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pnmos_cr3_2.sp +++ /dev/null @@ -1,87 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_gain_boosting -* View Name: schematic -* Netlisted on: Sep 11 21:05:36 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vinn Vinp Voutn Voutp -*.PININFO Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_gain_boosting -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_gain_boosting Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Vbiasp:O Voutn:O Voutp:O -MM8 Voutn net22 net23 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp net19 net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net23 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net21 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn net24 net25 vdd pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net20 net12 vdd pmos_rvt w=WA l=LA nfin=nA -MM1 net25 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -XI3 net12 net25 net24 net20 / fully_differential -XI1 net23 net21 net19 net22 / fully_differential -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR3_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 net15 gnd! res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_gain_boosting -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR3_2 Biasn Biasp CR3_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pnmos_cr4_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pnmos_cr4_2.sp deleted file mode 100644 index dd1cd3a57d..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pnmos_cr4_2.sp +++ /dev/null @@ -1,92 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_gain_boosting -* View Name: schematic -* Netlisted on: Sep 11 21:05:36 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vinn Vinp Voutn Voutp -*.PININFO Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_gain_boosting -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_gain_boosting Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Vbiasp:O Voutn:O Voutp:O -MM8 Voutn net22 net23 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp net19 net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net23 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net21 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn net24 net25 vdd pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net20 net12 vdd pmos_rvt w=WA l=LA nfin=nA -MM1 net25 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -XI3 net12 net25 net24 net20 / fully_differential -XI1 net23 net21 net19 net22 / fully_differential -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR4_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM11 net023 net024 Vbiasn gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM8 net025 net010 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM9 net024 net024 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM7 net010 net010 net025 gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net025 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 net024 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net010 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_gain_boosting -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR4_2 Biasn Biasp CR4_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pnmos_cr5_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pnmos_cr5_2.sp deleted file mode 100644 index 92d6a34323..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pnmos_cr5_2.sp +++ /dev/null @@ -1,89 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_gain_boosting -* View Name: schematic -* Netlisted on: Sep 11 21:05:36 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vinn Vinp Voutn Voutp -*.PININFO Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_gain_boosting -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_gain_boosting Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Vbiasp:O Voutn:O Voutp:O -MM8 Voutn net22 net23 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp net19 net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net23 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net21 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn net24 net25 vdd pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net20 net12 vdd pmos_rvt w=WA l=LA nfin=nA -MM1 net25 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -XI3 net12 net25 net24 net20 / fully_differential -XI1 net23 net21 net19 net22 / fully_differential -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR5_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM5 net014 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net014 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_gain_boosting -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR5_2 Biasn Biasp CR5_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pnmos_cr6_3.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pnmos_cr6_3.sp deleted file mode 100644 index 9db55b2abe..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_gain_boosting_LG_pnmos_cr6_3.sp +++ /dev/null @@ -1,89 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_gain_boosting -* View Name: schematic -* Netlisted on: Sep 11 21:05:36 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vinn Vinp Voutn Voutp -*.PININFO Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_gain_boosting -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_gain_boosting Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Vbiasp:O Voutn:O Voutp:O -MM8 Voutn net22 net23 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp net19 net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net23 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net21 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn net24 net25 vdd pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net20 net12 vdd pmos_rvt w=WA l=LA nfin=nA -MM1 net25 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -XI3 net12 net25 net24 net20 / fully_differential -XI1 net23 net21 net19 net22 / fully_differential -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR6_3 Vbiasn1 Vbiasn2 Vbiasp -*.PININFO Vbiasn1:O Vbiasn2:O Vbiasp:O -MM2 Vbiasp Vbiasn2 Vbiasn1 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn2 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 Vbiasn1 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM5 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn2 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_gain_boosting -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR6_3 Biasn1 Biasn2 Biasp CR6_3 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_nmos_cr13_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_nmos_cr13_1.sp deleted file mode 100644 index c8bb072dcf..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_nmos_cr13_1.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:05:48 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_miller_compensated Vbiasn Vbiasp Vinn Vinp Voutn -+ Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM7 Voutp net15 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net22 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net22 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM8 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net22 Vinp net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net15 Vinn net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net21 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -CC1 Voutp net15 1p $[CP] -CC0 Voutn net22 1p $[CP] -.ENDS - - -.SUBCKT LG_nmos Biasp Vbiasn -*.PININFO Biasp:I Vbiasn:O -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn fully_differential_miller_compensated -xiLG_nmos Biasp LG_Vbiasn LG_nmos -xibCR13_2 Biasn Biasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_nmos_cr13_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_nmos_cr13_2.sp deleted file mode 100644 index c8bb072dcf..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_nmos_cr13_2.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:05:48 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_miller_compensated Vbiasn Vbiasp Vinn Vinp Voutn -+ Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM7 Voutp net15 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net22 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net22 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM8 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net22 Vinp net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net15 Vinn net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net21 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -CC1 Voutp net15 1p $[CP] -CC0 Voutn net22 1p $[CP] -.ENDS - - -.SUBCKT LG_nmos Biasp Vbiasn -*.PININFO Biasp:I Vbiasn:O -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn fully_differential_miller_compensated -xiLG_nmos Biasp LG_Vbiasn LG_nmos -xibCR13_2 Biasn Biasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_nmos_cr14_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_nmos_cr14_2.sp deleted file mode 100644 index a55bea1b1d..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_nmos_cr14_2.sp +++ /dev/null @@ -1,69 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:05:48 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_miller_compensated Vbiasn Vbiasp Vinn Vinp Voutn -+ Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM7 Voutp net15 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net22 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net22 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM8 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net22 Vinp net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net15 Vinn net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net21 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -CC1 Voutp net15 1p $[CP] -CC0 Voutn net22 1p $[CP] -.ENDS - - -.SUBCKT LG_nmos Biasp Vbiasn -*.PININFO Biasp:I Vbiasn:O -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR14_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net010 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 Vbiasn net010 res=rK -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn fully_differential_miller_compensated -xiLG_nmos Biasp LG_Vbiasn LG_nmos -xibCR14_2 Biasn Biasp CR14_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_nmos_cr15_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_nmos_cr15_1.sp deleted file mode 100644 index 5191cc1f67..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_nmos_cr15_1.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:05:48 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_miller_compensated Vbiasn Vbiasp Vinn Vinp Voutn -+ Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM7 Voutp net15 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net22 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net22 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM8 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net22 Vinp net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net15 Vinn net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net21 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -CC1 Voutp net15 1p $[CP] -CC0 Voutn net22 1p $[CP] -.ENDS - - -.SUBCKT LG_nmos Biasp Vbiasn -*.PININFO Biasp:I Vbiasn:O -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR15_1 Vbiasp -*.PININFO Vbiasp:O -RR1 Vbiasp gnd! res=rK -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn fully_differential_miller_compensated -xiLG_nmos Biasp LG_Vbiasn LG_nmos -xibCR15_1 Biasp CR15_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_nmos_cr16_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_nmos_cr16_1.sp deleted file mode 100644 index 282fece788..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_nmos_cr16_1.sp +++ /dev/null @@ -1,67 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:05:48 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_miller_compensated Vbiasn Vbiasp Vinn Vinp Voutn -+ Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM7 Voutp net15 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net22 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net22 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM8 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net22 Vinp net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net15 Vinn net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net21 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -CC1 Voutp net15 1p $[CP] -CC0 Voutn net22 1p $[CP] -.ENDS - - -.SUBCKT LG_nmos Biasp Vbiasn -*.PININFO Biasp:I Vbiasn:O -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR16_1 Vbiasp -*.PININFO Vbiasp:O -RR0 vdd! net6 res=rK -RR1 Vbiasp gnd! res=rK -MM2 Vbiasp Vbiasp net6 vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn fully_differential_miller_compensated -xiLG_nmos Biasp LG_Vbiasn LG_nmos -xibCR16_1 Biasp CR16_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_nmos_cr2_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_nmos_cr2_2.sp deleted file mode 100644 index 20f4e30315..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_nmos_cr2_2.sp +++ /dev/null @@ -1,69 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:05:48 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_miller_compensated Vbiasn Vbiasp Vinn Vinp Voutn -+ Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM7 Voutp net15 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net22 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net22 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM8 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net22 Vinp net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net15 Vinn net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net21 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -CC1 Voutp net15 1p $[CP] -CC0 Voutn net22 1p $[CP] -.ENDS - - -.SUBCKT LG_nmos Biasp Vbiasn -*.PININFO Biasp:I Vbiasn:O -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR2_2_wilson Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -RR0 Vbiasn gnd! res=rK -MM2 Vbiasp net12 Vbiasn gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn fully_differential_miller_compensated -xiLG_nmos Biasp LG_Vbiasn LG_nmos -xibCR2_2_wilson Biasn Biasp CR2_2_wilson -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_nmos_cr3_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_nmos_cr3_2.sp deleted file mode 100644 index 0de27fb53c..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_nmos_cr3_2.sp +++ /dev/null @@ -1,69 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:05:48 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_miller_compensated Vbiasn Vbiasp Vinn Vinp Voutn -+ Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM7 Voutp net15 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net22 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net22 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM8 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net22 Vinp net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net15 Vinn net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net21 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -CC1 Voutp net15 1p $[CP] -CC0 Voutn net22 1p $[CP] -.ENDS - - -.SUBCKT LG_nmos Biasp Vbiasn -*.PININFO Biasp:I Vbiasn:O -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR3_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 net15 gnd! res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn fully_differential_miller_compensated -xiLG_nmos Biasp LG_Vbiasn LG_nmos -xibCR3_2 Biasn Biasp CR3_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_nmos_cr4_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_nmos_cr4_2.sp deleted file mode 100644 index bed11c070d..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_nmos_cr4_2.sp +++ /dev/null @@ -1,74 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:05:48 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_miller_compensated Vbiasn Vbiasp Vinn Vinp Voutn -+ Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM7 Voutp net15 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net22 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net22 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM8 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net22 Vinp net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net15 Vinn net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net21 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -CC1 Voutp net15 1p $[CP] -CC0 Voutn net22 1p $[CP] -.ENDS - - -.SUBCKT LG_nmos Biasp Vbiasn -*.PININFO Biasp:I Vbiasn:O -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR4_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM11 net023 net024 Vbiasn gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM8 net025 net010 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM9 net024 net024 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM7 net010 net010 net025 gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net025 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 net024 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net010 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn fully_differential_miller_compensated -xiLG_nmos Biasp LG_Vbiasn LG_nmos -xibCR4_2 Biasn Biasp CR4_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_nmos_cr5_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_nmos_cr5_2.sp deleted file mode 100644 index 2b93fb89c0..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_nmos_cr5_2.sp +++ /dev/null @@ -1,71 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:05:48 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_miller_compensated Vbiasn Vbiasp Vinn Vinp Voutn -+ Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM7 Voutp net15 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net22 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net22 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM8 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net22 Vinp net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net15 Vinn net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net21 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -CC1 Voutp net15 1p $[CP] -CC0 Voutn net22 1p $[CP] -.ENDS - - -.SUBCKT LG_nmos Biasp Vbiasn -*.PININFO Biasp:I Vbiasn:O -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR5_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM5 net014 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net014 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn fully_differential_miller_compensated -xiLG_nmos Biasp LG_Vbiasn LG_nmos -xibCR5_2 Biasn Biasp CR5_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_nmos_cr6_3.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_nmos_cr6_3.sp deleted file mode 100644 index efddbca442..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_nmos_cr6_3.sp +++ /dev/null @@ -1,71 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:05:48 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_miller_compensated Vbiasn Vbiasp Vinn Vinp Voutn -+ Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM7 Voutp net15 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net22 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net22 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM8 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net22 Vinp net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net15 Vinn net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net21 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -CC1 Voutp net15 1p $[CP] -CC0 Voutn net22 1p $[CP] -.ENDS - - -.SUBCKT LG_nmos Biasp Vbiasn -*.PININFO Biasp:I Vbiasn:O -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR6_3 Vbiasn1 Vbiasn2 Vbiasp -*.PININFO Vbiasn1:O Vbiasn2:O Vbiasp:O -MM2 Vbiasp Vbiasn2 Vbiasn1 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn2 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 Vbiasn1 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM5 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn2 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn fully_differential_miller_compensated -xiLG_nmos Biasp LG_Vbiasn LG_nmos -xibCR6_3 Biasn1 Biasn2 Biasp CR6_3 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_nmos_l1_cr11_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_nmos_l1_cr11_1.sp deleted file mode 100644 index 80bb289b5a..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_nmos_l1_cr11_1.sp +++ /dev/null @@ -1,71 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:05:48 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_miller_compensated Vbiasn Vbiasp Vinn Vinp Voutn -+ Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM7 Voutp net15 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net22 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net22 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM8 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net22 Vinp net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net15 Vinn net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net21 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -CC1 Voutp net15 1p $[CP] -CC0 Voutn net22 1p $[CP] -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR11_1 Vbiasn -*.PININFO Vbiasn:O -RRF vdd! Vbiasn res=rK -MM1 net9 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net9 net9 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn net9 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn fully_differential_miller_compensated -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR11_1 Biasn CR11_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_nmos_l1_cr12_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_nmos_l1_cr12_1.sp deleted file mode 100644 index 02f6837251..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_nmos_l1_cr12_1.sp +++ /dev/null @@ -1,71 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:05:48 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_miller_compensated Vbiasn Vbiasp Vinn Vinp Voutn -+ Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM7 Voutp net15 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net22 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net22 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM8 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net22 Vinp net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net15 Vinn net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net21 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -CC1 Voutp net15 1p $[CP] -CC0 Voutn net22 1p $[CP] -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR12_1 Vbiasn -*.PININFO Vbiasn:O -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 net10 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn net10 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RRF vdd! Vbiasn res=rK -RR0 vdd! net10 res=rK -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn fully_differential_miller_compensated -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR12_1 Biasn CR12_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_nmos_l1_cr13_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_nmos_l1_cr13_1.sp deleted file mode 100644 index 8347ee8458..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_nmos_l1_cr13_1.sp +++ /dev/null @@ -1,70 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:05:48 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_miller_compensated Vbiasn Vbiasp Vinn Vinp Voutn -+ Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM7 Voutp net15 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net22 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net22 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM8 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net22 Vinp net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net15 Vinn net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net21 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -CC1 Voutp net15 1p $[CP] -CC0 Voutn net22 1p $[CP] -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn fully_differential_miller_compensated -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR13_2 Biasn Vbiasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_nmos_l1_cr13_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_nmos_l1_cr13_2.sp deleted file mode 100644 index 8347ee8458..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_nmos_l1_cr13_2.sp +++ /dev/null @@ -1,70 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:05:48 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_miller_compensated Vbiasn Vbiasp Vinn Vinp Voutn -+ Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM7 Voutp net15 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net22 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net22 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM8 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net22 Vinp net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net15 Vinn net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net21 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -CC1 Voutp net15 1p $[CP] -CC0 Voutn net22 1p $[CP] -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn fully_differential_miller_compensated -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR13_2 Biasn Vbiasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_nmos_l1_cr14_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_nmos_l1_cr14_2.sp deleted file mode 100644 index 62206287bc..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_nmos_l1_cr14_2.sp +++ /dev/null @@ -1,71 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:05:48 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_miller_compensated Vbiasn Vbiasp Vinn Vinp Voutn -+ Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM7 Voutp net15 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net22 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net22 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM8 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net22 Vinp net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net15 Vinn net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net21 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -CC1 Voutp net15 1p $[CP] -CC0 Voutn net22 1p $[CP] -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR14_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net010 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 Vbiasn net010 res=rK -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn fully_differential_miller_compensated -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR14_2 Biasn Vbiasp CR14_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_nmos_l1_cr1_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_nmos_l1_cr1_1.sp deleted file mode 100644 index cc5f09e8e7..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_nmos_l1_cr1_1.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:05:48 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_miller_compensated Vbiasn Vbiasp Vinn Vinp Voutn -+ Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM7 Voutp net15 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net22 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net22 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM8 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net22 Vinp net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net15 Vinn net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net21 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -CC1 Voutp net15 1p $[CP] -CC0 Voutn net22 1p $[CP] -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR1_1 Vbiasn -*.PININFO Vbiasn:O -RRF vdd! Vbiasn res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn fully_differential_miller_compensated -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR1_1 Biasn CR1_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_nmos_l1_cr2_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_nmos_l1_cr2_2.sp deleted file mode 100644 index 1308df39c0..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_nmos_l1_cr2_2.sp +++ /dev/null @@ -1,71 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:05:48 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_miller_compensated Vbiasn Vbiasp Vinn Vinp Voutn -+ Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM7 Voutp net15 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net22 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net22 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM8 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net22 Vinp net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net15 Vinn net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net21 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -CC1 Voutp net15 1p $[CP] -CC0 Voutn net22 1p $[CP] -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR2_2_wilson Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -RR0 Vbiasn gnd! res=rK -MM2 Vbiasp net12 Vbiasn gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn fully_differential_miller_compensated -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR2_2_wilson Biasn Vbiasp CR2_2_wilson -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_nmos_l1_cr3_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_nmos_l1_cr3_2.sp deleted file mode 100644 index 3fd981799e..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_nmos_l1_cr3_2.sp +++ /dev/null @@ -1,71 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:05:48 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_miller_compensated Vbiasn Vbiasp Vinn Vinp Voutn -+ Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM7 Voutp net15 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net22 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net22 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM8 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net22 Vinp net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net15 Vinn net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net21 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -CC1 Voutp net15 1p $[CP] -CC0 Voutn net22 1p $[CP] -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR3_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 net15 gnd! res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn fully_differential_miller_compensated -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR3_2 Biasn Vbiasp CR3_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_nmos_l1_cr4_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_nmos_l1_cr4_2.sp deleted file mode 100644 index 166add3231..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_nmos_l1_cr4_2.sp +++ /dev/null @@ -1,76 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:05:48 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_miller_compensated Vbiasn Vbiasp Vinn Vinp Voutn -+ Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM7 Voutp net15 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net22 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net22 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM8 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net22 Vinp net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net15 Vinn net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net21 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -CC1 Voutp net15 1p $[CP] -CC0 Voutn net22 1p $[CP] -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR4_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM11 net023 net024 Vbiasn gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM8 net025 net010 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM9 net024 net024 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM7 net010 net010 net025 gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net025 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 net024 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net010 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn fully_differential_miller_compensated -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR4_2 Biasn Vbiasp CR4_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_nmos_l1_cr5_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_nmos_l1_cr5_2.sp deleted file mode 100644 index 110c60d209..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_nmos_l1_cr5_2.sp +++ /dev/null @@ -1,73 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:05:48 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_miller_compensated Vbiasn Vbiasp Vinn Vinp Voutn -+ Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM7 Voutp net15 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net22 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net22 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM8 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net22 Vinp net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net15 Vinn net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net21 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -CC1 Voutp net15 1p $[CP] -CC0 Voutn net22 1p $[CP] -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR5_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM5 net014 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net014 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn fully_differential_miller_compensated -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR5_2 Biasn Vbiasp CR5_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_nmos_l1_cr7_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_nmos_l1_cr7_1.sp deleted file mode 100644 index b47b61cafc..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_nmos_l1_cr7_1.sp +++ /dev/null @@ -1,71 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:05:48 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_miller_compensated Vbiasn Vbiasp Vinn Vinp Voutn -+ Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM7 Voutp net15 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net22 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net22 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM8 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net22 Vinp net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net15 Vinn net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net21 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -CC1 Voutp net15 1p $[CP] -CC0 Voutn net22 1p $[CP] -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR7_1 Vbiasn -*.PININFO Vbiasn:O -RR1 Vbiasn net7 res=rK -RR0 vdd! net7 res=rK -RRF vdd! Vbiasn res=rK -MM1 net7 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn fully_differential_miller_compensated -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR7_1 Biasn CR7_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_nmos_l1_cr9_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_nmos_l1_cr9_1.sp deleted file mode 100644 index 0a668685eb..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_nmos_l1_cr9_1.sp +++ /dev/null @@ -1,69 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:05:48 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_miller_compensated Vbiasn Vbiasp Vinn Vinp Voutn -+ Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM7 Voutp net15 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net22 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net22 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM8 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net22 Vinp net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net15 Vinn net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net21 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -CC1 Voutp net15 1p $[CP] -CC0 Voutn net22 1p $[CP] -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR9_1 Vbiasn -*.PININFO Vbiasn:O -RR1 net05 gnd! res=rK -RRF vdd! Vbiasn res=rK -MM0 Vbiasn Vbiasn net05 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn fully_differential_miller_compensated -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR9_1 Biasn CR9_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_npmos_cr11_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_npmos_cr11_1.sp deleted file mode 100644 index 7a35601335..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_npmos_cr11_1.sp +++ /dev/null @@ -1,73 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:05:48 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_miller_compensated Vbiasn Vbiasp Vinn Vinp Voutn -+ Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM7 Voutp net15 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net22 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net22 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM8 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net22 Vinp net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net15 Vinn net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net21 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -CC1 Voutp net15 1p $[CP] -CC0 Voutn net22 1p $[CP] -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR11_1 Vbiasn -*.PININFO Vbiasn:O -RRF vdd! Vbiasn res=rK -MM1 net9 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net9 net9 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn net9 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn fully_differential_miller_compensated -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR11_1 Biasn CR11_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_npmos_cr12_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_npmos_cr12_1.sp deleted file mode 100644 index 7bae2ad618..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_npmos_cr12_1.sp +++ /dev/null @@ -1,73 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:05:48 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_miller_compensated Vbiasn Vbiasp Vinn Vinp Voutn -+ Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM7 Voutp net15 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net22 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net22 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM8 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net22 Vinp net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net15 Vinn net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net21 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -CC1 Voutp net15 1p $[CP] -CC0 Voutn net22 1p $[CP] -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR12_1 Vbiasn -*.PININFO Vbiasn:O -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 net10 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn net10 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RRF vdd! Vbiasn res=rK -RR0 vdd! net10 res=rK -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn fully_differential_miller_compensated -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR12_1 Biasn CR12_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_npmos_cr13_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_npmos_cr13_1.sp deleted file mode 100644 index 3b0569035a..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_npmos_cr13_1.sp +++ /dev/null @@ -1,72 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:05:48 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_miller_compensated Vbiasn Vbiasp Vinn Vinp Voutn -+ Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM7 Voutp net15 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net22 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net22 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM8 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net22 Vinp net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net15 Vinn net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net21 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -CC1 Voutp net15 1p $[CP] -CC0 Voutn net22 1p $[CP] -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn fully_differential_miller_compensated -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR13_2 Biasn Vbiasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_npmos_cr13_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_npmos_cr13_2.sp deleted file mode 100644 index 3b0569035a..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_npmos_cr13_2.sp +++ /dev/null @@ -1,72 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:05:48 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_miller_compensated Vbiasn Vbiasp Vinn Vinp Voutn -+ Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM7 Voutp net15 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net22 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net22 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM8 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net22 Vinp net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net15 Vinn net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net21 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -CC1 Voutp net15 1p $[CP] -CC0 Voutn net22 1p $[CP] -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn fully_differential_miller_compensated -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR13_2 Biasn Vbiasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_npmos_cr14_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_npmos_cr14_2.sp deleted file mode 100644 index 14f3613b3a..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_npmos_cr14_2.sp +++ /dev/null @@ -1,73 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:05:48 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_miller_compensated Vbiasn Vbiasp Vinn Vinp Voutn -+ Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM7 Voutp net15 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net22 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net22 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM8 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net22 Vinp net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net15 Vinn net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net21 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -CC1 Voutp net15 1p $[CP] -CC0 Voutn net22 1p $[CP] -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR14_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net010 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 Vbiasn net010 res=rK -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn fully_differential_miller_compensated -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR14_2 Biasn Vbiasp CR14_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_npmos_cr1_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_npmos_cr1_1.sp deleted file mode 100644 index 1ba0d84df4..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_npmos_cr1_1.sp +++ /dev/null @@ -1,70 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:05:48 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_miller_compensated Vbiasn Vbiasp Vinn Vinp Voutn -+ Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM7 Voutp net15 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net22 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net22 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM8 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net22 Vinp net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net15 Vinn net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net21 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -CC1 Voutp net15 1p $[CP] -CC0 Voutn net22 1p $[CP] -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR1_1 Vbiasn -*.PININFO Vbiasn:O -RRF vdd! Vbiasn res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn fully_differential_miller_compensated -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR1_1 Biasn CR1_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_npmos_cr2_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_npmos_cr2_2.sp deleted file mode 100644 index 715d397cae..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_npmos_cr2_2.sp +++ /dev/null @@ -1,73 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:05:48 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_miller_compensated Vbiasn Vbiasp Vinn Vinp Voutn -+ Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM7 Voutp net15 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net22 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net22 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM8 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net22 Vinp net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net15 Vinn net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net21 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -CC1 Voutp net15 1p $[CP] -CC0 Voutn net22 1p $[CP] -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR2_2_wilson Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -RR0 Vbiasn gnd! res=rK -MM2 Vbiasp net12 Vbiasn gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn fully_differential_miller_compensated -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR2_2_wilson Biasn Vbiasp CR2_2_wilson -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_npmos_cr3_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_npmos_cr3_2.sp deleted file mode 100644 index 1a1f22ebd9..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_npmos_cr3_2.sp +++ /dev/null @@ -1,73 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:05:48 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_miller_compensated Vbiasn Vbiasp Vinn Vinp Voutn -+ Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM7 Voutp net15 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net22 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net22 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM8 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net22 Vinp net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net15 Vinn net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net21 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -CC1 Voutp net15 1p $[CP] -CC0 Voutn net22 1p $[CP] -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR3_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 net15 gnd! res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn fully_differential_miller_compensated -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR3_2 Biasn Vbiasp CR3_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_npmos_cr4_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_npmos_cr4_2.sp deleted file mode 100644 index d062dce6c6..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_npmos_cr4_2.sp +++ /dev/null @@ -1,78 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:05:48 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_miller_compensated Vbiasn Vbiasp Vinn Vinp Voutn -+ Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM7 Voutp net15 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net22 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net22 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM8 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net22 Vinp net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net15 Vinn net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net21 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -CC1 Voutp net15 1p $[CP] -CC0 Voutn net22 1p $[CP] -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR4_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM11 net023 net024 Vbiasn gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM8 net025 net010 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM9 net024 net024 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM7 net010 net010 net025 gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net025 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 net024 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net010 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn fully_differential_miller_compensated -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR4_2 Biasn Vbiasp CR4_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_npmos_cr5_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_npmos_cr5_2.sp deleted file mode 100644 index 56e62c6dfe..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_npmos_cr5_2.sp +++ /dev/null @@ -1,75 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:05:48 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_miller_compensated Vbiasn Vbiasp Vinn Vinp Voutn -+ Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM7 Voutp net15 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net22 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net22 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM8 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net22 Vinp net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net15 Vinn net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net21 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -CC1 Voutp net15 1p $[CP] -CC0 Voutn net22 1p $[CP] -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR5_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM5 net014 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net014 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn fully_differential_miller_compensated -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR5_2 Biasn Vbiasp CR5_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_npmos_cr7_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_npmos_cr7_1.sp deleted file mode 100644 index 7b6ab68aa1..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_npmos_cr7_1.sp +++ /dev/null @@ -1,73 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:05:48 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_miller_compensated Vbiasn Vbiasp Vinn Vinp Voutn -+ Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM7 Voutp net15 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net22 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net22 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM8 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net22 Vinp net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net15 Vinn net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net21 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -CC1 Voutp net15 1p $[CP] -CC0 Voutn net22 1p $[CP] -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR7_1 Vbiasn -*.PININFO Vbiasn:O -RR1 Vbiasn net7 res=rK -RR0 vdd! net7 res=rK -RRF vdd! Vbiasn res=rK -MM1 net7 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn fully_differential_miller_compensated -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR7_1 Biasn CR7_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_npmos_cr9_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_npmos_cr9_1.sp deleted file mode 100644 index ea7290b470..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_npmos_cr9_1.sp +++ /dev/null @@ -1,71 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:05:48 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_miller_compensated Vbiasn Vbiasp Vinn Vinp Voutn -+ Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM7 Voutp net15 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net22 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net22 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM8 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net22 Vinp net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net15 Vinn net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net21 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -CC1 Voutp net15 1p $[CP] -CC0 Voutn net22 1p $[CP] -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR9_1 Vbiasn -*.PININFO Vbiasn:O -RR1 net05 gnd! res=rK -RRF vdd! Vbiasn res=rK -MM0 Vbiasn Vbiasn net05 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn fully_differential_miller_compensated -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR9_1 Biasn CR9_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pmos_cr11_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pmos_cr11_1.sp deleted file mode 100644 index 1c0e9ceae2..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pmos_cr11_1.sp +++ /dev/null @@ -1,69 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:05:48 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_miller_compensated Vbiasn Vbiasp Vinn Vinp Voutn -+ Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM7 Voutp net15 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net22 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net22 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM8 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net22 Vinp net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net15 Vinn net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net21 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -CC1 Voutp net15 1p $[CP] -CC0 Voutn net22 1p $[CP] -.ENDS - - -.SUBCKT LG_pmos Biasn Vbiasp -*.PININFO Biasn:I Vbiasp:O -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR11_1 Vbiasn -*.PININFO Vbiasn:O -RRF vdd! Vbiasn res=rK -MM1 net9 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net9 net9 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn net9 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn fully_differential_miller_compensated -xiLG_pmos Biasn LG_Vbiasp LG_pmos -xibCR11_1 Biasn CR11_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pmos_cr12_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pmos_cr12_1.sp deleted file mode 100644 index 5ee01b5e0c..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pmos_cr12_1.sp +++ /dev/null @@ -1,69 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:05:48 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_miller_compensated Vbiasn Vbiasp Vinn Vinp Voutn -+ Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM7 Voutp net15 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net22 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net22 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM8 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net22 Vinp net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net15 Vinn net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net21 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -CC1 Voutp net15 1p $[CP] -CC0 Voutn net22 1p $[CP] -.ENDS - - -.SUBCKT LG_pmos Biasn Vbiasp -*.PININFO Biasn:I Vbiasp:O -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR12_1 Vbiasn -*.PININFO Vbiasn:O -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 net10 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn net10 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RRF vdd! Vbiasn res=rK -RR0 vdd! net10 res=rK -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn fully_differential_miller_compensated -xiLG_pmos Biasn LG_Vbiasp LG_pmos -xibCR12_1 Biasn CR12_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pmos_cr13_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pmos_cr13_1.sp deleted file mode 100644 index c4fb5a52a6..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pmos_cr13_1.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:05:48 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_miller_compensated Vbiasn Vbiasp Vinn Vinp Voutn -+ Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM7 Voutp net15 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net22 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net22 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM8 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net22 Vinp net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net15 Vinn net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net21 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -CC1 Voutp net15 1p $[CP] -CC0 Voutn net22 1p $[CP] -.ENDS - - -.SUBCKT LG_pmos Biasn Vbiasp -*.PININFO Biasn:I Vbiasp:O -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn fully_differential_miller_compensated -xiLG_pmos Biasn LG_Vbiasp LG_pmos -xibCR13_2 Biasn Vbiasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pmos_cr13_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pmos_cr13_2.sp deleted file mode 100644 index c4fb5a52a6..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pmos_cr13_2.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:05:48 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_miller_compensated Vbiasn Vbiasp Vinn Vinp Voutn -+ Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM7 Voutp net15 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net22 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net22 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM8 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net22 Vinp net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net15 Vinn net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net21 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -CC1 Voutp net15 1p $[CP] -CC0 Voutn net22 1p $[CP] -.ENDS - - -.SUBCKT LG_pmos Biasn Vbiasp -*.PININFO Biasn:I Vbiasp:O -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn fully_differential_miller_compensated -xiLG_pmos Biasn LG_Vbiasp LG_pmos -xibCR13_2 Biasn Vbiasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pmos_cr14_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pmos_cr14_2.sp deleted file mode 100644 index fce6473835..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pmos_cr14_2.sp +++ /dev/null @@ -1,69 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:05:48 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_miller_compensated Vbiasn Vbiasp Vinn Vinp Voutn -+ Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM7 Voutp net15 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net22 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net22 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM8 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net22 Vinp net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net15 Vinn net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net21 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -CC1 Voutp net15 1p $[CP] -CC0 Voutn net22 1p $[CP] -.ENDS - - -.SUBCKT LG_pmos Biasn Vbiasp -*.PININFO Biasn:I Vbiasp:O -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR14_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net010 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 Vbiasn net010 res=rK -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn fully_differential_miller_compensated -xiLG_pmos Biasn LG_Vbiasp LG_pmos -xibCR14_2 Biasn Vbiasp CR14_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pmos_cr1_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pmos_cr1_1.sp deleted file mode 100644 index 78caeb9ba9..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pmos_cr1_1.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:05:48 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_miller_compensated Vbiasn Vbiasp Vinn Vinp Voutn -+ Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM7 Voutp net15 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net22 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net22 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM8 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net22 Vinp net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net15 Vinn net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net21 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -CC1 Voutp net15 1p $[CP] -CC0 Voutn net22 1p $[CP] -.ENDS - - -.SUBCKT LG_pmos Biasn Vbiasp -*.PININFO Biasn:I Vbiasp:O -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR1_1 Vbiasn -*.PININFO Vbiasn:O -RRF vdd! Vbiasn res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn fully_differential_miller_compensated -xiLG_pmos Biasn LG_Vbiasp LG_pmos -xibCR1_1 Biasn CR1_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pmos_cr2_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pmos_cr2_2.sp deleted file mode 100644 index b1abbbd504..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pmos_cr2_2.sp +++ /dev/null @@ -1,69 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:05:48 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_miller_compensated Vbiasn Vbiasp Vinn Vinp Voutn -+ Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM7 Voutp net15 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net22 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net22 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM8 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net22 Vinp net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net15 Vinn net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net21 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -CC1 Voutp net15 1p $[CP] -CC0 Voutn net22 1p $[CP] -.ENDS - - -.SUBCKT LG_pmos Biasn Vbiasp -*.PININFO Biasn:I Vbiasp:O -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR2_2_wilson Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -RR0 Vbiasn gnd! res=rK -MM2 Vbiasp net12 Vbiasn gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn fully_differential_miller_compensated -xiLG_pmos Biasn LG_Vbiasp LG_pmos -xibCR2_2_wilson Biasn Vbiasp CR2_2_wilson -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pmos_cr3_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pmos_cr3_2.sp deleted file mode 100644 index 082aeba4ed..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pmos_cr3_2.sp +++ /dev/null @@ -1,69 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:05:48 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_miller_compensated Vbiasn Vbiasp Vinn Vinp Voutn -+ Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM7 Voutp net15 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net22 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net22 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM8 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net22 Vinp net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net15 Vinn net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net21 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -CC1 Voutp net15 1p $[CP] -CC0 Voutn net22 1p $[CP] -.ENDS - - -.SUBCKT LG_pmos Biasn Vbiasp -*.PININFO Biasn:I Vbiasp:O -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR3_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 net15 gnd! res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn fully_differential_miller_compensated -xiLG_pmos Biasn LG_Vbiasp LG_pmos -xibCR3_2 Biasn Vbiasp CR3_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pmos_cr4_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pmos_cr4_2.sp deleted file mode 100644 index bdffb59bcd..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pmos_cr4_2.sp +++ /dev/null @@ -1,74 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:05:48 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_miller_compensated Vbiasn Vbiasp Vinn Vinp Voutn -+ Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM7 Voutp net15 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net22 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net22 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM8 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net22 Vinp net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net15 Vinn net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net21 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -CC1 Voutp net15 1p $[CP] -CC0 Voutn net22 1p $[CP] -.ENDS - - -.SUBCKT LG_pmos Biasn Vbiasp -*.PININFO Biasn:I Vbiasp:O -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR4_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM11 net023 net024 Vbiasn gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM8 net025 net010 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM9 net024 net024 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM7 net010 net010 net025 gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net025 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 net024 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net010 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn fully_differential_miller_compensated -xiLG_pmos Biasn LG_Vbiasp LG_pmos -xibCR4_2 Biasn Vbiasp CR4_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pmos_cr5_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pmos_cr5_2.sp deleted file mode 100644 index 384f46da24..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pmos_cr5_2.sp +++ /dev/null @@ -1,71 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:05:48 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_miller_compensated Vbiasn Vbiasp Vinn Vinp Voutn -+ Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM7 Voutp net15 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net22 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net22 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM8 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net22 Vinp net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net15 Vinn net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net21 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -CC1 Voutp net15 1p $[CP] -CC0 Voutn net22 1p $[CP] -.ENDS - - -.SUBCKT LG_pmos Biasn Vbiasp -*.PININFO Biasn:I Vbiasp:O -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR5_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM5 net014 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net014 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn fully_differential_miller_compensated -xiLG_pmos Biasn LG_Vbiasp LG_pmos -xibCR5_2 Biasn Vbiasp CR5_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pmos_cr7_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pmos_cr7_1.sp deleted file mode 100644 index 88b812074c..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pmos_cr7_1.sp +++ /dev/null @@ -1,69 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:05:48 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_miller_compensated Vbiasn Vbiasp Vinn Vinp Voutn -+ Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM7 Voutp net15 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net22 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net22 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM8 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net22 Vinp net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net15 Vinn net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net21 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -CC1 Voutp net15 1p $[CP] -CC0 Voutn net22 1p $[CP] -.ENDS - - -.SUBCKT LG_pmos Biasn Vbiasp -*.PININFO Biasn:I Vbiasp:O -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR7_1 Vbiasn -*.PININFO Vbiasn:O -RR1 Vbiasn net7 res=rK -RR0 vdd! net7 res=rK -RRF vdd! Vbiasn res=rK -MM1 net7 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn fully_differential_miller_compensated -xiLG_pmos Biasn LG_Vbiasp LG_pmos -xibCR7_1 Biasn CR7_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pmos_cr9_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pmos_cr9_1.sp deleted file mode 100644 index 329b75ab7b..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pmos_cr9_1.sp +++ /dev/null @@ -1,67 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:05:48 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_miller_compensated Vbiasn Vbiasp Vinn Vinp Voutn -+ Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM7 Voutp net15 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net22 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net22 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM8 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net22 Vinp net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net15 Vinn net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net21 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -CC1 Voutp net15 1p $[CP] -CC0 Voutn net22 1p $[CP] -.ENDS - - -.SUBCKT LG_pmos Biasn Vbiasp -*.PININFO Biasn:I Vbiasp:O -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR9_1 Vbiasn -*.PININFO Vbiasn:O -RR1 net05 gnd! res=rK -RRF vdd! Vbiasn res=rK -MM0 Vbiasn Vbiasn net05 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn fully_differential_miller_compensated -xiLG_pmos Biasn LG_Vbiasp LG_pmos -xibCR9_1 Biasn CR9_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pmos_l1_cr13_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pmos_l1_cr13_1.sp deleted file mode 100644 index 7102b79e6f..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pmos_l1_cr13_1.sp +++ /dev/null @@ -1,70 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:05:48 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_miller_compensated Vbiasn Vbiasp Vinn Vinp Voutn -+ Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM7 Voutp net15 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net22 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net22 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM8 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net22 Vinp net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net15 Vinn net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net21 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -CC1 Voutp net15 1p $[CP] -CC0 Voutn net22 1p $[CP] -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn fully_differential_miller_compensated -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR13_2 Biasn Biasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pmos_l1_cr13_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pmos_l1_cr13_2.sp deleted file mode 100644 index 7102b79e6f..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pmos_l1_cr13_2.sp +++ /dev/null @@ -1,70 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:05:48 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_miller_compensated Vbiasn Vbiasp Vinn Vinp Voutn -+ Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM7 Voutp net15 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net22 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net22 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM8 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net22 Vinp net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net15 Vinn net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net21 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -CC1 Voutp net15 1p $[CP] -CC0 Voutn net22 1p $[CP] -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn fully_differential_miller_compensated -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR13_2 Biasn Biasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pmos_l1_cr14_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pmos_l1_cr14_2.sp deleted file mode 100644 index aaecefef5c..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pmos_l1_cr14_2.sp +++ /dev/null @@ -1,71 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:05:48 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_miller_compensated Vbiasn Vbiasp Vinn Vinp Voutn -+ Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM7 Voutp net15 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net22 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net22 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM8 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net22 Vinp net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net15 Vinn net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net21 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -CC1 Voutp net15 1p $[CP] -CC0 Voutn net22 1p $[CP] -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR14_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net010 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 Vbiasn net010 res=rK -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn fully_differential_miller_compensated -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR14_2 Biasn Biasp CR14_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pmos_l1_cr15_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pmos_l1_cr15_1.sp deleted file mode 100644 index 0e1dc174c4..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pmos_l1_cr15_1.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:05:48 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_miller_compensated Vbiasn Vbiasp Vinn Vinp Voutn -+ Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM7 Voutp net15 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net22 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net22 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM8 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net22 Vinp net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net15 Vinn net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net21 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -CC1 Voutp net15 1p $[CP] -CC0 Voutn net22 1p $[CP] -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR15_1 Vbiasp -*.PININFO Vbiasp:O -RR1 Vbiasp gnd! res=rK -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn fully_differential_miller_compensated -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR15_1 Biasp CR15_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pmos_l1_cr16_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pmos_l1_cr16_1.sp deleted file mode 100644 index cf6d784060..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pmos_l1_cr16_1.sp +++ /dev/null @@ -1,69 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:05:48 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_miller_compensated Vbiasn Vbiasp Vinn Vinp Voutn -+ Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM7 Voutp net15 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net22 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net22 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM8 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net22 Vinp net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net15 Vinn net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net21 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -CC1 Voutp net15 1p $[CP] -CC0 Voutn net22 1p $[CP] -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR16_1 Vbiasp -*.PININFO Vbiasp:O -RR0 vdd! net6 res=rK -RR1 Vbiasp gnd! res=rK -MM2 Vbiasp Vbiasp net6 vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn fully_differential_miller_compensated -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR16_1 Biasp CR16_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pmos_l1_cr2_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pmos_l1_cr2_2.sp deleted file mode 100644 index 43c1fa7452..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pmos_l1_cr2_2.sp +++ /dev/null @@ -1,71 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:05:48 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_miller_compensated Vbiasn Vbiasp Vinn Vinp Voutn -+ Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM7 Voutp net15 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net22 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net22 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM8 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net22 Vinp net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net15 Vinn net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net21 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -CC1 Voutp net15 1p $[CP] -CC0 Voutn net22 1p $[CP] -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR2_2_wilson Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -RR0 Vbiasn gnd! res=rK -MM2 Vbiasp net12 Vbiasn gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn fully_differential_miller_compensated -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR2_2_wilson Biasn Biasp CR2_2_wilson -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pmos_l1_cr3_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pmos_l1_cr3_2.sp deleted file mode 100644 index c6fe98a24b..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pmos_l1_cr3_2.sp +++ /dev/null @@ -1,71 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:05:48 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_miller_compensated Vbiasn Vbiasp Vinn Vinp Voutn -+ Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM7 Voutp net15 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net22 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net22 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM8 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net22 Vinp net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net15 Vinn net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net21 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -CC1 Voutp net15 1p $[CP] -CC0 Voutn net22 1p $[CP] -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR3_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 net15 gnd! res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn fully_differential_miller_compensated -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR3_2 Biasn Biasp CR3_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pmos_l1_cr4_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pmos_l1_cr4_2.sp deleted file mode 100644 index 90368f4870..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pmos_l1_cr4_2.sp +++ /dev/null @@ -1,76 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:05:48 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_miller_compensated Vbiasn Vbiasp Vinn Vinp Voutn -+ Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM7 Voutp net15 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net22 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net22 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM8 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net22 Vinp net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net15 Vinn net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net21 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -CC1 Voutp net15 1p $[CP] -CC0 Voutn net22 1p $[CP] -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR4_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM11 net023 net024 Vbiasn gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM8 net025 net010 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM9 net024 net024 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM7 net010 net010 net025 gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net025 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 net024 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net010 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn fully_differential_miller_compensated -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR4_2 Biasn Biasp CR4_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pmos_l1_cr5_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pmos_l1_cr5_2.sp deleted file mode 100644 index bb2e17d6c8..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pmos_l1_cr5_2.sp +++ /dev/null @@ -1,73 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:05:48 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_miller_compensated Vbiasn Vbiasp Vinn Vinp Voutn -+ Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM7 Voutp net15 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net22 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net22 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM8 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net22 Vinp net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net15 Vinn net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net21 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -CC1 Voutp net15 1p $[CP] -CC0 Voutn net22 1p $[CP] -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR5_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM5 net014 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net014 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn fully_differential_miller_compensated -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR5_2 Biasn Biasp CR5_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pmos_l1_cr6_3.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pmos_l1_cr6_3.sp deleted file mode 100644 index 17ce970958..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pmos_l1_cr6_3.sp +++ /dev/null @@ -1,73 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:05:48 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_miller_compensated Vbiasn Vbiasp Vinn Vinp Voutn -+ Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM7 Voutp net15 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net22 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net22 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM8 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net22 Vinp net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net15 Vinn net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net21 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -CC1 Voutp net15 1p $[CP] -CC0 Voutn net22 1p $[CP] -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR6_3 Vbiasn1 Vbiasn2 Vbiasp -*.PININFO Vbiasn1:O Vbiasn2:O Vbiasp:O -MM2 Vbiasp Vbiasn2 Vbiasn1 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn2 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 Vbiasn1 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM5 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn2 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn fully_differential_miller_compensated -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR6_3 Biasn1 Biasn2 Biasp CR6_3 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pnmos_4_cr13_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pnmos_4_cr13_1.sp deleted file mode 100644 index 8ac7c76fdf..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pnmos_4_cr13_1.sp +++ /dev/null @@ -1,72 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:05:48 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_miller_compensated Vbiasn Vbiasp Vinn Vinp Voutn -+ Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM7 Voutp net15 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net22 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net22 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM8 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net22 Vinp net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net15 Vinn net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net21 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -CC1 Voutp net15 1p $[CP] -CC0 Voutn net22 1p $[CP] -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn fully_differential_miller_compensated -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR13_2 Biasn Biasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pnmos_4_cr13_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pnmos_4_cr13_2.sp deleted file mode 100644 index 8ac7c76fdf..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pnmos_4_cr13_2.sp +++ /dev/null @@ -1,72 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:05:48 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_miller_compensated Vbiasn Vbiasp Vinn Vinp Voutn -+ Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM7 Voutp net15 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net22 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net22 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM8 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net22 Vinp net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net15 Vinn net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net21 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -CC1 Voutp net15 1p $[CP] -CC0 Voutn net22 1p $[CP] -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn fully_differential_miller_compensated -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR13_2 Biasn Biasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pnmos_4_cr14_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pnmos_4_cr14_2.sp deleted file mode 100644 index 29a0f1cc54..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pnmos_4_cr14_2.sp +++ /dev/null @@ -1,73 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:05:48 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_miller_compensated Vbiasn Vbiasp Vinn Vinp Voutn -+ Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM7 Voutp net15 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net22 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net22 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM8 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net22 Vinp net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net15 Vinn net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net21 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -CC1 Voutp net15 1p $[CP] -CC0 Voutn net22 1p $[CP] -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR14_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net010 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 Vbiasn net010 res=rK -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn fully_differential_miller_compensated -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR14_2 Biasn Biasp CR14_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pnmos_4_cr15_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pnmos_4_cr15_1.sp deleted file mode 100644 index 1a6f70b54b..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pnmos_4_cr15_1.sp +++ /dev/null @@ -1,70 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:05:48 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_miller_compensated Vbiasn Vbiasp Vinn Vinp Voutn -+ Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM7 Voutp net15 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net22 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net22 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM8 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net22 Vinp net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net15 Vinn net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net21 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -CC1 Voutp net15 1p $[CP] -CC0 Voutn net22 1p $[CP] -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR15_1 Vbiasp -*.PININFO Vbiasp:O -RR1 Vbiasp gnd! res=rK -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn fully_differential_miller_compensated -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR15_1 Biasp CR15_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pnmos_4_cr16_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pnmos_4_cr16_1.sp deleted file mode 100644 index d87245b652..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pnmos_4_cr16_1.sp +++ /dev/null @@ -1,71 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:05:48 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_miller_compensated Vbiasn Vbiasp Vinn Vinp Voutn -+ Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM7 Voutp net15 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net22 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net22 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM8 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net22 Vinp net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net15 Vinn net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net21 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -CC1 Voutp net15 1p $[CP] -CC0 Voutn net22 1p $[CP] -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR16_1 Vbiasp -*.PININFO Vbiasp:O -RR0 vdd! net6 res=rK -RR1 Vbiasp gnd! res=rK -MM2 Vbiasp Vbiasp net6 vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn fully_differential_miller_compensated -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR16_1 Biasp CR16_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pnmos_4_cr2_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pnmos_4_cr2_2.sp deleted file mode 100644 index cd7610d067..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pnmos_4_cr2_2.sp +++ /dev/null @@ -1,73 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:05:48 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_miller_compensated Vbiasn Vbiasp Vinn Vinp Voutn -+ Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM7 Voutp net15 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net22 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net22 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM8 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net22 Vinp net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net15 Vinn net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net21 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -CC1 Voutp net15 1p $[CP] -CC0 Voutn net22 1p $[CP] -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR2_2_wilson Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -RR0 Vbiasn gnd! res=rK -MM2 Vbiasp net12 Vbiasn gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn fully_differential_miller_compensated -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR2_2_wilson Biasn Biasp CR2_2_wilson -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pnmos_4_cr3_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pnmos_4_cr3_2.sp deleted file mode 100644 index cfc5cb969c..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pnmos_4_cr3_2.sp +++ /dev/null @@ -1,73 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:05:48 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_miller_compensated Vbiasn Vbiasp Vinn Vinp Voutn -+ Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM7 Voutp net15 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net22 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net22 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM8 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net22 Vinp net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net15 Vinn net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net21 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -CC1 Voutp net15 1p $[CP] -CC0 Voutn net22 1p $[CP] -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR3_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 net15 gnd! res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn fully_differential_miller_compensated -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR3_2 Biasn Biasp CR3_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pnmos_4_cr4_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pnmos_4_cr4_2.sp deleted file mode 100644 index 7d787a2885..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pnmos_4_cr4_2.sp +++ /dev/null @@ -1,78 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:05:48 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_miller_compensated Vbiasn Vbiasp Vinn Vinp Voutn -+ Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM7 Voutp net15 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net22 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net22 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM8 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net22 Vinp net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net15 Vinn net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net21 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -CC1 Voutp net15 1p $[CP] -CC0 Voutn net22 1p $[CP] -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR4_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM11 net023 net024 Vbiasn gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM8 net025 net010 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM9 net024 net024 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM7 net010 net010 net025 gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net025 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 net024 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net010 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn fully_differential_miller_compensated -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR4_2 Biasn Biasp CR4_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pnmos_4_cr5_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pnmos_4_cr5_2.sp deleted file mode 100644 index 94c910e6ec..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pnmos_4_cr5_2.sp +++ /dev/null @@ -1,75 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:05:48 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_miller_compensated Vbiasn Vbiasp Vinn Vinp Voutn -+ Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM7 Voutp net15 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net22 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net22 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM8 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net22 Vinp net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net15 Vinn net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net21 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -CC1 Voutp net15 1p $[CP] -CC0 Voutn net22 1p $[CP] -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR5_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM5 net014 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net014 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn fully_differential_miller_compensated -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR5_2 Biasn Biasp CR5_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pnmos_4_cr6_3.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pnmos_4_cr6_3.sp deleted file mode 100644 index 4dfabafc35..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pnmos_4_cr6_3.sp +++ /dev/null @@ -1,75 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:05:48 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_miller_compensated Vbiasn Vbiasp Vinn Vinp Voutn -+ Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM7 Voutp net15 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net22 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net22 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM8 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net22 Vinp net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net15 Vinn net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net21 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -CC1 Voutp net15 1p $[CP] -CC0 Voutn net22 1p $[CP] -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR6_3 Vbiasn1 Vbiasn2 Vbiasp -*.PININFO Vbiasn1:O Vbiasn2:O Vbiasp:O -MM2 Vbiasp Vbiasn2 Vbiasn1 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn2 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 Vbiasn1 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM5 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn2 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn fully_differential_miller_compensated -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR6_3 Biasn1 Biasn2 Biasp CR6_3 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pnmos_cr13_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pnmos_cr13_1.sp deleted file mode 100644 index 26c329f562..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pnmos_cr13_1.sp +++ /dev/null @@ -1,72 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:05:48 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_miller_compensated Vbiasn Vbiasp Vinn Vinp Voutn -+ Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM7 Voutp net15 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net22 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net22 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM8 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net22 Vinp net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net15 Vinn net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net21 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -CC1 Voutp net15 1p $[CP] -CC0 Voutn net22 1p $[CP] -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn fully_differential_miller_compensated -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR13_2 Biasn Biasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pnmos_cr13_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pnmos_cr13_2.sp deleted file mode 100644 index 26c329f562..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pnmos_cr13_2.sp +++ /dev/null @@ -1,72 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:05:48 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_miller_compensated Vbiasn Vbiasp Vinn Vinp Voutn -+ Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM7 Voutp net15 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net22 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net22 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM8 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net22 Vinp net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net15 Vinn net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net21 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -CC1 Voutp net15 1p $[CP] -CC0 Voutn net22 1p $[CP] -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn fully_differential_miller_compensated -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR13_2 Biasn Biasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pnmos_cr14_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pnmos_cr14_2.sp deleted file mode 100644 index dad4aed808..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pnmos_cr14_2.sp +++ /dev/null @@ -1,73 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:05:48 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_miller_compensated Vbiasn Vbiasp Vinn Vinp Voutn -+ Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM7 Voutp net15 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net22 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net22 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM8 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net22 Vinp net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net15 Vinn net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net21 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -CC1 Voutp net15 1p $[CP] -CC0 Voutn net22 1p $[CP] -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR14_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net010 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 Vbiasn net010 res=rK -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn fully_differential_miller_compensated -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR14_2 Biasn Biasp CR14_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pnmos_cr15_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pnmos_cr15_1.sp deleted file mode 100644 index 75fefd3967..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pnmos_cr15_1.sp +++ /dev/null @@ -1,70 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:05:48 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_miller_compensated Vbiasn Vbiasp Vinn Vinp Voutn -+ Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM7 Voutp net15 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net22 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net22 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM8 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net22 Vinp net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net15 Vinn net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net21 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -CC1 Voutp net15 1p $[CP] -CC0 Voutn net22 1p $[CP] -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR15_1 Vbiasp -*.PININFO Vbiasp:O -RR1 Vbiasp gnd! res=rK -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn fully_differential_miller_compensated -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR15_1 Biasp CR15_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pnmos_cr16_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pnmos_cr16_1.sp deleted file mode 100644 index 1d8007e851..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pnmos_cr16_1.sp +++ /dev/null @@ -1,71 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:05:48 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_miller_compensated Vbiasn Vbiasp Vinn Vinp Voutn -+ Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM7 Voutp net15 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net22 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net22 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM8 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net22 Vinp net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net15 Vinn net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net21 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -CC1 Voutp net15 1p $[CP] -CC0 Voutn net22 1p $[CP] -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR16_1 Vbiasp -*.PININFO Vbiasp:O -RR0 vdd! net6 res=rK -RR1 Vbiasp gnd! res=rK -MM2 Vbiasp Vbiasp net6 vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn fully_differential_miller_compensated -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR16_1 Biasp CR16_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pnmos_cr2_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pnmos_cr2_2.sp deleted file mode 100644 index d86c46336d..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pnmos_cr2_2.sp +++ /dev/null @@ -1,73 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:05:48 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_miller_compensated Vbiasn Vbiasp Vinn Vinp Voutn -+ Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM7 Voutp net15 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net22 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net22 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM8 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net22 Vinp net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net15 Vinn net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net21 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -CC1 Voutp net15 1p $[CP] -CC0 Voutn net22 1p $[CP] -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR2_2_wilson Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -RR0 Vbiasn gnd! res=rK -MM2 Vbiasp net12 Vbiasn gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn fully_differential_miller_compensated -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR2_2_wilson Biasn Biasp CR2_2_wilson -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pnmos_cr3_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pnmos_cr3_2.sp deleted file mode 100644 index da4e52eb0e..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pnmos_cr3_2.sp +++ /dev/null @@ -1,73 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:05:48 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_miller_compensated Vbiasn Vbiasp Vinn Vinp Voutn -+ Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM7 Voutp net15 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net22 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net22 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM8 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net22 Vinp net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net15 Vinn net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net21 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -CC1 Voutp net15 1p $[CP] -CC0 Voutn net22 1p $[CP] -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR3_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 net15 gnd! res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn fully_differential_miller_compensated -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR3_2 Biasn Biasp CR3_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pnmos_cr4_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pnmos_cr4_2.sp deleted file mode 100644 index 521bb3fbef..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pnmos_cr4_2.sp +++ /dev/null @@ -1,78 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:05:48 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_miller_compensated Vbiasn Vbiasp Vinn Vinp Voutn -+ Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM7 Voutp net15 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net22 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net22 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM8 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net22 Vinp net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net15 Vinn net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net21 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -CC1 Voutp net15 1p $[CP] -CC0 Voutn net22 1p $[CP] -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR4_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM11 net023 net024 Vbiasn gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM8 net025 net010 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM9 net024 net024 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM7 net010 net010 net025 gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net025 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 net024 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net010 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn fully_differential_miller_compensated -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR4_2 Biasn Biasp CR4_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pnmos_cr5_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pnmos_cr5_2.sp deleted file mode 100644 index 74ffa44796..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pnmos_cr5_2.sp +++ /dev/null @@ -1,75 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:05:48 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_miller_compensated Vbiasn Vbiasp Vinn Vinp Voutn -+ Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM7 Voutp net15 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net22 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net22 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM8 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net22 Vinp net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net15 Vinn net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net21 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -CC1 Voutp net15 1p $[CP] -CC0 Voutn net22 1p $[CP] -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR5_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM5 net014 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net014 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn fully_differential_miller_compensated -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR5_2 Biasn Biasp CR5_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pnmos_cr6_3.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pnmos_cr6_3.sp deleted file mode 100644 index dd5559fc41..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_miller_compensated_LG_pnmos_cr6_3.sp +++ /dev/null @@ -1,75 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:05:48 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_miller_compensated Vbiasn Vbiasp Vinn Vinp Voutn -+ Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM7 Voutp net15 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net22 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net22 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM8 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net22 Vinp net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net15 Vinn net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net21 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -CC1 Voutp net15 1p $[CP] -CC0 Voutn net22 1p $[CP] -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR6_3 Vbiasn1 Vbiasn2 Vbiasp -*.PININFO Vbiasn1:O Vbiasn2:O Vbiasp:O -MM2 Vbiasp Vbiasn2 Vbiasn1 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn2 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 Vbiasn1 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM5 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn2 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn fully_differential_miller_compensated -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR6_3 Biasn1 Biasn2 Biasp CR6_3 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_nmos_cr13_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_nmos_cr13_1.sp deleted file mode 100644 index 954c4bd177..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_nmos_cr13_1.sp +++ /dev/null @@ -1,61 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:06:01 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_pmos Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Vbiasn:O Voutn:O Voutp:O -MM7 Voutp Vinn net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vinp net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM5 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos Biasp Vbiasn -*.PININFO Biasp:I Vbiasn:O -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_pmos -xiLG_nmos Biasp LG_Vbiasn LG_nmos -xibCR13_2 Biasn Biasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_nmos_cr13_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_nmos_cr13_2.sp deleted file mode 100644 index 954c4bd177..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_nmos_cr13_2.sp +++ /dev/null @@ -1,61 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:06:01 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_pmos Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Vbiasn:O Voutn:O Voutp:O -MM7 Voutp Vinn net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vinp net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM5 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos Biasp Vbiasn -*.PININFO Biasp:I Vbiasn:O -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_pmos -xiLG_nmos Biasp LG_Vbiasn LG_nmos -xibCR13_2 Biasn Biasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_nmos_cr14_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_nmos_cr14_2.sp deleted file mode 100644 index 23b8f59192..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_nmos_cr14_2.sp +++ /dev/null @@ -1,62 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:06:01 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_pmos Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Vbiasn:O Voutn:O Voutp:O -MM7 Voutp Vinn net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vinp net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM5 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos Biasp Vbiasn -*.PININFO Biasp:I Vbiasn:O -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR14_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net010 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 Vbiasn net010 res=rK -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_pmos -xiLG_nmos Biasp LG_Vbiasn LG_nmos -xibCR14_2 Biasn Biasp CR14_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_nmos_cr15_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_nmos_cr15_1.sp deleted file mode 100644 index abfebd9a40..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_nmos_cr15_1.sp +++ /dev/null @@ -1,59 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:06:01 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_pmos Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Vbiasn:O Voutn:O Voutp:O -MM7 Voutp Vinn net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vinp net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM5 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos Biasp Vbiasn -*.PININFO Biasp:I Vbiasn:O -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR15_1 Vbiasp -*.PININFO Vbiasp:O -RR1 Vbiasp gnd! res=rK -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_pmos -xiLG_nmos Biasp LG_Vbiasn LG_nmos -xibCR15_1 Biasp CR15_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_nmos_cr16_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_nmos_cr16_1.sp deleted file mode 100644 index 55359e8a60..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_nmos_cr16_1.sp +++ /dev/null @@ -1,60 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:06:01 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_pmos Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Vbiasn:O Voutn:O Voutp:O -MM7 Voutp Vinn net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vinp net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM5 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos Biasp Vbiasn -*.PININFO Biasp:I Vbiasn:O -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR16_1 Vbiasp -*.PININFO Vbiasp:O -RR0 vdd! net6 res=rK -RR1 Vbiasp gnd! res=rK -MM2 Vbiasp Vbiasp net6 vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_pmos -xiLG_nmos Biasp LG_Vbiasn LG_nmos -xibCR16_1 Biasp CR16_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_nmos_cr2_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_nmos_cr2_2.sp deleted file mode 100644 index 7602396e24..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_nmos_cr2_2.sp +++ /dev/null @@ -1,62 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:06:01 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_pmos Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Vbiasn:O Voutn:O Voutp:O -MM7 Voutp Vinn net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vinp net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM5 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos Biasp Vbiasn -*.PININFO Biasp:I Vbiasn:O -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR2_2_wilson Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -RR0 Vbiasn gnd! res=rK -MM2 Vbiasp net12 Vbiasn gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_pmos -xiLG_nmos Biasp LG_Vbiasn LG_nmos -xibCR2_2_wilson Biasn Biasp CR2_2_wilson -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_nmos_cr3_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_nmos_cr3_2.sp deleted file mode 100644 index bb0f4bab37..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_nmos_cr3_2.sp +++ /dev/null @@ -1,62 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:06:01 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_pmos Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Vbiasn:O Voutn:O Voutp:O -MM7 Voutp Vinn net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vinp net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM5 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos Biasp Vbiasn -*.PININFO Biasp:I Vbiasn:O -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR3_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 net15 gnd! res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_pmos -xiLG_nmos Biasp LG_Vbiasn LG_nmos -xibCR3_2 Biasn Biasp CR3_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_nmos_cr4_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_nmos_cr4_2.sp deleted file mode 100644 index a3ef960049..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_nmos_cr4_2.sp +++ /dev/null @@ -1,67 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:06:01 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_pmos Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Vbiasn:O Voutn:O Voutp:O -MM7 Voutp Vinn net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vinp net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM5 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos Biasp Vbiasn -*.PININFO Biasp:I Vbiasn:O -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR4_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM11 net023 net024 Vbiasn gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM8 net025 net010 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM9 net024 net024 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM7 net010 net010 net025 gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net025 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 net024 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net010 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_pmos -xiLG_nmos Biasp LG_Vbiasn LG_nmos -xibCR4_2 Biasn Biasp CR4_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_nmos_cr5_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_nmos_cr5_2.sp deleted file mode 100644 index d4ab6be361..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_nmos_cr5_2.sp +++ /dev/null @@ -1,64 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:06:01 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_pmos Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Vbiasn:O Voutn:O Voutp:O -MM7 Voutp Vinn net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vinp net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM5 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos Biasp Vbiasn -*.PININFO Biasp:I Vbiasn:O -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR5_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM5 net014 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net014 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_pmos -xiLG_nmos Biasp LG_Vbiasn LG_nmos -xibCR5_2 Biasn Biasp CR5_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_nmos_cr6_3.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_nmos_cr6_3.sp deleted file mode 100644 index c07ee6511e..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_nmos_cr6_3.sp +++ /dev/null @@ -1,64 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:06:01 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_pmos Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Vbiasn:O Voutn:O Voutp:O -MM7 Voutp Vinn net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vinp net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM5 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos Biasp Vbiasn -*.PININFO Biasp:I Vbiasn:O -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR6_3 Vbiasn1 Vbiasn2 Vbiasp -*.PININFO Vbiasn1:O Vbiasn2:O Vbiasp:O -MM2 Vbiasp Vbiasn2 Vbiasn1 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn2 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 Vbiasn1 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM5 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn2 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_pmos -xiLG_nmos Biasp LG_Vbiasn LG_nmos -xibCR6_3 Biasn1 Biasn2 Biasp CR6_3 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_nmos_l1_cr11_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_nmos_l1_cr11_1.sp deleted file mode 100644 index 4a6cb1a529..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_nmos_l1_cr11_1.sp +++ /dev/null @@ -1,64 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:06:01 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_pmos Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Vbiasn:O Voutn:O Voutp:O -MM7 Voutp Vinn net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vinp net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM5 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR11_1 Vbiasn -*.PININFO Vbiasn:O -RRF vdd! Vbiasn res=rK -MM1 net9 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net9 net9 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn net9 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_pmos -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR11_1 Biasn CR11_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_nmos_l1_cr12_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_nmos_l1_cr12_1.sp deleted file mode 100644 index f0915459b8..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_nmos_l1_cr12_1.sp +++ /dev/null @@ -1,64 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:06:01 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_pmos Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Vbiasn:O Voutn:O Voutp:O -MM7 Voutp Vinn net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vinp net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM5 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR12_1 Vbiasn -*.PININFO Vbiasn:O -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 net10 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn net10 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RRF vdd! Vbiasn res=rK -RR0 vdd! net10 res=rK -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_pmos -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR12_1 Biasn CR12_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_nmos_l1_cr13_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_nmos_l1_cr13_1.sp deleted file mode 100644 index 7e5d5beb7f..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_nmos_l1_cr13_1.sp +++ /dev/null @@ -1,63 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:06:01 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_pmos Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Vbiasn:O Voutn:O Voutp:O -MM7 Voutp Vinn net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vinp net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM5 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_pmos -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR13_2 Biasn Vbiasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_nmos_l1_cr13_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_nmos_l1_cr13_2.sp deleted file mode 100644 index 7e5d5beb7f..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_nmos_l1_cr13_2.sp +++ /dev/null @@ -1,63 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:06:01 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_pmos Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Vbiasn:O Voutn:O Voutp:O -MM7 Voutp Vinn net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vinp net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM5 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_pmos -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR13_2 Biasn Vbiasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_nmos_l1_cr14_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_nmos_l1_cr14_2.sp deleted file mode 100644 index f3e417fa1a..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_nmos_l1_cr14_2.sp +++ /dev/null @@ -1,64 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:06:01 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_pmos Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Vbiasn:O Voutn:O Voutp:O -MM7 Voutp Vinn net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vinp net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM5 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR14_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net010 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 Vbiasn net010 res=rK -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_pmos -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR14_2 Biasn Vbiasp CR14_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_nmos_l1_cr1_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_nmos_l1_cr1_1.sp deleted file mode 100644 index 66b58265a4..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_nmos_l1_cr1_1.sp +++ /dev/null @@ -1,61 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:06:01 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_pmos Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Vbiasn:O Voutn:O Voutp:O -MM7 Voutp Vinn net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vinp net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM5 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR1_1 Vbiasn -*.PININFO Vbiasn:O -RRF vdd! Vbiasn res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_pmos -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR1_1 Biasn CR1_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_nmos_l1_cr2_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_nmos_l1_cr2_2.sp deleted file mode 100644 index 08280ab8db..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_nmos_l1_cr2_2.sp +++ /dev/null @@ -1,64 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:06:01 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_pmos Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Vbiasn:O Voutn:O Voutp:O -MM7 Voutp Vinn net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vinp net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM5 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR2_2_wilson Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -RR0 Vbiasn gnd! res=rK -MM2 Vbiasp net12 Vbiasn gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_pmos -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR2_2_wilson Biasn Vbiasp CR2_2_wilson -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_nmos_l1_cr3_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_nmos_l1_cr3_2.sp deleted file mode 100644 index 07ae59d1f9..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_nmos_l1_cr3_2.sp +++ /dev/null @@ -1,64 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:06:01 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_pmos Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Vbiasn:O Voutn:O Voutp:O -MM7 Voutp Vinn net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vinp net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM5 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR3_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 net15 gnd! res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_pmos -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR3_2 Biasn Vbiasp CR3_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_nmos_l1_cr4_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_nmos_l1_cr4_2.sp deleted file mode 100644 index f96622f0c5..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_nmos_l1_cr4_2.sp +++ /dev/null @@ -1,69 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:06:01 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_pmos Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Vbiasn:O Voutn:O Voutp:O -MM7 Voutp Vinn net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vinp net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM5 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR4_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM11 net023 net024 Vbiasn gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM8 net025 net010 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM9 net024 net024 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM7 net010 net010 net025 gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net025 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 net024 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net010 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_pmos -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR4_2 Biasn Vbiasp CR4_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_nmos_l1_cr5_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_nmos_l1_cr5_2.sp deleted file mode 100644 index b8e649e55e..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_nmos_l1_cr5_2.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:06:01 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_pmos Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Vbiasn:O Voutn:O Voutp:O -MM7 Voutp Vinn net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vinp net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM5 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR5_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM5 net014 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net014 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_pmos -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR5_2 Biasn Vbiasp CR5_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_nmos_l1_cr7_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_nmos_l1_cr7_1.sp deleted file mode 100644 index 1b31e01fed..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_nmos_l1_cr7_1.sp +++ /dev/null @@ -1,64 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:06:01 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_pmos Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Vbiasn:O Voutn:O Voutp:O -MM7 Voutp Vinn net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vinp net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM5 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR7_1 Vbiasn -*.PININFO Vbiasn:O -RR1 Vbiasn net7 res=rK -RR0 vdd! net7 res=rK -RRF vdd! Vbiasn res=rK -MM1 net7 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_pmos -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR7_1 Biasn CR7_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_nmos_l1_cr9_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_nmos_l1_cr9_1.sp deleted file mode 100644 index 914dfd769a..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_nmos_l1_cr9_1.sp +++ /dev/null @@ -1,62 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:06:01 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_pmos Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Vbiasn:O Voutn:O Voutp:O -MM7 Voutp Vinn net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vinp net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM5 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR9_1 Vbiasn -*.PININFO Vbiasn:O -RR1 net05 gnd! res=rK -RRF vdd! Vbiasn res=rK -MM0 Vbiasn Vbiasn net05 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_pmos -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR9_1 Biasn CR9_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_npmos_cr11_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_npmos_cr11_1.sp deleted file mode 100644 index f582a5dd1c..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_npmos_cr11_1.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:06:01 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_pmos Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Vbiasn:O Voutn:O Voutp:O -MM7 Voutp Vinn net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vinp net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM5 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR11_1 Vbiasn -*.PININFO Vbiasn:O -RRF vdd! Vbiasn res=rK -MM1 net9 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net9 net9 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn net9 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_pmos -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR11_1 Biasn CR11_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_npmos_cr12_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_npmos_cr12_1.sp deleted file mode 100644 index e65885f183..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_npmos_cr12_1.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:06:01 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_pmos Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Vbiasn:O Voutn:O Voutp:O -MM7 Voutp Vinn net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vinp net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM5 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR12_1 Vbiasn -*.PININFO Vbiasn:O -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 net10 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn net10 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RRF vdd! Vbiasn res=rK -RR0 vdd! net10 res=rK -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_pmos -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR12_1 Biasn CR12_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_npmos_cr13_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_npmos_cr13_1.sp deleted file mode 100644 index c7f28b902d..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_npmos_cr13_1.sp +++ /dev/null @@ -1,65 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:06:01 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_pmos Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Vbiasn:O Voutn:O Voutp:O -MM7 Voutp Vinn net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vinp net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM5 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_pmos -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR13_2 Biasn Vbiasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_npmos_cr13_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_npmos_cr13_2.sp deleted file mode 100644 index c7f28b902d..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_npmos_cr13_2.sp +++ /dev/null @@ -1,65 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:06:01 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_pmos Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Vbiasn:O Voutn:O Voutp:O -MM7 Voutp Vinn net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vinp net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM5 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_pmos -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR13_2 Biasn Vbiasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_npmos_cr14_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_npmos_cr14_2.sp deleted file mode 100644 index bb64ffd9c5..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_npmos_cr14_2.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:06:01 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_pmos Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Vbiasn:O Voutn:O Voutp:O -MM7 Voutp Vinn net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vinp net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM5 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR14_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net010 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 Vbiasn net010 res=rK -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_pmos -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR14_2 Biasn Vbiasp CR14_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_npmos_cr1_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_npmos_cr1_1.sp deleted file mode 100644 index e2bd80e08e..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_npmos_cr1_1.sp +++ /dev/null @@ -1,63 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:06:01 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_pmos Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Vbiasn:O Voutn:O Voutp:O -MM7 Voutp Vinn net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vinp net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM5 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR1_1 Vbiasn -*.PININFO Vbiasn:O -RRF vdd! Vbiasn res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_pmos -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR1_1 Biasn CR1_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_npmos_cr2_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_npmos_cr2_2.sp deleted file mode 100644 index 575da6f59b..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_npmos_cr2_2.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:06:01 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_pmos Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Vbiasn:O Voutn:O Voutp:O -MM7 Voutp Vinn net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vinp net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM5 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR2_2_wilson Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -RR0 Vbiasn gnd! res=rK -MM2 Vbiasp net12 Vbiasn gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_pmos -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR2_2_wilson Biasn Vbiasp CR2_2_wilson -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_npmos_cr3_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_npmos_cr3_2.sp deleted file mode 100644 index 5bc0daddbd..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_npmos_cr3_2.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:06:01 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_pmos Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Vbiasn:O Voutn:O Voutp:O -MM7 Voutp Vinn net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vinp net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM5 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR3_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 net15 gnd! res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_pmos -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR3_2 Biasn Vbiasp CR3_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_npmos_cr4_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_npmos_cr4_2.sp deleted file mode 100644 index 651fb937bb..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_npmos_cr4_2.sp +++ /dev/null @@ -1,71 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:06:01 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_pmos Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Vbiasn:O Voutn:O Voutp:O -MM7 Voutp Vinn net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vinp net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM5 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR4_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM11 net023 net024 Vbiasn gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM8 net025 net010 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM9 net024 net024 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM7 net010 net010 net025 gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net025 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 net024 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net010 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_pmos -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR4_2 Biasn Vbiasp CR4_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_npmos_cr5_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_npmos_cr5_2.sp deleted file mode 100644 index a4a3c4ea44..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_npmos_cr5_2.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:06:01 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_pmos Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Vbiasn:O Voutn:O Voutp:O -MM7 Voutp Vinn net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vinp net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM5 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR5_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM5 net014 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net014 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_pmos -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR5_2 Biasn Vbiasp CR5_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_npmos_cr7_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_npmos_cr7_1.sp deleted file mode 100644 index 6eb80cdd34..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_npmos_cr7_1.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:06:01 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_pmos Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Vbiasn:O Voutn:O Voutp:O -MM7 Voutp Vinn net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vinp net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM5 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR7_1 Vbiasn -*.PININFO Vbiasn:O -RR1 Vbiasn net7 res=rK -RR0 vdd! net7 res=rK -RRF vdd! Vbiasn res=rK -MM1 net7 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_pmos -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR7_1 Biasn CR7_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_npmos_cr9_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_npmos_cr9_1.sp deleted file mode 100644 index 1a5c54c8de..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_npmos_cr9_1.sp +++ /dev/null @@ -1,64 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:06:01 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_pmos Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Vbiasn:O Voutn:O Voutp:O -MM7 Voutp Vinn net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vinp net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM5 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR9_1 Vbiasn -*.PININFO Vbiasn:O -RR1 net05 gnd! res=rK -RRF vdd! Vbiasn res=rK -MM0 Vbiasn Vbiasn net05 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_pmos -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR9_1 Biasn CR9_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pmos_cr11_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pmos_cr11_1.sp deleted file mode 100644 index f80dc03090..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pmos_cr11_1.sp +++ /dev/null @@ -1,62 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:06:01 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_pmos Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Vbiasn:O Voutn:O Voutp:O -MM7 Voutp Vinn net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vinp net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM5 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos Biasn Vbiasp -*.PININFO Biasn:I Vbiasp:O -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR11_1 Vbiasn -*.PININFO Vbiasn:O -RRF vdd! Vbiasn res=rK -MM1 net9 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net9 net9 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn net9 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_pmos -xiLG_pmos Biasn LG_Vbiasp LG_pmos -xibCR11_1 Biasn CR11_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pmos_cr12_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pmos_cr12_1.sp deleted file mode 100644 index 2be63fe4a4..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pmos_cr12_1.sp +++ /dev/null @@ -1,62 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:06:01 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_pmos Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Vbiasn:O Voutn:O Voutp:O -MM7 Voutp Vinn net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vinp net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM5 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos Biasn Vbiasp -*.PININFO Biasn:I Vbiasp:O -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR12_1 Vbiasn -*.PININFO Vbiasn:O -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 net10 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn net10 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RRF vdd! Vbiasn res=rK -RR0 vdd! net10 res=rK -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_pmos -xiLG_pmos Biasn LG_Vbiasp LG_pmos -xibCR12_1 Biasn CR12_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pmos_cr13_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pmos_cr13_1.sp deleted file mode 100644 index 2e498b1ff9..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pmos_cr13_1.sp +++ /dev/null @@ -1,61 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:06:01 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_pmos Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Vbiasn:O Voutn:O Voutp:O -MM7 Voutp Vinn net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vinp net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM5 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos Biasn Vbiasp -*.PININFO Biasn:I Vbiasp:O -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_pmos -xiLG_pmos Biasn LG_Vbiasp LG_pmos -xibCR13_2 Biasn Vbiasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pmos_cr13_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pmos_cr13_2.sp deleted file mode 100644 index 2e498b1ff9..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pmos_cr13_2.sp +++ /dev/null @@ -1,61 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:06:01 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_pmos Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Vbiasn:O Voutn:O Voutp:O -MM7 Voutp Vinn net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vinp net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM5 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos Biasn Vbiasp -*.PININFO Biasn:I Vbiasp:O -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_pmos -xiLG_pmos Biasn LG_Vbiasp LG_pmos -xibCR13_2 Biasn Vbiasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pmos_cr14_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pmos_cr14_2.sp deleted file mode 100644 index 53ae6f66c2..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pmos_cr14_2.sp +++ /dev/null @@ -1,62 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:06:01 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_pmos Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Vbiasn:O Voutn:O Voutp:O -MM7 Voutp Vinn net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vinp net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM5 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos Biasn Vbiasp -*.PININFO Biasn:I Vbiasp:O -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR14_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net010 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 Vbiasn net010 res=rK -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_pmos -xiLG_pmos Biasn LG_Vbiasp LG_pmos -xibCR14_2 Biasn Vbiasp CR14_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pmos_cr1_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pmos_cr1_1.sp deleted file mode 100644 index 279d5ff915..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pmos_cr1_1.sp +++ /dev/null @@ -1,59 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:06:01 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_pmos Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Vbiasn:O Voutn:O Voutp:O -MM7 Voutp Vinn net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vinp net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM5 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos Biasn Vbiasp -*.PININFO Biasn:I Vbiasp:O -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR1_1 Vbiasn -*.PININFO Vbiasn:O -RRF vdd! Vbiasn res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_pmos -xiLG_pmos Biasn LG_Vbiasp LG_pmos -xibCR1_1 Biasn CR1_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pmos_cr2_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pmos_cr2_2.sp deleted file mode 100644 index 4e51d4febc..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pmos_cr2_2.sp +++ /dev/null @@ -1,62 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:06:01 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_pmos Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Vbiasn:O Voutn:O Voutp:O -MM7 Voutp Vinn net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vinp net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM5 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos Biasn Vbiasp -*.PININFO Biasn:I Vbiasp:O -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR2_2_wilson Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -RR0 Vbiasn gnd! res=rK -MM2 Vbiasp net12 Vbiasn gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_pmos -xiLG_pmos Biasn LG_Vbiasp LG_pmos -xibCR2_2_wilson Biasn Vbiasp CR2_2_wilson -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pmos_cr3_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pmos_cr3_2.sp deleted file mode 100644 index 98f8d4388b..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pmos_cr3_2.sp +++ /dev/null @@ -1,62 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:06:01 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_pmos Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Vbiasn:O Voutn:O Voutp:O -MM7 Voutp Vinn net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vinp net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM5 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos Biasn Vbiasp -*.PININFO Biasn:I Vbiasp:O -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR3_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 net15 gnd! res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_pmos -xiLG_pmos Biasn LG_Vbiasp LG_pmos -xibCR3_2 Biasn Vbiasp CR3_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pmos_cr4_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pmos_cr4_2.sp deleted file mode 100644 index 8c2435046c..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pmos_cr4_2.sp +++ /dev/null @@ -1,67 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:06:01 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_pmos Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Vbiasn:O Voutn:O Voutp:O -MM7 Voutp Vinn net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vinp net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM5 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos Biasn Vbiasp -*.PININFO Biasn:I Vbiasp:O -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR4_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM11 net023 net024 Vbiasn gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM8 net025 net010 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM9 net024 net024 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM7 net010 net010 net025 gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net025 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 net024 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net010 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_pmos -xiLG_pmos Biasn LG_Vbiasp LG_pmos -xibCR4_2 Biasn Vbiasp CR4_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pmos_cr5_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pmos_cr5_2.sp deleted file mode 100644 index f2d9d48c34..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pmos_cr5_2.sp +++ /dev/null @@ -1,64 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:06:01 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_pmos Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Vbiasn:O Voutn:O Voutp:O -MM7 Voutp Vinn net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vinp net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM5 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos Biasn Vbiasp -*.PININFO Biasn:I Vbiasp:O -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR5_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM5 net014 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net014 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_pmos -xiLG_pmos Biasn LG_Vbiasp LG_pmos -xibCR5_2 Biasn Vbiasp CR5_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pmos_cr7_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pmos_cr7_1.sp deleted file mode 100644 index 32d351a3b8..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pmos_cr7_1.sp +++ /dev/null @@ -1,62 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:06:01 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_pmos Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Vbiasn:O Voutn:O Voutp:O -MM7 Voutp Vinn net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vinp net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM5 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos Biasn Vbiasp -*.PININFO Biasn:I Vbiasp:O -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR7_1 Vbiasn -*.PININFO Vbiasn:O -RR1 Vbiasn net7 res=rK -RR0 vdd! net7 res=rK -RRF vdd! Vbiasn res=rK -MM1 net7 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_pmos -xiLG_pmos Biasn LG_Vbiasp LG_pmos -xibCR7_1 Biasn CR7_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pmos_cr9_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pmos_cr9_1.sp deleted file mode 100644 index 085be69ee7..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pmos_cr9_1.sp +++ /dev/null @@ -1,60 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:06:01 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_pmos Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Vbiasn:O Voutn:O Voutp:O -MM7 Voutp Vinn net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vinp net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM5 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos Biasn Vbiasp -*.PININFO Biasn:I Vbiasp:O -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR9_1 Vbiasn -*.PININFO Vbiasn:O -RR1 net05 gnd! res=rK -RRF vdd! Vbiasn res=rK -MM0 Vbiasn Vbiasn net05 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_pmos -xiLG_pmos Biasn LG_Vbiasp LG_pmos -xibCR9_1 Biasn CR9_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pmos_l1_cr13_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pmos_l1_cr13_1.sp deleted file mode 100644 index 96634d3ee2..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pmos_l1_cr13_1.sp +++ /dev/null @@ -1,63 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:06:01 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_pmos Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Vbiasn:O Voutn:O Voutp:O -MM7 Voutp Vinn net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vinp net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM5 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_pmos -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR13_2 Biasn Biasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pmos_l1_cr13_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pmos_l1_cr13_2.sp deleted file mode 100644 index 96634d3ee2..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pmos_l1_cr13_2.sp +++ /dev/null @@ -1,63 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:06:01 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_pmos Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Vbiasn:O Voutn:O Voutp:O -MM7 Voutp Vinn net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vinp net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM5 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_pmos -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR13_2 Biasn Biasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pmos_l1_cr14_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pmos_l1_cr14_2.sp deleted file mode 100644 index ee2c78203d..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pmos_l1_cr14_2.sp +++ /dev/null @@ -1,64 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:06:01 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_pmos Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Vbiasn:O Voutn:O Voutp:O -MM7 Voutp Vinn net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vinp net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM5 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR14_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net010 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 Vbiasn net010 res=rK -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_pmos -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR14_2 Biasn Biasp CR14_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pmos_l1_cr15_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pmos_l1_cr15_1.sp deleted file mode 100644 index 1207d7883e..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pmos_l1_cr15_1.sp +++ /dev/null @@ -1,61 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:06:01 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_pmos Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Vbiasn:O Voutn:O Voutp:O -MM7 Voutp Vinn net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vinp net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM5 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR15_1 Vbiasp -*.PININFO Vbiasp:O -RR1 Vbiasp gnd! res=rK -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_pmos -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR15_1 Biasp CR15_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pmos_l1_cr16_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pmos_l1_cr16_1.sp deleted file mode 100644 index 47b28b98f3..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pmos_l1_cr16_1.sp +++ /dev/null @@ -1,62 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:06:01 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_pmos Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Vbiasn:O Voutn:O Voutp:O -MM7 Voutp Vinn net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vinp net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM5 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR16_1 Vbiasp -*.PININFO Vbiasp:O -RR0 vdd! net6 res=rK -RR1 Vbiasp gnd! res=rK -MM2 Vbiasp Vbiasp net6 vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_pmos -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR16_1 Biasp CR16_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pmos_l1_cr2_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pmos_l1_cr2_2.sp deleted file mode 100644 index bb24d27823..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pmos_l1_cr2_2.sp +++ /dev/null @@ -1,64 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:06:01 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_pmos Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Vbiasn:O Voutn:O Voutp:O -MM7 Voutp Vinn net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vinp net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM5 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR2_2_wilson Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -RR0 Vbiasn gnd! res=rK -MM2 Vbiasp net12 Vbiasn gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_pmos -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR2_2_wilson Biasn Biasp CR2_2_wilson -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pmos_l1_cr3_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pmos_l1_cr3_2.sp deleted file mode 100644 index ebcb56f636..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pmos_l1_cr3_2.sp +++ /dev/null @@ -1,64 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:06:01 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_pmos Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Vbiasn:O Voutn:O Voutp:O -MM7 Voutp Vinn net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vinp net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM5 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR3_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 net15 gnd! res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_pmos -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR3_2 Biasn Biasp CR3_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pmos_l1_cr4_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pmos_l1_cr4_2.sp deleted file mode 100644 index c63c4eb9f1..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pmos_l1_cr4_2.sp +++ /dev/null @@ -1,69 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:06:01 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_pmos Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Vbiasn:O Voutn:O Voutp:O -MM7 Voutp Vinn net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vinp net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM5 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR4_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM11 net023 net024 Vbiasn gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM8 net025 net010 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM9 net024 net024 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM7 net010 net010 net025 gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net025 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 net024 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net010 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_pmos -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR4_2 Biasn Biasp CR4_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pmos_l1_cr5_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pmos_l1_cr5_2.sp deleted file mode 100644 index 4d8319245f..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pmos_l1_cr5_2.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:06:01 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_pmos Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Vbiasn:O Voutn:O Voutp:O -MM7 Voutp Vinn net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vinp net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM5 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR5_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM5 net014 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net014 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_pmos -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR5_2 Biasn Biasp CR5_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pmos_l1_cr6_3.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pmos_l1_cr6_3.sp deleted file mode 100644 index 0e59dc5467..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pmos_l1_cr6_3.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:06:01 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_pmos Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Vbiasn:O Voutn:O Voutp:O -MM7 Voutp Vinn net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vinp net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM5 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR6_3 Vbiasn1 Vbiasn2 Vbiasp -*.PININFO Vbiasn1:O Vbiasn2:O Vbiasp:O -MM2 Vbiasp Vbiasn2 Vbiasn1 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn2 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 Vbiasn1 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM5 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn2 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_pmos -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR6_3 Biasn1 Biasn2 Biasp CR6_3 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pnmos_4_cr13_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pnmos_4_cr13_1.sp deleted file mode 100644 index f29bcc5275..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pnmos_4_cr13_1.sp +++ /dev/null @@ -1,65 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:06:01 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_pmos Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Vbiasn:O Voutn:O Voutp:O -MM7 Voutp Vinn net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vinp net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM5 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_pmos -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR13_2 Biasn Biasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pnmos_4_cr13_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pnmos_4_cr13_2.sp deleted file mode 100644 index f29bcc5275..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pnmos_4_cr13_2.sp +++ /dev/null @@ -1,65 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:06:01 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_pmos Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Vbiasn:O Voutn:O Voutp:O -MM7 Voutp Vinn net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vinp net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM5 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_pmos -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR13_2 Biasn Biasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pnmos_4_cr14_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pnmos_4_cr14_2.sp deleted file mode 100644 index d92a83fa2d..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pnmos_4_cr14_2.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:06:01 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_pmos Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Vbiasn:O Voutn:O Voutp:O -MM7 Voutp Vinn net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vinp net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM5 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR14_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net010 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 Vbiasn net010 res=rK -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_pmos -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR14_2 Biasn Biasp CR14_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pnmos_4_cr15_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pnmos_4_cr15_1.sp deleted file mode 100644 index 660b1815b4..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pnmos_4_cr15_1.sp +++ /dev/null @@ -1,63 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:06:01 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_pmos Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Vbiasn:O Voutn:O Voutp:O -MM7 Voutp Vinn net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vinp net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM5 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR15_1 Vbiasp -*.PININFO Vbiasp:O -RR1 Vbiasp gnd! res=rK -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_pmos -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR15_1 Biasp CR15_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pnmos_4_cr16_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pnmos_4_cr16_1.sp deleted file mode 100644 index f7ed2208a1..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pnmos_4_cr16_1.sp +++ /dev/null @@ -1,64 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:06:01 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_pmos Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Vbiasn:O Voutn:O Voutp:O -MM7 Voutp Vinn net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vinp net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM5 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR16_1 Vbiasp -*.PININFO Vbiasp:O -RR0 vdd! net6 res=rK -RR1 Vbiasp gnd! res=rK -MM2 Vbiasp Vbiasp net6 vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_pmos -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR16_1 Biasp CR16_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pnmos_4_cr2_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pnmos_4_cr2_2.sp deleted file mode 100644 index 7224668691..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pnmos_4_cr2_2.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:06:01 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_pmos Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Vbiasn:O Voutn:O Voutp:O -MM7 Voutp Vinn net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vinp net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM5 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR2_2_wilson Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -RR0 Vbiasn gnd! res=rK -MM2 Vbiasp net12 Vbiasn gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_pmos -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR2_2_wilson Biasn Biasp CR2_2_wilson -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pnmos_4_cr3_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pnmos_4_cr3_2.sp deleted file mode 100644 index 3b6cdc5703..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pnmos_4_cr3_2.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:06:01 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_pmos Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Vbiasn:O Voutn:O Voutp:O -MM7 Voutp Vinn net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vinp net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM5 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR3_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 net15 gnd! res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_pmos -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR3_2 Biasn Biasp CR3_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pnmos_4_cr4_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pnmos_4_cr4_2.sp deleted file mode 100644 index a610560877..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pnmos_4_cr4_2.sp +++ /dev/null @@ -1,71 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:06:01 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_pmos Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Vbiasn:O Voutn:O Voutp:O -MM7 Voutp Vinn net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vinp net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM5 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR4_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM11 net023 net024 Vbiasn gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM8 net025 net010 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM9 net024 net024 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM7 net010 net010 net025 gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net025 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 net024 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net010 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_pmos -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR4_2 Biasn Biasp CR4_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pnmos_4_cr5_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pnmos_4_cr5_2.sp deleted file mode 100644 index 48f46e8bf4..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pnmos_4_cr5_2.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:06:01 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_pmos Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Vbiasn:O Voutn:O Voutp:O -MM7 Voutp Vinn net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vinp net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM5 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR5_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM5 net014 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net014 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_pmos -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR5_2 Biasn Biasp CR5_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pnmos_4_cr6_3.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pnmos_4_cr6_3.sp deleted file mode 100644 index 7f8c2b87a9..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pnmos_4_cr6_3.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:06:01 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_pmos Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Vbiasn:O Voutn:O Voutp:O -MM7 Voutp Vinn net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vinp net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM5 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR6_3 Vbiasn1 Vbiasn2 Vbiasp -*.PININFO Vbiasn1:O Vbiasn2:O Vbiasp:O -MM2 Vbiasp Vbiasn2 Vbiasn1 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn2 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 Vbiasn1 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM5 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn2 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_pmos -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR6_3 Biasn1 Biasn2 Biasp CR6_3 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pnmos_cr13_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pnmos_cr13_1.sp deleted file mode 100644 index 6274a890bd..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pnmos_cr13_1.sp +++ /dev/null @@ -1,65 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:06:01 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_pmos Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Vbiasn:O Voutn:O Voutp:O -MM7 Voutp Vinn net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vinp net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM5 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_pmos -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR13_2 Biasn Biasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pnmos_cr13_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pnmos_cr13_2.sp deleted file mode 100644 index 6274a890bd..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pnmos_cr13_2.sp +++ /dev/null @@ -1,65 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:06:01 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_pmos Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Vbiasn:O Voutn:O Voutp:O -MM7 Voutp Vinn net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vinp net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM5 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_pmos -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR13_2 Biasn Biasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pnmos_cr14_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pnmos_cr14_2.sp deleted file mode 100644 index 5d224613b0..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pnmos_cr14_2.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:06:01 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_pmos Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Vbiasn:O Voutn:O Voutp:O -MM7 Voutp Vinn net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vinp net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM5 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR14_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net010 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 Vbiasn net010 res=rK -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_pmos -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR14_2 Biasn Biasp CR14_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pnmos_cr15_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pnmos_cr15_1.sp deleted file mode 100644 index 593f12d025..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pnmos_cr15_1.sp +++ /dev/null @@ -1,63 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:06:01 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_pmos Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Vbiasn:O Voutn:O Voutp:O -MM7 Voutp Vinn net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vinp net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM5 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR15_1 Vbiasp -*.PININFO Vbiasp:O -RR1 Vbiasp gnd! res=rK -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_pmos -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR15_1 Biasp CR15_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pnmos_cr16_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pnmos_cr16_1.sp deleted file mode 100644 index 3e6049377b..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pnmos_cr16_1.sp +++ /dev/null @@ -1,64 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:06:01 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_pmos Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Vbiasn:O Voutn:O Voutp:O -MM7 Voutp Vinn net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vinp net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM5 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR16_1 Vbiasp -*.PININFO Vbiasp:O -RR0 vdd! net6 res=rK -RR1 Vbiasp gnd! res=rK -MM2 Vbiasp Vbiasp net6 vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_pmos -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR16_1 Biasp CR16_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pnmos_cr2_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pnmos_cr2_2.sp deleted file mode 100644 index 460fff657c..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pnmos_cr2_2.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:06:01 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_pmos Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Vbiasn:O Voutn:O Voutp:O -MM7 Voutp Vinn net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vinp net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM5 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR2_2_wilson Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -RR0 Vbiasn gnd! res=rK -MM2 Vbiasp net12 Vbiasn gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_pmos -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR2_2_wilson Biasn Biasp CR2_2_wilson -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pnmos_cr3_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pnmos_cr3_2.sp deleted file mode 100644 index fce0f9b5cd..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pnmos_cr3_2.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:06:01 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_pmos Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Vbiasn:O Voutn:O Voutp:O -MM7 Voutp Vinn net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vinp net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM5 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR3_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 net15 gnd! res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_pmos -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR3_2 Biasn Biasp CR3_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pnmos_cr4_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pnmos_cr4_2.sp deleted file mode 100644 index 202456d21f..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pnmos_cr4_2.sp +++ /dev/null @@ -1,71 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:06:01 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_pmos Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Vbiasn:O Voutn:O Voutp:O -MM7 Voutp Vinn net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vinp net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM5 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR4_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM11 net023 net024 Vbiasn gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM8 net025 net010 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM9 net024 net024 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM7 net010 net010 net025 gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net025 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 net024 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net010 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_pmos -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR4_2 Biasn Biasp CR4_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pnmos_cr5_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pnmos_cr5_2.sp deleted file mode 100644 index 674bee212a..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pnmos_cr5_2.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:06:01 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_pmos Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Vbiasn:O Voutn:O Voutp:O -MM7 Voutp Vinn net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vinp net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM5 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR5_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM5 net014 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net014 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_pmos -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR5_2 Biasn Biasp CR5_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pnmos_cr6_3.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pnmos_cr6_3.sp deleted file mode 100644 index b3a8e1c95b..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/fully_differential_OTA/fully_differential_pmos_LG_pnmos_cr6_3.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:06:01 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_pmos Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Vbiasn:O Voutn:O Voutp:O -MM7 Voutp Vinn net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vinp net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM5 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR6_3 Vbiasn1 Vbiasn2 Vbiasp -*.PININFO Vbiasn1:O Vbiasn2:O Vbiasp:O -MM2 Vbiasp Vbiasn2 Vbiasn1 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn2 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 Vbiasn1 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM5 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn2 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp Vinn Vinp Voutn Voutp fully_differential_pmos -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR6_3 Biasn1 Biasn2 Biasp CR6_3 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_nmos_cr13_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_nmos_cr13_1.sp deleted file mode 100644 index b625125abb..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_nmos_cr13_1.sp +++ /dev/null @@ -1,61 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended -* View Name: schematic -* Netlisted on: Sep 11 21:06:14 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos Biasp Vbiasn -*.PININFO Biasp:I Vbiasn:O -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended -xiLG_nmos Biasp LG_Vbiasn LG_nmos -xibCR13_2 Biasn Biasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_nmos_cr13_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_nmos_cr13_2.sp deleted file mode 100644 index b625125abb..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_nmos_cr13_2.sp +++ /dev/null @@ -1,61 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended -* View Name: schematic -* Netlisted on: Sep 11 21:06:14 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos Biasp Vbiasn -*.PININFO Biasp:I Vbiasn:O -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended -xiLG_nmos Biasp LG_Vbiasn LG_nmos -xibCR13_2 Biasn Biasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_nmos_cr14_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_nmos_cr14_2.sp deleted file mode 100644 index 5b8d754be5..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_nmos_cr14_2.sp +++ /dev/null @@ -1,62 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended -* View Name: schematic -* Netlisted on: Sep 11 21:06:14 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos Biasp Vbiasn -*.PININFO Biasp:I Vbiasn:O -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR14_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net010 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 Vbiasn net010 res=rK -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended -xiLG_nmos Biasp LG_Vbiasn LG_nmos -xibCR14_2 Biasn Biasp CR14_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_nmos_cr15_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_nmos_cr15_1.sp deleted file mode 100644 index f278aec84b..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_nmos_cr15_1.sp +++ /dev/null @@ -1,59 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended -* View Name: schematic -* Netlisted on: Sep 11 21:06:14 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos Biasp Vbiasn -*.PININFO Biasp:I Vbiasn:O -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR15_1 Vbiasp -*.PININFO Vbiasp:O -RR1 Vbiasp gnd! res=rK -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended -xiLG_nmos Biasp LG_Vbiasn LG_nmos -xibCR15_1 Biasp CR15_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_nmos_cr16_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_nmos_cr16_1.sp deleted file mode 100644 index d2b5fc9dc7..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_nmos_cr16_1.sp +++ /dev/null @@ -1,60 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended -* View Name: schematic -* Netlisted on: Sep 11 21:06:14 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos Biasp Vbiasn -*.PININFO Biasp:I Vbiasn:O -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR16_1 Vbiasp -*.PININFO Vbiasp:O -RR0 vdd! net6 res=rK -RR1 Vbiasp gnd! res=rK -MM2 Vbiasp Vbiasp net6 vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended -xiLG_nmos Biasp LG_Vbiasn LG_nmos -xibCR16_1 Biasp CR16_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_nmos_cr2_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_nmos_cr2_2.sp deleted file mode 100644 index 790dbc33d3..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_nmos_cr2_2.sp +++ /dev/null @@ -1,62 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended -* View Name: schematic -* Netlisted on: Sep 11 21:06:14 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos Biasp Vbiasn -*.PININFO Biasp:I Vbiasn:O -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR2_2_wilson Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -RR0 Vbiasn gnd! res=rK -MM2 Vbiasp net12 Vbiasn gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended -xiLG_nmos Biasp LG_Vbiasn LG_nmos -xibCR2_2_wilson Biasn Biasp CR2_2_wilson -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_nmos_cr3_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_nmos_cr3_2.sp deleted file mode 100644 index d5aa06f9bf..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_nmos_cr3_2.sp +++ /dev/null @@ -1,62 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended -* View Name: schematic -* Netlisted on: Sep 11 21:06:14 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos Biasp Vbiasn -*.PININFO Biasp:I Vbiasn:O -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR3_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 net15 gnd! res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended -xiLG_nmos Biasp LG_Vbiasn LG_nmos -xibCR3_2 Biasn Biasp CR3_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_nmos_cr4_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_nmos_cr4_2.sp deleted file mode 100644 index 3062e6bf7d..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_nmos_cr4_2.sp +++ /dev/null @@ -1,67 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended -* View Name: schematic -* Netlisted on: Sep 11 21:06:14 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos Biasp Vbiasn -*.PININFO Biasp:I Vbiasn:O -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR4_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM11 net023 net024 Vbiasn gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM8 net025 net010 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM9 net024 net024 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM7 net010 net010 net025 gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net025 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 net024 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net010 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended -xiLG_nmos Biasp LG_Vbiasn LG_nmos -xibCR4_2 Biasn Biasp CR4_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_nmos_cr5_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_nmos_cr5_2.sp deleted file mode 100644 index be5584ee36..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_nmos_cr5_2.sp +++ /dev/null @@ -1,64 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended -* View Name: schematic -* Netlisted on: Sep 11 21:06:14 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos Biasp Vbiasn -*.PININFO Biasp:I Vbiasn:O -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR5_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM5 net014 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net014 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended -xiLG_nmos Biasp LG_Vbiasn LG_nmos -xibCR5_2 Biasn Biasp CR5_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_nmos_cr6_3.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_nmos_cr6_3.sp deleted file mode 100644 index 59adbf95ad..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_nmos_cr6_3.sp +++ /dev/null @@ -1,64 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended -* View Name: schematic -* Netlisted on: Sep 11 21:06:14 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos Biasp Vbiasn -*.PININFO Biasp:I Vbiasn:O -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR6_3 Vbiasn1 Vbiasn2 Vbiasp -*.PININFO Vbiasn1:O Vbiasn2:O Vbiasp:O -MM2 Vbiasp Vbiasn2 Vbiasn1 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn2 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 Vbiasn1 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM5 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn2 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended -xiLG_nmos Biasp LG_Vbiasn LG_nmos -xibCR6_3 Biasn1 Biasn2 Biasp CR6_3 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_nmos_l1_cr11_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_nmos_l1_cr11_1.sp deleted file mode 100644 index 74e025f49c..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_nmos_l1_cr11_1.sp +++ /dev/null @@ -1,64 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended -* View Name: schematic -* Netlisted on: Sep 11 21:06:14 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR11_1 Vbiasn -*.PININFO Vbiasn:O -RRF vdd! Vbiasn res=rK -MM1 net9 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net9 net9 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn net9 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR11_1 Biasn CR11_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_nmos_l1_cr12_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_nmos_l1_cr12_1.sp deleted file mode 100644 index 757f46ef4e..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_nmos_l1_cr12_1.sp +++ /dev/null @@ -1,64 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended -* View Name: schematic -* Netlisted on: Sep 11 21:06:14 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR12_1 Vbiasn -*.PININFO Vbiasn:O -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 net10 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn net10 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RRF vdd! Vbiasn res=rK -RR0 vdd! net10 res=rK -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR12_1 Biasn CR12_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_nmos_l1_cr13_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_nmos_l1_cr13_1.sp deleted file mode 100644 index 1b92f62a69..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_nmos_l1_cr13_1.sp +++ /dev/null @@ -1,63 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended -* View Name: schematic -* Netlisted on: Sep 11 21:06:14 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR13_2 Biasn Vbiasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_nmos_l1_cr13_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_nmos_l1_cr13_2.sp deleted file mode 100644 index 1b92f62a69..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_nmos_l1_cr13_2.sp +++ /dev/null @@ -1,63 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended -* View Name: schematic -* Netlisted on: Sep 11 21:06:14 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR13_2 Biasn Vbiasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_nmos_l1_cr14_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_nmos_l1_cr14_2.sp deleted file mode 100644 index 17992115a6..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_nmos_l1_cr14_2.sp +++ /dev/null @@ -1,64 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended -* View Name: schematic -* Netlisted on: Sep 11 21:06:14 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR14_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net010 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 Vbiasn net010 res=rK -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR14_2 Biasn Vbiasp CR14_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_nmos_l1_cr1_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_nmos_l1_cr1_1.sp deleted file mode 100644 index f23b56479e..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_nmos_l1_cr1_1.sp +++ /dev/null @@ -1,61 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended -* View Name: schematic -* Netlisted on: Sep 11 21:06:14 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR1_1 Vbiasn -*.PININFO Vbiasn:O -RRF vdd! Vbiasn res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR1_1 Biasn CR1_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_nmos_l1_cr2_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_nmos_l1_cr2_2.sp deleted file mode 100644 index 7dbde2523d..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_nmos_l1_cr2_2.sp +++ /dev/null @@ -1,64 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended -* View Name: schematic -* Netlisted on: Sep 11 21:06:14 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR2_2_wilson Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -RR0 Vbiasn gnd! res=rK -MM2 Vbiasp net12 Vbiasn gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR2_2_wilson Biasn Vbiasp CR2_2_wilson -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_nmos_l1_cr3_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_nmos_l1_cr3_2.sp deleted file mode 100644 index 5a64a51238..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_nmos_l1_cr3_2.sp +++ /dev/null @@ -1,64 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended -* View Name: schematic -* Netlisted on: Sep 11 21:06:14 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR3_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 net15 gnd! res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR3_2 Biasn Vbiasp CR3_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_nmos_l1_cr4_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_nmos_l1_cr4_2.sp deleted file mode 100644 index 4d4556de58..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_nmos_l1_cr4_2.sp +++ /dev/null @@ -1,69 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended -* View Name: schematic -* Netlisted on: Sep 11 21:06:14 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR4_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM11 net023 net024 Vbiasn gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM8 net025 net010 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM9 net024 net024 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM7 net010 net010 net025 gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net025 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 net024 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net010 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR4_2 Biasn Vbiasp CR4_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_nmos_l1_cr5_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_nmos_l1_cr5_2.sp deleted file mode 100644 index 619702cbc8..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_nmos_l1_cr5_2.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended -* View Name: schematic -* Netlisted on: Sep 11 21:06:14 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR5_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM5 net014 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net014 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR5_2 Biasn Vbiasp CR5_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_nmos_l1_cr7_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_nmos_l1_cr7_1.sp deleted file mode 100644 index 39c676e708..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_nmos_l1_cr7_1.sp +++ /dev/null @@ -1,64 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended -* View Name: schematic -* Netlisted on: Sep 11 21:06:14 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR7_1 Vbiasn -*.PININFO Vbiasn:O -RR1 Vbiasn net7 res=rK -RR0 vdd! net7 res=rK -RRF vdd! Vbiasn res=rK -MM1 net7 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR7_1 Biasn CR7_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_nmos_l1_cr9_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_nmos_l1_cr9_1.sp deleted file mode 100644 index a28461b58b..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_nmos_l1_cr9_1.sp +++ /dev/null @@ -1,62 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended -* View Name: schematic -* Netlisted on: Sep 11 21:06:14 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR9_1 Vbiasn -*.PININFO Vbiasn:O -RR1 net05 gnd! res=rK -RRF vdd! Vbiasn res=rK -MM0 Vbiasn Vbiasn net05 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR9_1 Biasn CR9_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_npmos_cr11_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_npmos_cr11_1.sp deleted file mode 100644 index 4c6cec57cd..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_npmos_cr11_1.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended -* View Name: schematic -* Netlisted on: Sep 11 21:06:14 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR11_1 Vbiasn -*.PININFO Vbiasn:O -RRF vdd! Vbiasn res=rK -MM1 net9 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net9 net9 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn net9 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR11_1 Biasn CR11_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_npmos_cr12_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_npmos_cr12_1.sp deleted file mode 100644 index e94f8f6b32..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_npmos_cr12_1.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended -* View Name: schematic -* Netlisted on: Sep 11 21:06:14 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR12_1 Vbiasn -*.PININFO Vbiasn:O -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 net10 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn net10 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RRF vdd! Vbiasn res=rK -RR0 vdd! net10 res=rK -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR12_1 Biasn CR12_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_npmos_cr13_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_npmos_cr13_1.sp deleted file mode 100644 index a7d2d5279a..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_npmos_cr13_1.sp +++ /dev/null @@ -1,65 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended -* View Name: schematic -* Netlisted on: Sep 11 21:06:14 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR13_2 Biasn Vbiasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_npmos_cr13_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_npmos_cr13_2.sp deleted file mode 100644 index a7d2d5279a..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_npmos_cr13_2.sp +++ /dev/null @@ -1,65 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended -* View Name: schematic -* Netlisted on: Sep 11 21:06:14 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR13_2 Biasn Vbiasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_npmos_cr14_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_npmos_cr14_2.sp deleted file mode 100644 index dfdcb48d50..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_npmos_cr14_2.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended -* View Name: schematic -* Netlisted on: Sep 11 21:06:14 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR14_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net010 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 Vbiasn net010 res=rK -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR14_2 Biasn Vbiasp CR14_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_npmos_cr1_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_npmos_cr1_1.sp deleted file mode 100644 index 447cc815a0..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_npmos_cr1_1.sp +++ /dev/null @@ -1,63 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended -* View Name: schematic -* Netlisted on: Sep 11 21:06:14 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR1_1 Vbiasn -*.PININFO Vbiasn:O -RRF vdd! Vbiasn res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR1_1 Biasn CR1_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_npmos_cr2_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_npmos_cr2_2.sp deleted file mode 100644 index 559a3b4bbb..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_npmos_cr2_2.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended -* View Name: schematic -* Netlisted on: Sep 11 21:06:14 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR2_2_wilson Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -RR0 Vbiasn gnd! res=rK -MM2 Vbiasp net12 Vbiasn gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR2_2_wilson Biasn Vbiasp CR2_2_wilson -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_npmos_cr3_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_npmos_cr3_2.sp deleted file mode 100644 index db11a17c83..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_npmos_cr3_2.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended -* View Name: schematic -* Netlisted on: Sep 11 21:06:14 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR3_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 net15 gnd! res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR3_2 Biasn Vbiasp CR3_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_npmos_cr4_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_npmos_cr4_2.sp deleted file mode 100644 index 29391b8796..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_npmos_cr4_2.sp +++ /dev/null @@ -1,71 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended -* View Name: schematic -* Netlisted on: Sep 11 21:06:14 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR4_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM11 net023 net024 Vbiasn gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM8 net025 net010 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM9 net024 net024 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM7 net010 net010 net025 gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net025 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 net024 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net010 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR4_2 Biasn Vbiasp CR4_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_npmos_cr5_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_npmos_cr5_2.sp deleted file mode 100644 index 6bed98dd1b..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_npmos_cr5_2.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended -* View Name: schematic -* Netlisted on: Sep 11 21:06:14 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR5_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM5 net014 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net014 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR5_2 Biasn Vbiasp CR5_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_npmos_cr7_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_npmos_cr7_1.sp deleted file mode 100644 index 5ec8f00076..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_npmos_cr7_1.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended -* View Name: schematic -* Netlisted on: Sep 11 21:06:14 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR7_1 Vbiasn -*.PININFO Vbiasn:O -RR1 Vbiasn net7 res=rK -RR0 vdd! net7 res=rK -RRF vdd! Vbiasn res=rK -MM1 net7 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR7_1 Biasn CR7_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_npmos_cr9_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_npmos_cr9_1.sp deleted file mode 100644 index 7a07214990..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_npmos_cr9_1.sp +++ /dev/null @@ -1,64 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended -* View Name: schematic -* Netlisted on: Sep 11 21:06:14 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR9_1 Vbiasn -*.PININFO Vbiasn:O -RR1 net05 gnd! res=rK -RRF vdd! Vbiasn res=rK -MM0 Vbiasn Vbiasn net05 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR9_1 Biasn CR9_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_pmos_l1_cr13_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_pmos_l1_cr13_1.sp deleted file mode 100644 index 5fc4897caa..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_pmos_l1_cr13_1.sp +++ /dev/null @@ -1,63 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended -* View Name: schematic -* Netlisted on: Sep 11 21:06:14 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR13_2 Biasn Biasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_pmos_l1_cr13_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_pmos_l1_cr13_2.sp deleted file mode 100644 index 5fc4897caa..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_pmos_l1_cr13_2.sp +++ /dev/null @@ -1,63 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended -* View Name: schematic -* Netlisted on: Sep 11 21:06:14 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR13_2 Biasn Biasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_pmos_l1_cr14_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_pmos_l1_cr14_2.sp deleted file mode 100644 index 72cad804de..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_pmos_l1_cr14_2.sp +++ /dev/null @@ -1,64 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended -* View Name: schematic -* Netlisted on: Sep 11 21:06:14 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR14_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net010 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 Vbiasn net010 res=rK -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR14_2 Biasn Biasp CR14_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_pmos_l1_cr15_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_pmos_l1_cr15_1.sp deleted file mode 100644 index a542edeee0..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_pmos_l1_cr15_1.sp +++ /dev/null @@ -1,61 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended -* View Name: schematic -* Netlisted on: Sep 11 21:06:14 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR15_1 Vbiasp -*.PININFO Vbiasp:O -RR1 Vbiasp gnd! res=rK -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR15_1 Biasp CR15_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_pmos_l1_cr16_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_pmos_l1_cr16_1.sp deleted file mode 100644 index 20c665d4f7..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_pmos_l1_cr16_1.sp +++ /dev/null @@ -1,62 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended -* View Name: schematic -* Netlisted on: Sep 11 21:06:14 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR16_1 Vbiasp -*.PININFO Vbiasp:O -RR0 vdd! net6 res=rK -RR1 Vbiasp gnd! res=rK -MM2 Vbiasp Vbiasp net6 vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR16_1 Biasp CR16_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_pmos_l1_cr2_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_pmos_l1_cr2_2.sp deleted file mode 100644 index df44fdd7f9..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_pmos_l1_cr2_2.sp +++ /dev/null @@ -1,64 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended -* View Name: schematic -* Netlisted on: Sep 11 21:06:14 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR2_2_wilson Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -RR0 Vbiasn gnd! res=rK -MM2 Vbiasp net12 Vbiasn gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR2_2_wilson Biasn Biasp CR2_2_wilson -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_pmos_l1_cr3_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_pmos_l1_cr3_2.sp deleted file mode 100644 index e815ea95dd..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_pmos_l1_cr3_2.sp +++ /dev/null @@ -1,64 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended -* View Name: schematic -* Netlisted on: Sep 11 21:06:14 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR3_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 net15 gnd! res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR3_2 Biasn Biasp CR3_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_pmos_l1_cr4_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_pmos_l1_cr4_2.sp deleted file mode 100644 index c4eb0ab8ff..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_pmos_l1_cr4_2.sp +++ /dev/null @@ -1,69 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended -* View Name: schematic -* Netlisted on: Sep 11 21:06:14 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR4_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM11 net023 net024 Vbiasn gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM8 net025 net010 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM9 net024 net024 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM7 net010 net010 net025 gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net025 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 net024 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net010 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR4_2 Biasn Biasp CR4_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_pmos_l1_cr5_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_pmos_l1_cr5_2.sp deleted file mode 100644 index 279a58dd03..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_pmos_l1_cr5_2.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended -* View Name: schematic -* Netlisted on: Sep 11 21:06:14 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR5_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM5 net014 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net014 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR5_2 Biasn Biasp CR5_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_pmos_l1_cr6_3.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_pmos_l1_cr6_3.sp deleted file mode 100644 index 88b2942a87..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_pmos_l1_cr6_3.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended -* View Name: schematic -* Netlisted on: Sep 11 21:06:14 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR6_3 Vbiasn1 Vbiasn2 Vbiasp -*.PININFO Vbiasn1:O Vbiasn2:O Vbiasp:O -MM2 Vbiasp Vbiasn2 Vbiasn1 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn2 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 Vbiasn1 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM5 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn2 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR6_3 Biasn1 Biasn2 Biasp CR6_3 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_pnmos_4_cr13_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_pnmos_4_cr13_1.sp deleted file mode 100644 index e9a2e3924d..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_pnmos_4_cr13_1.sp +++ /dev/null @@ -1,65 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended -* View Name: schematic -* Netlisted on: Sep 11 21:06:14 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR13_2 Biasn Biasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_pnmos_4_cr13_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_pnmos_4_cr13_2.sp deleted file mode 100644 index e9a2e3924d..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_pnmos_4_cr13_2.sp +++ /dev/null @@ -1,65 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended -* View Name: schematic -* Netlisted on: Sep 11 21:06:14 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR13_2 Biasn Biasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_pnmos_4_cr14_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_pnmos_4_cr14_2.sp deleted file mode 100644 index c6c4b89ebd..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_pnmos_4_cr14_2.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended -* View Name: schematic -* Netlisted on: Sep 11 21:06:14 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR14_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net010 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 Vbiasn net010 res=rK -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR14_2 Biasn Biasp CR14_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_pnmos_4_cr15_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_pnmos_4_cr15_1.sp deleted file mode 100644 index 437bbaa8e3..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_pnmos_4_cr15_1.sp +++ /dev/null @@ -1,63 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended -* View Name: schematic -* Netlisted on: Sep 11 21:06:14 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR15_1 Vbiasp -*.PININFO Vbiasp:O -RR1 Vbiasp gnd! res=rK -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR15_1 Biasp CR15_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_pnmos_4_cr16_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_pnmos_4_cr16_1.sp deleted file mode 100644 index f006404c2e..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_pnmos_4_cr16_1.sp +++ /dev/null @@ -1,64 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended -* View Name: schematic -* Netlisted on: Sep 11 21:06:14 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR16_1 Vbiasp -*.PININFO Vbiasp:O -RR0 vdd! net6 res=rK -RR1 Vbiasp gnd! res=rK -MM2 Vbiasp Vbiasp net6 vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR16_1 Biasp CR16_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_pnmos_4_cr2_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_pnmos_4_cr2_2.sp deleted file mode 100644 index dc5027b521..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_pnmos_4_cr2_2.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended -* View Name: schematic -* Netlisted on: Sep 11 21:06:14 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR2_2_wilson Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -RR0 Vbiasn gnd! res=rK -MM2 Vbiasp net12 Vbiasn gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR2_2_wilson Biasn Biasp CR2_2_wilson -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_pnmos_4_cr3_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_pnmos_4_cr3_2.sp deleted file mode 100644 index dc7c3d7862..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_pnmos_4_cr3_2.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended -* View Name: schematic -* Netlisted on: Sep 11 21:06:14 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR3_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 net15 gnd! res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR3_2 Biasn Biasp CR3_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_pnmos_4_cr4_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_pnmos_4_cr4_2.sp deleted file mode 100644 index 03a14506dc..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_pnmos_4_cr4_2.sp +++ /dev/null @@ -1,71 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended -* View Name: schematic -* Netlisted on: Sep 11 21:06:14 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR4_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM11 net023 net024 Vbiasn gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM8 net025 net010 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM9 net024 net024 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM7 net010 net010 net025 gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net025 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 net024 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net010 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR4_2 Biasn Biasp CR4_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_pnmos_4_cr5_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_pnmos_4_cr5_2.sp deleted file mode 100644 index 1852707e7a..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_pnmos_4_cr5_2.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended -* View Name: schematic -* Netlisted on: Sep 11 21:06:14 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR5_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM5 net014 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net014 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR5_2 Biasn Biasp CR5_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_pnmos_4_cr6_3.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_pnmos_4_cr6_3.sp deleted file mode 100644 index dd8a1d11ec..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_pnmos_4_cr6_3.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended -* View Name: schematic -* Netlisted on: Sep 11 21:06:14 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR6_3 Vbiasn1 Vbiasn2 Vbiasp -*.PININFO Vbiasn1:O Vbiasn2:O Vbiasp:O -MM2 Vbiasp Vbiasn2 Vbiasn1 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn2 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 Vbiasn1 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM5 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn2 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR6_3 Biasn1 Biasn2 Biasp CR6_3 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_pnmos_cr13_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_pnmos_cr13_1.sp deleted file mode 100644 index a7f84816d1..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_pnmos_cr13_1.sp +++ /dev/null @@ -1,65 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended -* View Name: schematic -* Netlisted on: Sep 11 21:06:14 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR13_2 Biasn Biasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_pnmos_cr13_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_pnmos_cr13_2.sp deleted file mode 100644 index a7f84816d1..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_pnmos_cr13_2.sp +++ /dev/null @@ -1,65 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended -* View Name: schematic -* Netlisted on: Sep 11 21:06:14 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR13_2 Biasn Biasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_pnmos_cr14_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_pnmos_cr14_2.sp deleted file mode 100644 index b65d634119..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_pnmos_cr14_2.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended -* View Name: schematic -* Netlisted on: Sep 11 21:06:14 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR14_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net010 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 Vbiasn net010 res=rK -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR14_2 Biasn Biasp CR14_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_pnmos_cr15_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_pnmos_cr15_1.sp deleted file mode 100644 index f7a95f2c47..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_pnmos_cr15_1.sp +++ /dev/null @@ -1,63 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended -* View Name: schematic -* Netlisted on: Sep 11 21:06:14 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR15_1 Vbiasp -*.PININFO Vbiasp:O -RR1 Vbiasp gnd! res=rK -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR15_1 Biasp CR15_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_pnmos_cr16_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_pnmos_cr16_1.sp deleted file mode 100644 index 91d27146ef..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_pnmos_cr16_1.sp +++ /dev/null @@ -1,64 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended -* View Name: schematic -* Netlisted on: Sep 11 21:06:14 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR16_1 Vbiasp -*.PININFO Vbiasp:O -RR0 vdd! net6 res=rK -RR1 Vbiasp gnd! res=rK -MM2 Vbiasp Vbiasp net6 vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR16_1 Biasp CR16_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_pnmos_cr2_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_pnmos_cr2_2.sp deleted file mode 100644 index 87eaeaf1f7..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_pnmos_cr2_2.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended -* View Name: schematic -* Netlisted on: Sep 11 21:06:14 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR2_2_wilson Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -RR0 Vbiasn gnd! res=rK -MM2 Vbiasp net12 Vbiasn gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR2_2_wilson Biasn Biasp CR2_2_wilson -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_pnmos_cr3_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_pnmos_cr3_2.sp deleted file mode 100644 index da52d153ed..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_pnmos_cr3_2.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended -* View Name: schematic -* Netlisted on: Sep 11 21:06:14 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR3_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 net15 gnd! res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR3_2 Biasn Biasp CR3_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_pnmos_cr4_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_pnmos_cr4_2.sp deleted file mode 100644 index 43f8baef00..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_pnmos_cr4_2.sp +++ /dev/null @@ -1,71 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended -* View Name: schematic -* Netlisted on: Sep 11 21:06:14 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR4_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM11 net023 net024 Vbiasn gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM8 net025 net010 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM9 net024 net024 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM7 net010 net010 net025 gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net025 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 net024 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net010 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR4_2 Biasn Biasp CR4_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_pnmos_cr5_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_pnmos_cr5_2.sp deleted file mode 100644 index ed209cdd3f..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_pnmos_cr5_2.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended -* View Name: schematic -* Netlisted on: Sep 11 21:06:14 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR5_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM5 net014 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net014 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR5_2 Biasn Biasp CR5_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_pnmos_cr6_3.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_pnmos_cr6_3.sp deleted file mode 100644 index 6d685bc3fe..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_LG_pnmos_cr6_3.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended -* View Name: schematic -* Netlisted on: Sep 11 21:06:14 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR6_3 Vbiasn1 Vbiasn2 Vbiasp -*.PININFO Vbiasn1:O Vbiasn2:O Vbiasp:O -MM2 Vbiasp Vbiasn2 Vbiasn1 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn2 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 Vbiasn1 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM5 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn2 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR6_3 Biasn1 Biasn2 Biasp CR6_3 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_LG_load_biasn_LV_cr13_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_LG_load_biasn_LV_cr13_1.sp deleted file mode 100644 index ee3ce8879f..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_LG_load_biasn_LV_cr13_1.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_cascode -* View Name: schematic -* Netlisted on: Sep 11 21:06:28 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_cascode -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_cascode Vbiasn1 Vbiasn2 Vbiasp1 Vbiasp2 Vinn Vinp Voutn -*.PININFO Vbiasn1:I Vbiasn2:I Vbiasp1:I Vbiasp2:I Vinn:I Vinp:I Voutn:O -MM10 net27 net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net21 net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net12 Vbiasn2 net27 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutn Vbiasn2 net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net32 Vinp net10 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net26 Vinn net10 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net10 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net12 Vbiasp2 net26 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn Vbiasp2 net32 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net32 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net26 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasn_LV Vbiasn2 Biasp -*.PININFO Biasp:I Vbiasn2:O -MM13 net9 Vbiasn2 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM15 Vbiasn2 Vbiasn2 net9 gnd! nmos_rvt w=WA l=LA nfin=nA -MM14 Vbiasn2 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn1 LG_Vbiasn2 LG_Vbiasp1 LG_Vbiasp2 Vinn Vinp Voutn single_ended_cascode -xiLG_load_biasn_LV Biasp LG_Vbiasn2 LG_load_biasn_LV -xibCR13_2 Biasn Biasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_LG_load_biasn_LV_cr13_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_LG_load_biasn_LV_cr13_2.sp deleted file mode 100644 index ee3ce8879f..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_LG_load_biasn_LV_cr13_2.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_cascode -* View Name: schematic -* Netlisted on: Sep 11 21:06:28 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_cascode -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_cascode Vbiasn1 Vbiasn2 Vbiasp1 Vbiasp2 Vinn Vinp Voutn -*.PININFO Vbiasn1:I Vbiasn2:I Vbiasp1:I Vbiasp2:I Vinn:I Vinp:I Voutn:O -MM10 net27 net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net21 net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net12 Vbiasn2 net27 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutn Vbiasn2 net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net32 Vinp net10 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net26 Vinn net10 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net10 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net12 Vbiasp2 net26 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn Vbiasp2 net32 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net32 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net26 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasn_LV Vbiasn2 Biasp -*.PININFO Biasp:I Vbiasn2:O -MM13 net9 Vbiasn2 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM15 Vbiasn2 Vbiasn2 net9 gnd! nmos_rvt w=WA l=LA nfin=nA -MM14 Vbiasn2 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn1 LG_Vbiasn2 LG_Vbiasp1 LG_Vbiasp2 Vinn Vinp Voutn single_ended_cascode -xiLG_load_biasn_LV Biasp LG_Vbiasn2 LG_load_biasn_LV -xibCR13_2 Biasn Biasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_LG_load_biasn_LV_cr14_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_LG_load_biasn_LV_cr14_2.sp deleted file mode 100644 index 8e36df8213..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_LG_load_biasn_LV_cr14_2.sp +++ /dev/null @@ -1,69 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_cascode -* View Name: schematic -* Netlisted on: Sep 11 21:06:28 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_cascode -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_cascode Vbiasn1 Vbiasn2 Vbiasp1 Vbiasp2 Vinn Vinp Voutn -*.PININFO Vbiasn1:I Vbiasn2:I Vbiasp1:I Vbiasp2:I Vinn:I Vinp:I Voutn:O -MM10 net27 net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net21 net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net12 Vbiasn2 net27 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutn Vbiasn2 net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net32 Vinp net10 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net26 Vinn net10 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net10 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net12 Vbiasp2 net26 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn Vbiasp2 net32 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net32 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net26 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasn_LV Vbiasn2 Biasp -*.PININFO Biasp:I Vbiasn2:O -MM13 net9 Vbiasn2 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM15 Vbiasn2 Vbiasn2 net9 gnd! nmos_rvt w=WA l=LA nfin=nA -MM14 Vbiasn2 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR14_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net010 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 Vbiasn net010 res=rK -.ENDS - - -xiota LG_Vbiasn1 LG_Vbiasn2 LG_Vbiasp1 LG_Vbiasp2 Vinn Vinp Voutn single_ended_cascode -xiLG_load_biasn_LV Biasp LG_Vbiasn2 LG_load_biasn_LV -xibCR14_2 Biasn Biasp CR14_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_LG_load_biasn_LV_cr15_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_LG_load_biasn_LV_cr15_1.sp deleted file mode 100644 index 7dd0be3cff..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_LG_load_biasn_LV_cr15_1.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_cascode -* View Name: schematic -* Netlisted on: Sep 11 21:06:28 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_cascode -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_cascode Vbiasn1 Vbiasn2 Vbiasp1 Vbiasp2 Vinn Vinp Voutn -*.PININFO Vbiasn1:I Vbiasn2:I Vbiasp1:I Vbiasp2:I Vinn:I Vinp:I Voutn:O -MM10 net27 net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net21 net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net12 Vbiasn2 net27 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutn Vbiasn2 net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net32 Vinp net10 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net26 Vinn net10 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net10 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net12 Vbiasp2 net26 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn Vbiasp2 net32 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net32 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net26 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasn_LV Vbiasn2 Biasp -*.PININFO Biasp:I Vbiasn2:O -MM13 net9 Vbiasn2 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM15 Vbiasn2 Vbiasn2 net9 gnd! nmos_rvt w=WA l=LA nfin=nA -MM14 Vbiasn2 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR15_1 Vbiasp -*.PININFO Vbiasp:O -RR1 Vbiasp gnd! res=rK -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn1 LG_Vbiasn2 LG_Vbiasp1 LG_Vbiasp2 Vinn Vinp Voutn single_ended_cascode -xiLG_load_biasn_LV Biasp LG_Vbiasn2 LG_load_biasn_LV -xibCR15_1 Biasp CR15_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_LG_load_biasn_LV_cr16_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_LG_load_biasn_LV_cr16_1.sp deleted file mode 100644 index 794aabb376..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_LG_load_biasn_LV_cr16_1.sp +++ /dev/null @@ -1,67 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_cascode -* View Name: schematic -* Netlisted on: Sep 11 21:06:28 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_cascode -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_cascode Vbiasn1 Vbiasn2 Vbiasp1 Vbiasp2 Vinn Vinp Voutn -*.PININFO Vbiasn1:I Vbiasn2:I Vbiasp1:I Vbiasp2:I Vinn:I Vinp:I Voutn:O -MM10 net27 net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net21 net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net12 Vbiasn2 net27 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutn Vbiasn2 net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net32 Vinp net10 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net26 Vinn net10 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net10 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net12 Vbiasp2 net26 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn Vbiasp2 net32 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net32 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net26 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasn_LV Vbiasn2 Biasp -*.PININFO Biasp:I Vbiasn2:O -MM13 net9 Vbiasn2 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM15 Vbiasn2 Vbiasn2 net9 gnd! nmos_rvt w=WA l=LA nfin=nA -MM14 Vbiasn2 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR16_1 Vbiasp -*.PININFO Vbiasp:O -RR0 vdd! net6 res=rK -RR1 Vbiasp gnd! res=rK -MM2 Vbiasp Vbiasp net6 vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn1 LG_Vbiasn2 LG_Vbiasp1 LG_Vbiasp2 Vinn Vinp Voutn single_ended_cascode -xiLG_load_biasn_LV Biasp LG_Vbiasn2 LG_load_biasn_LV -xibCR16_1 Biasp CR16_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_LG_load_biasn_LV_cr2_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_LG_load_biasn_LV_cr2_2.sp deleted file mode 100644 index 6df0b825e3..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_LG_load_biasn_LV_cr2_2.sp +++ /dev/null @@ -1,69 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_cascode -* View Name: schematic -* Netlisted on: Sep 11 21:06:28 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_cascode -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_cascode Vbiasn1 Vbiasn2 Vbiasp1 Vbiasp2 Vinn Vinp Voutn -*.PININFO Vbiasn1:I Vbiasn2:I Vbiasp1:I Vbiasp2:I Vinn:I Vinp:I Voutn:O -MM10 net27 net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net21 net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net12 Vbiasn2 net27 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutn Vbiasn2 net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net32 Vinp net10 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net26 Vinn net10 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net10 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net12 Vbiasp2 net26 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn Vbiasp2 net32 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net32 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net26 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasn_LV Vbiasn2 Biasp -*.PININFO Biasp:I Vbiasn2:O -MM13 net9 Vbiasn2 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM15 Vbiasn2 Vbiasn2 net9 gnd! nmos_rvt w=WA l=LA nfin=nA -MM14 Vbiasn2 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR2_2_wilson Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -RR0 Vbiasn gnd! res=rK -MM2 Vbiasp net12 Vbiasn gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn1 LG_Vbiasn2 LG_Vbiasp1 LG_Vbiasp2 Vinn Vinp Voutn single_ended_cascode -xiLG_load_biasn_LV Biasp LG_Vbiasn2 LG_load_biasn_LV -xibCR2_2_wilson Biasn Biasp CR2_2_wilson -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_LG_load_biasn_LV_cr3_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_LG_load_biasn_LV_cr3_2.sp deleted file mode 100644 index 5b8454df0a..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_LG_load_biasn_LV_cr3_2.sp +++ /dev/null @@ -1,69 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_cascode -* View Name: schematic -* Netlisted on: Sep 11 21:06:28 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_cascode -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_cascode Vbiasn1 Vbiasn2 Vbiasp1 Vbiasp2 Vinn Vinp Voutn -*.PININFO Vbiasn1:I Vbiasn2:I Vbiasp1:I Vbiasp2:I Vinn:I Vinp:I Voutn:O -MM10 net27 net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net21 net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net12 Vbiasn2 net27 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutn Vbiasn2 net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net32 Vinp net10 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net26 Vinn net10 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net10 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net12 Vbiasp2 net26 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn Vbiasp2 net32 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net32 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net26 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasn_LV Vbiasn2 Biasp -*.PININFO Biasp:I Vbiasn2:O -MM13 net9 Vbiasn2 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM15 Vbiasn2 Vbiasn2 net9 gnd! nmos_rvt w=WA l=LA nfin=nA -MM14 Vbiasn2 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR3_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 net15 gnd! res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn1 LG_Vbiasn2 LG_Vbiasp1 LG_Vbiasp2 Vinn Vinp Voutn single_ended_cascode -xiLG_load_biasn_LV Biasp LG_Vbiasn2 LG_load_biasn_LV -xibCR3_2 Biasn Biasp CR3_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_LG_load_biasn_LV_cr4_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_LG_load_biasn_LV_cr4_2.sp deleted file mode 100644 index c82d7d31e9..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_LG_load_biasn_LV_cr4_2.sp +++ /dev/null @@ -1,74 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_cascode -* View Name: schematic -* Netlisted on: Sep 11 21:06:28 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_cascode -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_cascode Vbiasn1 Vbiasn2 Vbiasp1 Vbiasp2 Vinn Vinp Voutn -*.PININFO Vbiasn1:I Vbiasn2:I Vbiasp1:I Vbiasp2:I Vinn:I Vinp:I Voutn:O -MM10 net27 net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net21 net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net12 Vbiasn2 net27 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutn Vbiasn2 net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net32 Vinp net10 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net26 Vinn net10 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net10 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net12 Vbiasp2 net26 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn Vbiasp2 net32 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net32 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net26 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasn_LV Vbiasn2 Biasp -*.PININFO Biasp:I Vbiasn2:O -MM13 net9 Vbiasn2 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM15 Vbiasn2 Vbiasn2 net9 gnd! nmos_rvt w=WA l=LA nfin=nA -MM14 Vbiasn2 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR4_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM11 net023 net024 Vbiasn gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM8 net025 net010 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM9 net024 net024 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM7 net010 net010 net025 gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net025 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 net024 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net010 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn1 LG_Vbiasn2 LG_Vbiasp1 LG_Vbiasp2 Vinn Vinp Voutn single_ended_cascode -xiLG_load_biasn_LV Biasp LG_Vbiasn2 LG_load_biasn_LV -xibCR4_2 Biasn Biasp CR4_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_LG_load_biasn_LV_cr5_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_LG_load_biasn_LV_cr5_2.sp deleted file mode 100644 index 3a295720bd..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_LG_load_biasn_LV_cr5_2.sp +++ /dev/null @@ -1,71 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_cascode -* View Name: schematic -* Netlisted on: Sep 11 21:06:28 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_cascode -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_cascode Vbiasn1 Vbiasn2 Vbiasp1 Vbiasp2 Vinn Vinp Voutn -*.PININFO Vbiasn1:I Vbiasn2:I Vbiasp1:I Vbiasp2:I Vinn:I Vinp:I Voutn:O -MM10 net27 net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net21 net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net12 Vbiasn2 net27 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutn Vbiasn2 net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net32 Vinp net10 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net26 Vinn net10 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net10 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net12 Vbiasp2 net26 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn Vbiasp2 net32 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net32 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net26 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasn_LV Vbiasn2 Biasp -*.PININFO Biasp:I Vbiasn2:O -MM13 net9 Vbiasn2 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM15 Vbiasn2 Vbiasn2 net9 gnd! nmos_rvt w=WA l=LA nfin=nA -MM14 Vbiasn2 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR5_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM5 net014 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net014 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn1 LG_Vbiasn2 LG_Vbiasp1 LG_Vbiasp2 Vinn Vinp Voutn single_ended_cascode -xiLG_load_biasn_LV Biasp LG_Vbiasn2 LG_load_biasn_LV -xibCR5_2 Biasn Biasp CR5_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_LG_load_biasn_LV_cr6_3.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_LG_load_biasn_LV_cr6_3.sp deleted file mode 100644 index 088a59a703..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_LG_load_biasn_LV_cr6_3.sp +++ /dev/null @@ -1,71 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_cascode -* View Name: schematic -* Netlisted on: Sep 11 21:06:28 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_cascode -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_cascode Vbiasn1 Vbiasn2 Vbiasp1 Vbiasp2 Vinn Vinp Voutn -*.PININFO Vbiasn1:I Vbiasn2:I Vbiasp1:I Vbiasp2:I Vinn:I Vinp:I Voutn:O -MM10 net27 net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net21 net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net12 Vbiasn2 net27 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutn Vbiasn2 net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net32 Vinp net10 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net26 Vinn net10 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net10 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net12 Vbiasp2 net26 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn Vbiasp2 net32 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net32 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net26 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasn_LV Vbiasn2 Biasp -*.PININFO Biasp:I Vbiasn2:O -MM13 net9 Vbiasn2 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM15 Vbiasn2 Vbiasn2 net9 gnd! nmos_rvt w=WA l=LA nfin=nA -MM14 Vbiasn2 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR6_3 Vbiasn1 Vbiasn2 Vbiasp -*.PININFO Vbiasn1:O Vbiasn2:O Vbiasp:O -MM2 Vbiasp Vbiasn2 Vbiasn1 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn2 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 Vbiasn1 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM5 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn2 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn1 LG_Vbiasn2 LG_Vbiasp1 LG_Vbiasp2 Vinn Vinp Voutn single_ended_cascode -xiLG_load_biasn_LV Biasp LG_Vbiasn2 LG_load_biasn_LV -xibCR6_3 Biasn1 Biasn2 Biasp CR6_3 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_LG_load_biasn_cr13_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_LG_load_biasn_cr13_1.sp deleted file mode 100644 index cf527658fc..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_LG_load_biasn_cr13_1.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_cascode -* View Name: schematic -* Netlisted on: Sep 11 21:06:28 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_cascode -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_cascode Vbiasn1 Vbiasn2 Vbiasp1 Vbiasp2 Vinn Vinp Voutn -*.PININFO Vbiasn1:I Vbiasn2:I Vbiasp1:I Vbiasp2:I Vinn:I Vinp:I Voutn:O -MM10 net27 net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net21 net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net12 Vbiasn2 net27 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutn Vbiasn2 net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net32 Vinp net10 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net26 Vinn net10 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net10 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net12 Vbiasp2 net26 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn Vbiasp2 net32 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net32 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net26 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasn Vbiasn1 Vbiasn2 Biasp -*.PININFO Biasp:I Vbiasn1:O Vbiasn2:O -MM15 Vbiasn2 Vbiasn2 Vbiasn1 gnd! nmos_rvt w=WA l=LA nfin=nA -MM13 Vbiasn1 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM14 Vbiasn2 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn1 LG_Vbiasn2 LG_Vbiasp1 LG_Vbiasp2 Vinn Vinp Voutn single_ended_cascode -xiLG_load_biasn Biasp LG_Vbiasn1 LG_Vbiasn2 LG_load_biasn -xibCR13_2 Biasn Biasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_LG_load_biasn_cr13_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_LG_load_biasn_cr13_2.sp deleted file mode 100644 index cf527658fc..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_LG_load_biasn_cr13_2.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_cascode -* View Name: schematic -* Netlisted on: Sep 11 21:06:28 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_cascode -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_cascode Vbiasn1 Vbiasn2 Vbiasp1 Vbiasp2 Vinn Vinp Voutn -*.PININFO Vbiasn1:I Vbiasn2:I Vbiasp1:I Vbiasp2:I Vinn:I Vinp:I Voutn:O -MM10 net27 net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net21 net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net12 Vbiasn2 net27 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutn Vbiasn2 net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net32 Vinp net10 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net26 Vinn net10 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net10 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net12 Vbiasp2 net26 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn Vbiasp2 net32 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net32 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net26 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasn Vbiasn1 Vbiasn2 Biasp -*.PININFO Biasp:I Vbiasn1:O Vbiasn2:O -MM15 Vbiasn2 Vbiasn2 Vbiasn1 gnd! nmos_rvt w=WA l=LA nfin=nA -MM13 Vbiasn1 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM14 Vbiasn2 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn1 LG_Vbiasn2 LG_Vbiasp1 LG_Vbiasp2 Vinn Vinp Voutn single_ended_cascode -xiLG_load_biasn Biasp LG_Vbiasn1 LG_Vbiasn2 LG_load_biasn -xibCR13_2 Biasn Biasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_LG_load_biasn_cr14_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_LG_load_biasn_cr14_2.sp deleted file mode 100644 index 9479bb3184..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_LG_load_biasn_cr14_2.sp +++ /dev/null @@ -1,69 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_cascode -* View Name: schematic -* Netlisted on: Sep 11 21:06:28 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_cascode -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_cascode Vbiasn1 Vbiasn2 Vbiasp1 Vbiasp2 Vinn Vinp Voutn -*.PININFO Vbiasn1:I Vbiasn2:I Vbiasp1:I Vbiasp2:I Vinn:I Vinp:I Voutn:O -MM10 net27 net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net21 net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net12 Vbiasn2 net27 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutn Vbiasn2 net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net32 Vinp net10 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net26 Vinn net10 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net10 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net12 Vbiasp2 net26 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn Vbiasp2 net32 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net32 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net26 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasn Vbiasn1 Vbiasn2 Biasp -*.PININFO Biasp:I Vbiasn1:O Vbiasn2:O -MM15 Vbiasn2 Vbiasn2 Vbiasn1 gnd! nmos_rvt w=WA l=LA nfin=nA -MM13 Vbiasn1 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM14 Vbiasn2 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR14_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net010 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 Vbiasn net010 res=rK -.ENDS - - -xiota LG_Vbiasn1 LG_Vbiasn2 LG_Vbiasp1 LG_Vbiasp2 Vinn Vinp Voutn single_ended_cascode -xiLG_load_biasn Biasp LG_Vbiasn1 LG_Vbiasn2 LG_load_biasn -xibCR14_2 Biasn Biasp CR14_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_LG_load_biasn_cr15_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_LG_load_biasn_cr15_1.sp deleted file mode 100644 index 840c003200..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_LG_load_biasn_cr15_1.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_cascode -* View Name: schematic -* Netlisted on: Sep 11 21:06:28 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_cascode -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_cascode Vbiasn1 Vbiasn2 Vbiasp1 Vbiasp2 Vinn Vinp Voutn -*.PININFO Vbiasn1:I Vbiasn2:I Vbiasp1:I Vbiasp2:I Vinn:I Vinp:I Voutn:O -MM10 net27 net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net21 net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net12 Vbiasn2 net27 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutn Vbiasn2 net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net32 Vinp net10 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net26 Vinn net10 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net10 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net12 Vbiasp2 net26 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn Vbiasp2 net32 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net32 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net26 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasn Vbiasn1 Vbiasn2 Biasp -*.PININFO Biasp:I Vbiasn1:O Vbiasn2:O -MM15 Vbiasn2 Vbiasn2 Vbiasn1 gnd! nmos_rvt w=WA l=LA nfin=nA -MM13 Vbiasn1 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM14 Vbiasn2 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR15_1 Vbiasp -*.PININFO Vbiasp:O -RR1 Vbiasp gnd! res=rK -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn1 LG_Vbiasn2 LG_Vbiasp1 LG_Vbiasp2 Vinn Vinp Voutn single_ended_cascode -xiLG_load_biasn Biasp LG_Vbiasn1 LG_Vbiasn2 LG_load_biasn -xibCR15_1 Biasp CR15_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_LG_load_biasn_cr16_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_LG_load_biasn_cr16_1.sp deleted file mode 100644 index ed07471bd9..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_LG_load_biasn_cr16_1.sp +++ /dev/null @@ -1,67 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_cascode -* View Name: schematic -* Netlisted on: Sep 11 21:06:28 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_cascode -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_cascode Vbiasn1 Vbiasn2 Vbiasp1 Vbiasp2 Vinn Vinp Voutn -*.PININFO Vbiasn1:I Vbiasn2:I Vbiasp1:I Vbiasp2:I Vinn:I Vinp:I Voutn:O -MM10 net27 net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net21 net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net12 Vbiasn2 net27 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutn Vbiasn2 net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net32 Vinp net10 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net26 Vinn net10 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net10 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net12 Vbiasp2 net26 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn Vbiasp2 net32 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net32 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net26 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasn Vbiasn1 Vbiasn2 Biasp -*.PININFO Biasp:I Vbiasn1:O Vbiasn2:O -MM15 Vbiasn2 Vbiasn2 Vbiasn1 gnd! nmos_rvt w=WA l=LA nfin=nA -MM13 Vbiasn1 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM14 Vbiasn2 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR16_1 Vbiasp -*.PININFO Vbiasp:O -RR0 vdd! net6 res=rK -RR1 Vbiasp gnd! res=rK -MM2 Vbiasp Vbiasp net6 vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn1 LG_Vbiasn2 LG_Vbiasp1 LG_Vbiasp2 Vinn Vinp Voutn single_ended_cascode -xiLG_load_biasn Biasp LG_Vbiasn1 LG_Vbiasn2 LG_load_biasn -xibCR16_1 Biasp CR16_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_LG_load_biasn_cr2_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_LG_load_biasn_cr2_2.sp deleted file mode 100644 index 2ac7ad7c66..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_LG_load_biasn_cr2_2.sp +++ /dev/null @@ -1,69 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_cascode -* View Name: schematic -* Netlisted on: Sep 11 21:06:28 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_cascode -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_cascode Vbiasn1 Vbiasn2 Vbiasp1 Vbiasp2 Vinn Vinp Voutn -*.PININFO Vbiasn1:I Vbiasn2:I Vbiasp1:I Vbiasp2:I Vinn:I Vinp:I Voutn:O -MM10 net27 net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net21 net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net12 Vbiasn2 net27 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutn Vbiasn2 net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net32 Vinp net10 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net26 Vinn net10 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net10 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net12 Vbiasp2 net26 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn Vbiasp2 net32 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net32 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net26 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasn Vbiasn1 Vbiasn2 Biasp -*.PININFO Biasp:I Vbiasn1:O Vbiasn2:O -MM15 Vbiasn2 Vbiasn2 Vbiasn1 gnd! nmos_rvt w=WA l=LA nfin=nA -MM13 Vbiasn1 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM14 Vbiasn2 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR2_2_wilson Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -RR0 Vbiasn gnd! res=rK -MM2 Vbiasp net12 Vbiasn gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn1 LG_Vbiasn2 LG_Vbiasp1 LG_Vbiasp2 Vinn Vinp Voutn single_ended_cascode -xiLG_load_biasn Biasp LG_Vbiasn1 LG_Vbiasn2 LG_load_biasn -xibCR2_2_wilson Biasn Biasp CR2_2_wilson -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_LG_load_biasn_cr3_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_LG_load_biasn_cr3_2.sp deleted file mode 100644 index 1468654c93..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_LG_load_biasn_cr3_2.sp +++ /dev/null @@ -1,69 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_cascode -* View Name: schematic -* Netlisted on: Sep 11 21:06:28 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_cascode -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_cascode Vbiasn1 Vbiasn2 Vbiasp1 Vbiasp2 Vinn Vinp Voutn -*.PININFO Vbiasn1:I Vbiasn2:I Vbiasp1:I Vbiasp2:I Vinn:I Vinp:I Voutn:O -MM10 net27 net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net21 net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net12 Vbiasn2 net27 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutn Vbiasn2 net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net32 Vinp net10 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net26 Vinn net10 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net10 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net12 Vbiasp2 net26 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn Vbiasp2 net32 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net32 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net26 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasn Vbiasn1 Vbiasn2 Biasp -*.PININFO Biasp:I Vbiasn1:O Vbiasn2:O -MM15 Vbiasn2 Vbiasn2 Vbiasn1 gnd! nmos_rvt w=WA l=LA nfin=nA -MM13 Vbiasn1 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM14 Vbiasn2 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR3_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 net15 gnd! res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn1 LG_Vbiasn2 LG_Vbiasp1 LG_Vbiasp2 Vinn Vinp Voutn single_ended_cascode -xiLG_load_biasn Biasp LG_Vbiasn1 LG_Vbiasn2 LG_load_biasn -xibCR3_2 Biasn Biasp CR3_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_LG_load_biasn_cr4_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_LG_load_biasn_cr4_2.sp deleted file mode 100644 index b96f83ecf6..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_LG_load_biasn_cr4_2.sp +++ /dev/null @@ -1,74 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_cascode -* View Name: schematic -* Netlisted on: Sep 11 21:06:28 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_cascode -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_cascode Vbiasn1 Vbiasn2 Vbiasp1 Vbiasp2 Vinn Vinp Voutn -*.PININFO Vbiasn1:I Vbiasn2:I Vbiasp1:I Vbiasp2:I Vinn:I Vinp:I Voutn:O -MM10 net27 net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net21 net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net12 Vbiasn2 net27 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutn Vbiasn2 net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net32 Vinp net10 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net26 Vinn net10 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net10 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net12 Vbiasp2 net26 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn Vbiasp2 net32 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net32 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net26 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasn Vbiasn1 Vbiasn2 Biasp -*.PININFO Biasp:I Vbiasn1:O Vbiasn2:O -MM15 Vbiasn2 Vbiasn2 Vbiasn1 gnd! nmos_rvt w=WA l=LA nfin=nA -MM13 Vbiasn1 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM14 Vbiasn2 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR4_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM11 net023 net024 Vbiasn gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM8 net025 net010 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM9 net024 net024 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM7 net010 net010 net025 gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net025 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 net024 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net010 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn1 LG_Vbiasn2 LG_Vbiasp1 LG_Vbiasp2 Vinn Vinp Voutn single_ended_cascode -xiLG_load_biasn Biasp LG_Vbiasn1 LG_Vbiasn2 LG_load_biasn -xibCR4_2 Biasn Biasp CR4_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_LG_load_biasn_cr5_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_LG_load_biasn_cr5_2.sp deleted file mode 100644 index b73076df0d..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_LG_load_biasn_cr5_2.sp +++ /dev/null @@ -1,71 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_cascode -* View Name: schematic -* Netlisted on: Sep 11 21:06:28 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_cascode -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_cascode Vbiasn1 Vbiasn2 Vbiasp1 Vbiasp2 Vinn Vinp Voutn -*.PININFO Vbiasn1:I Vbiasn2:I Vbiasp1:I Vbiasp2:I Vinn:I Vinp:I Voutn:O -MM10 net27 net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net21 net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net12 Vbiasn2 net27 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutn Vbiasn2 net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net32 Vinp net10 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net26 Vinn net10 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net10 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net12 Vbiasp2 net26 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn Vbiasp2 net32 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net32 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net26 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasn Vbiasn1 Vbiasn2 Biasp -*.PININFO Biasp:I Vbiasn1:O Vbiasn2:O -MM15 Vbiasn2 Vbiasn2 Vbiasn1 gnd! nmos_rvt w=WA l=LA nfin=nA -MM13 Vbiasn1 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM14 Vbiasn2 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR5_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM5 net014 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net014 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn1 LG_Vbiasn2 LG_Vbiasp1 LG_Vbiasp2 Vinn Vinp Voutn single_ended_cascode -xiLG_load_biasn Biasp LG_Vbiasn1 LG_Vbiasn2 LG_load_biasn -xibCR5_2 Biasn Biasp CR5_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_LG_load_biasn_cr6_3.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_LG_load_biasn_cr6_3.sp deleted file mode 100644 index 80c24d84be..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_LG_load_biasn_cr6_3.sp +++ /dev/null @@ -1,71 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_cascode -* View Name: schematic -* Netlisted on: Sep 11 21:06:28 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_cascode -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_cascode Vbiasn1 Vbiasn2 Vbiasp1 Vbiasp2 Vinn Vinp Voutn -*.PININFO Vbiasn1:I Vbiasn2:I Vbiasp1:I Vbiasp2:I Vinn:I Vinp:I Voutn:O -MM10 net27 net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net21 net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net12 Vbiasn2 net27 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutn Vbiasn2 net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net32 Vinp net10 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net26 Vinn net10 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net10 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net12 Vbiasp2 net26 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn Vbiasp2 net32 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net32 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net26 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasn Vbiasn1 Vbiasn2 Biasp -*.PININFO Biasp:I Vbiasn1:O Vbiasn2:O -MM15 Vbiasn2 Vbiasn2 Vbiasn1 gnd! nmos_rvt w=WA l=LA nfin=nA -MM13 Vbiasn1 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM14 Vbiasn2 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR6_3 Vbiasn1 Vbiasn2 Vbiasp -*.PININFO Vbiasn1:O Vbiasn2:O Vbiasp:O -MM2 Vbiasp Vbiasn2 Vbiasn1 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn2 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 Vbiasn1 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM5 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn2 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn1 LG_Vbiasn2 LG_Vbiasp1 LG_Vbiasp2 Vinn Vinp Voutn single_ended_cascode -xiLG_load_biasn Biasp LG_Vbiasn1 LG_Vbiasn2 LG_load_biasn -xibCR6_3 Biasn1 Biasn2 Biasp CR6_3 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_current_mirror_LG_load_biasn_LV_cr13_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_current_mirror_LG_load_biasn_LV_cr13_1.sp deleted file mode 100644 index 5e02c237b2..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_current_mirror_LG_load_biasn_LV_cr13_1.sp +++ /dev/null @@ -1,73 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_cascode_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:41:11 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_cascode_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_cascode_current_mirror Vbiasn Vbiasn2 Vbiasp2 Vinn Vinp -+ Voutn -*.PININFO Vbiasn:I Vbiasn2:I Vbiasp2:I Vinn:I Vinp:I Voutn:O -MM12 net12 Vbiasp2 net37 vdd! pmos_rvt w=WA l=LA nfin=nA -MM11 net23 Vbiasp2 net36 vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net10 Vbiasp2 net35 vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 Voutn Vbiasp2 net34 vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net37 net12 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net36 net23 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM6 net35 net12 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 net34 net23 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM14 net10 Vbiasn2 net33 gnd! nmos_rvt w=WA l=LA nfin=nA -MM13 Voutn Vbiasn2 net31 gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net23 Vinp net17 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vinn net17 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net17 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net33 net10 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 net31 net10 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasn_LV Vbiasn2 Biasp -*.PININFO Biasp:I Vbiasn2:O -MM13 net9 Vbiasn2 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM15 Vbiasn2 Vbiasn2 net9 gnd! nmos_rvt w=WA l=LA nfin=nA -MM14 Vbiasn2 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasn2 LG_Vbiasp2 Vinn Vinp single_ended_cascode_current_mirror -xiLG_load_biasn_LV Biasp LG_Vbiasn2 LG_load_biasn_LV -xibCR13_2 Biasn Biasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_current_mirror_LG_load_biasn_LV_cr13_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_current_mirror_LG_load_biasn_LV_cr13_2.sp deleted file mode 100644 index 5e02c237b2..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_current_mirror_LG_load_biasn_LV_cr13_2.sp +++ /dev/null @@ -1,73 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_cascode_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:41:11 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_cascode_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_cascode_current_mirror Vbiasn Vbiasn2 Vbiasp2 Vinn Vinp -+ Voutn -*.PININFO Vbiasn:I Vbiasn2:I Vbiasp2:I Vinn:I Vinp:I Voutn:O -MM12 net12 Vbiasp2 net37 vdd! pmos_rvt w=WA l=LA nfin=nA -MM11 net23 Vbiasp2 net36 vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net10 Vbiasp2 net35 vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 Voutn Vbiasp2 net34 vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net37 net12 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net36 net23 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM6 net35 net12 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 net34 net23 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM14 net10 Vbiasn2 net33 gnd! nmos_rvt w=WA l=LA nfin=nA -MM13 Voutn Vbiasn2 net31 gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net23 Vinp net17 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vinn net17 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net17 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net33 net10 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 net31 net10 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasn_LV Vbiasn2 Biasp -*.PININFO Biasp:I Vbiasn2:O -MM13 net9 Vbiasn2 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM15 Vbiasn2 Vbiasn2 net9 gnd! nmos_rvt w=WA l=LA nfin=nA -MM14 Vbiasn2 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasn2 LG_Vbiasp2 Vinn Vinp single_ended_cascode_current_mirror -xiLG_load_biasn_LV Biasp LG_Vbiasn2 LG_load_biasn_LV -xibCR13_2 Biasn Biasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_current_mirror_LG_load_biasn_LV_cr14_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_current_mirror_LG_load_biasn_LV_cr14_2.sp deleted file mode 100644 index c07d8e2d7d..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_current_mirror_LG_load_biasn_LV_cr14_2.sp +++ /dev/null @@ -1,74 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_cascode_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:41:11 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_cascode_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_cascode_current_mirror Vbiasn Vbiasn2 Vbiasp2 Vinn Vinp -+ Voutn -*.PININFO Vbiasn:I Vbiasn2:I Vbiasp2:I Vinn:I Vinp:I Voutn:O -MM12 net12 Vbiasp2 net37 vdd! pmos_rvt w=WA l=LA nfin=nA -MM11 net23 Vbiasp2 net36 vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net10 Vbiasp2 net35 vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 Voutn Vbiasp2 net34 vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net37 net12 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net36 net23 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM6 net35 net12 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 net34 net23 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM14 net10 Vbiasn2 net33 gnd! nmos_rvt w=WA l=LA nfin=nA -MM13 Voutn Vbiasn2 net31 gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net23 Vinp net17 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vinn net17 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net17 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net33 net10 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 net31 net10 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasn_LV Vbiasn2 Biasp -*.PININFO Biasp:I Vbiasn2:O -MM13 net9 Vbiasn2 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM15 Vbiasn2 Vbiasn2 net9 gnd! nmos_rvt w=WA l=LA nfin=nA -MM14 Vbiasn2 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR14_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net010 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 Vbiasn net010 res=rK -.ENDS - - -xiota LG_Vbiasn LG_Vbiasn2 LG_Vbiasp2 Vinn Vinp single_ended_cascode_current_mirror -xiLG_load_biasn_LV Biasp LG_Vbiasn2 LG_load_biasn_LV -xibCR14_2 Biasn Biasp CR14_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_current_mirror_LG_load_biasn_LV_cr15_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_current_mirror_LG_load_biasn_LV_cr15_1.sp deleted file mode 100644 index 2bb4ec4d43..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_current_mirror_LG_load_biasn_LV_cr15_1.sp +++ /dev/null @@ -1,71 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_cascode_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:41:11 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_cascode_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_cascode_current_mirror Vbiasn Vbiasn2 Vbiasp2 Vinn Vinp -+ Voutn -*.PININFO Vbiasn:I Vbiasn2:I Vbiasp2:I Vinn:I Vinp:I Voutn:O -MM12 net12 Vbiasp2 net37 vdd! pmos_rvt w=WA l=LA nfin=nA -MM11 net23 Vbiasp2 net36 vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net10 Vbiasp2 net35 vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 Voutn Vbiasp2 net34 vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net37 net12 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net36 net23 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM6 net35 net12 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 net34 net23 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM14 net10 Vbiasn2 net33 gnd! nmos_rvt w=WA l=LA nfin=nA -MM13 Voutn Vbiasn2 net31 gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net23 Vinp net17 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vinn net17 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net17 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net33 net10 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 net31 net10 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasn_LV Vbiasn2 Biasp -*.PININFO Biasp:I Vbiasn2:O -MM13 net9 Vbiasn2 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM15 Vbiasn2 Vbiasn2 net9 gnd! nmos_rvt w=WA l=LA nfin=nA -MM14 Vbiasn2 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR15_1 Vbiasp -*.PININFO Vbiasp:O -RR1 Vbiasp gnd! res=rK -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasn2 LG_Vbiasp2 Vinn Vinp single_ended_cascode_current_mirror -xiLG_load_biasn_LV Biasp LG_Vbiasn2 LG_load_biasn_LV -xibCR15_1 Biasp CR15_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_current_mirror_LG_load_biasn_LV_cr16_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_current_mirror_LG_load_biasn_LV_cr16_1.sp deleted file mode 100644 index dd45c42d63..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_current_mirror_LG_load_biasn_LV_cr16_1.sp +++ /dev/null @@ -1,72 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_cascode_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:41:11 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_cascode_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_cascode_current_mirror Vbiasn Vbiasn2 Vbiasp2 Vinn Vinp -+ Voutn -*.PININFO Vbiasn:I Vbiasn2:I Vbiasp2:I Vinn:I Vinp:I Voutn:O -MM12 net12 Vbiasp2 net37 vdd! pmos_rvt w=WA l=LA nfin=nA -MM11 net23 Vbiasp2 net36 vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net10 Vbiasp2 net35 vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 Voutn Vbiasp2 net34 vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net37 net12 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net36 net23 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM6 net35 net12 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 net34 net23 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM14 net10 Vbiasn2 net33 gnd! nmos_rvt w=WA l=LA nfin=nA -MM13 Voutn Vbiasn2 net31 gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net23 Vinp net17 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vinn net17 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net17 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net33 net10 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 net31 net10 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasn_LV Vbiasn2 Biasp -*.PININFO Biasp:I Vbiasn2:O -MM13 net9 Vbiasn2 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM15 Vbiasn2 Vbiasn2 net9 gnd! nmos_rvt w=WA l=LA nfin=nA -MM14 Vbiasn2 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR16_1 Vbiasp -*.PININFO Vbiasp:O -RR0 vdd! net6 res=rK -RR1 Vbiasp gnd! res=rK -MM2 Vbiasp Vbiasp net6 vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasn2 LG_Vbiasp2 Vinn Vinp single_ended_cascode_current_mirror -xiLG_load_biasn_LV Biasp LG_Vbiasn2 LG_load_biasn_LV -xibCR16_1 Biasp CR16_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_current_mirror_LG_load_biasn_LV_cr2_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_current_mirror_LG_load_biasn_LV_cr2_2.sp deleted file mode 100644 index 079b3c831a..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_current_mirror_LG_load_biasn_LV_cr2_2.sp +++ /dev/null @@ -1,74 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_cascode_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:41:11 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_cascode_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_cascode_current_mirror Vbiasn Vbiasn2 Vbiasp2 Vinn Vinp -+ Voutn -*.PININFO Vbiasn:I Vbiasn2:I Vbiasp2:I Vinn:I Vinp:I Voutn:O -MM12 net12 Vbiasp2 net37 vdd! pmos_rvt w=WA l=LA nfin=nA -MM11 net23 Vbiasp2 net36 vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net10 Vbiasp2 net35 vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 Voutn Vbiasp2 net34 vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net37 net12 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net36 net23 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM6 net35 net12 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 net34 net23 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM14 net10 Vbiasn2 net33 gnd! nmos_rvt w=WA l=LA nfin=nA -MM13 Voutn Vbiasn2 net31 gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net23 Vinp net17 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vinn net17 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net17 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net33 net10 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 net31 net10 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasn_LV Vbiasn2 Biasp -*.PININFO Biasp:I Vbiasn2:O -MM13 net9 Vbiasn2 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM15 Vbiasn2 Vbiasn2 net9 gnd! nmos_rvt w=WA l=LA nfin=nA -MM14 Vbiasn2 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR2_2_wilson Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -RR0 Vbiasn gnd! res=rK -MM2 Vbiasp net12 Vbiasn gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasn2 LG_Vbiasp2 Vinn Vinp single_ended_cascode_current_mirror -xiLG_load_biasn_LV Biasp LG_Vbiasn2 LG_load_biasn_LV -xibCR2_2_wilson Biasn Biasp CR2_2_wilson -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_current_mirror_LG_load_biasn_LV_cr3_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_current_mirror_LG_load_biasn_LV_cr3_2.sp deleted file mode 100644 index fb7cc88761..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_current_mirror_LG_load_biasn_LV_cr3_2.sp +++ /dev/null @@ -1,74 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_cascode_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:41:11 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_cascode_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_cascode_current_mirror Vbiasn Vbiasn2 Vbiasp2 Vinn Vinp -+ Voutn -*.PININFO Vbiasn:I Vbiasn2:I Vbiasp2:I Vinn:I Vinp:I Voutn:O -MM12 net12 Vbiasp2 net37 vdd! pmos_rvt w=WA l=LA nfin=nA -MM11 net23 Vbiasp2 net36 vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net10 Vbiasp2 net35 vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 Voutn Vbiasp2 net34 vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net37 net12 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net36 net23 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM6 net35 net12 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 net34 net23 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM14 net10 Vbiasn2 net33 gnd! nmos_rvt w=WA l=LA nfin=nA -MM13 Voutn Vbiasn2 net31 gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net23 Vinp net17 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vinn net17 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net17 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net33 net10 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 net31 net10 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasn_LV Vbiasn2 Biasp -*.PININFO Biasp:I Vbiasn2:O -MM13 net9 Vbiasn2 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM15 Vbiasn2 Vbiasn2 net9 gnd! nmos_rvt w=WA l=LA nfin=nA -MM14 Vbiasn2 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR3_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 net15 gnd! res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasn2 LG_Vbiasp2 Vinn Vinp single_ended_cascode_current_mirror -xiLG_load_biasn_LV Biasp LG_Vbiasn2 LG_load_biasn_LV -xibCR3_2 Biasn Biasp CR3_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_current_mirror_LG_load_biasn_LV_cr4_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_current_mirror_LG_load_biasn_LV_cr4_2.sp deleted file mode 100644 index 6c3e7831c5..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_current_mirror_LG_load_biasn_LV_cr4_2.sp +++ /dev/null @@ -1,79 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_cascode_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:41:11 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_cascode_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_cascode_current_mirror Vbiasn Vbiasn2 Vbiasp2 Vinn Vinp -+ Voutn -*.PININFO Vbiasn:I Vbiasn2:I Vbiasp2:I Vinn:I Vinp:I Voutn:O -MM12 net12 Vbiasp2 net37 vdd! pmos_rvt w=WA l=LA nfin=nA -MM11 net23 Vbiasp2 net36 vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net10 Vbiasp2 net35 vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 Voutn Vbiasp2 net34 vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net37 net12 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net36 net23 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM6 net35 net12 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 net34 net23 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM14 net10 Vbiasn2 net33 gnd! nmos_rvt w=WA l=LA nfin=nA -MM13 Voutn Vbiasn2 net31 gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net23 Vinp net17 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vinn net17 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net17 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net33 net10 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 net31 net10 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasn_LV Vbiasn2 Biasp -*.PININFO Biasp:I Vbiasn2:O -MM13 net9 Vbiasn2 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM15 Vbiasn2 Vbiasn2 net9 gnd! nmos_rvt w=WA l=LA nfin=nA -MM14 Vbiasn2 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR4_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM11 net023 net024 Vbiasn gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM8 net025 net010 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM9 net024 net024 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM7 net010 net010 net025 gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net025 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 net024 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net010 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasn2 LG_Vbiasp2 Vinn Vinp single_ended_cascode_current_mirror -xiLG_load_biasn_LV Biasp LG_Vbiasn2 LG_load_biasn_LV -xibCR4_2 Biasn Biasp CR4_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_current_mirror_LG_load_biasn_LV_cr5_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_current_mirror_LG_load_biasn_LV_cr5_2.sp deleted file mode 100644 index 6701c07ac0..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_current_mirror_LG_load_biasn_LV_cr5_2.sp +++ /dev/null @@ -1,76 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_cascode_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:41:11 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_cascode_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_cascode_current_mirror Vbiasn Vbiasn2 Vbiasp2 Vinn Vinp -+ Voutn -*.PININFO Vbiasn:I Vbiasn2:I Vbiasp2:I Vinn:I Vinp:I Voutn:O -MM12 net12 Vbiasp2 net37 vdd! pmos_rvt w=WA l=LA nfin=nA -MM11 net23 Vbiasp2 net36 vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net10 Vbiasp2 net35 vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 Voutn Vbiasp2 net34 vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net37 net12 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net36 net23 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM6 net35 net12 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 net34 net23 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM14 net10 Vbiasn2 net33 gnd! nmos_rvt w=WA l=LA nfin=nA -MM13 Voutn Vbiasn2 net31 gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net23 Vinp net17 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vinn net17 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net17 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net33 net10 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 net31 net10 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasn_LV Vbiasn2 Biasp -*.PININFO Biasp:I Vbiasn2:O -MM13 net9 Vbiasn2 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM15 Vbiasn2 Vbiasn2 net9 gnd! nmos_rvt w=WA l=LA nfin=nA -MM14 Vbiasn2 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR5_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM5 net014 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net014 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasn2 LG_Vbiasp2 Vinn Vinp single_ended_cascode_current_mirror -xiLG_load_biasn_LV Biasp LG_Vbiasn2 LG_load_biasn_LV -xibCR5_2 Biasn Biasp CR5_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_current_mirror_LG_load_biasn_LV_cr6_3.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_current_mirror_LG_load_biasn_LV_cr6_3.sp deleted file mode 100644 index e54021bb4e..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_current_mirror_LG_load_biasn_LV_cr6_3.sp +++ /dev/null @@ -1,76 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_cascode_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:41:11 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_cascode_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_cascode_current_mirror Vbiasn Vbiasn2 Vbiasp2 Vinn Vinp -+ Voutn -*.PININFO Vbiasn:I Vbiasn2:I Vbiasp2:I Vinn:I Vinp:I Voutn:O -MM12 net12 Vbiasp2 net37 vdd! pmos_rvt w=WA l=LA nfin=nA -MM11 net23 Vbiasp2 net36 vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net10 Vbiasp2 net35 vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 Voutn Vbiasp2 net34 vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net37 net12 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net36 net23 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM6 net35 net12 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 net34 net23 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM14 net10 Vbiasn2 net33 gnd! nmos_rvt w=WA l=LA nfin=nA -MM13 Voutn Vbiasn2 net31 gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net23 Vinp net17 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vinn net17 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net17 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net33 net10 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 net31 net10 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasn_LV Vbiasn2 Biasp -*.PININFO Biasp:I Vbiasn2:O -MM13 net9 Vbiasn2 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM15 Vbiasn2 Vbiasn2 net9 gnd! nmos_rvt w=WA l=LA nfin=nA -MM14 Vbiasn2 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR6_3 Vbiasn1 Vbiasn2 Vbiasp -*.PININFO Vbiasn1:O Vbiasn2:O Vbiasp:O -MM2 Vbiasp Vbiasn2 Vbiasn1 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn2 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 Vbiasn1 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM5 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn2 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasn2 LG_Vbiasp2 Vinn Vinp single_ended_cascode_current_mirror -xiLG_load_biasn_LV Biasp LG_Vbiasn2 LG_load_biasn_LV -xibCR6_3 Biasn1 Biasn2 Biasp CR6_3 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_current_mirror_pmos_LG_load_biasn_LV_cr13_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_current_mirror_pmos_LG_load_biasn_LV_cr13_1.sp deleted file mode 100644 index 1cc83c568b..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_current_mirror_pmos_LG_load_biasn_LV_cr13_1.sp +++ /dev/null @@ -1,73 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_cascode_current_mirror_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:41:22 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_cascode_current_mirror_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_cascode_current_mirror_pmos Vbiasn2 Vbiasp Vbiasp2 Vinn -+ Vinp Voutp -*.PININFO Vbiasn2:I Vbiasp:I Vbiasp2:I Vinn:I Vinp:I Voutp:O -MM14 net025 net012 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM13 net024 net012 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Voutp Vbiasp2 net025 vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net012 Vbiasp2 net024 vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net11 Vinn net14 net27 pmos_rvt w=WA l=LA nfin=nA -MM6 net16 Vinp net14 net27 pmos_rvt w=WA l=LA nfin=nA -MM5 net14 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM12 net29 net11 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM11 net32 net16 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 net33 net11 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net26 net16 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Voutp Vbiasn2 net29 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net012 Vbiasn2 net32 gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net11 Vbiasn2 net33 gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net16 Vbiasn2 net26 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasn_LV Vbiasn2 Biasp -*.PININFO Biasp:I Vbiasn2:O -MM13 net9 Vbiasn2 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM15 Vbiasn2 Vbiasn2 net9 gnd! nmos_rvt w=WA l=LA nfin=nA -MM14 Vbiasn2 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn2 LG_Vbiasp LG_Vbiasp2 Vinn single_ended_cascode_current_mirror_pmos -xiLG_load_biasn_LV Biasp LG_Vbiasn2 LG_load_biasn_LV -xibCR13_2 Biasn Biasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_current_mirror_pmos_LG_load_biasn_LV_cr13_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_current_mirror_pmos_LG_load_biasn_LV_cr13_2.sp deleted file mode 100644 index 1cc83c568b..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_current_mirror_pmos_LG_load_biasn_LV_cr13_2.sp +++ /dev/null @@ -1,73 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_cascode_current_mirror_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:41:22 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_cascode_current_mirror_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_cascode_current_mirror_pmos Vbiasn2 Vbiasp Vbiasp2 Vinn -+ Vinp Voutp -*.PININFO Vbiasn2:I Vbiasp:I Vbiasp2:I Vinn:I Vinp:I Voutp:O -MM14 net025 net012 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM13 net024 net012 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Voutp Vbiasp2 net025 vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net012 Vbiasp2 net024 vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net11 Vinn net14 net27 pmos_rvt w=WA l=LA nfin=nA -MM6 net16 Vinp net14 net27 pmos_rvt w=WA l=LA nfin=nA -MM5 net14 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM12 net29 net11 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM11 net32 net16 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 net33 net11 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net26 net16 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Voutp Vbiasn2 net29 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net012 Vbiasn2 net32 gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net11 Vbiasn2 net33 gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net16 Vbiasn2 net26 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasn_LV Vbiasn2 Biasp -*.PININFO Biasp:I Vbiasn2:O -MM13 net9 Vbiasn2 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM15 Vbiasn2 Vbiasn2 net9 gnd! nmos_rvt w=WA l=LA nfin=nA -MM14 Vbiasn2 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn2 LG_Vbiasp LG_Vbiasp2 Vinn single_ended_cascode_current_mirror_pmos -xiLG_load_biasn_LV Biasp LG_Vbiasn2 LG_load_biasn_LV -xibCR13_2 Biasn Biasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_current_mirror_pmos_LG_load_biasn_LV_cr14_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_current_mirror_pmos_LG_load_biasn_LV_cr14_2.sp deleted file mode 100644 index 6c409efc4a..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_current_mirror_pmos_LG_load_biasn_LV_cr14_2.sp +++ /dev/null @@ -1,74 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_cascode_current_mirror_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:41:22 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_cascode_current_mirror_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_cascode_current_mirror_pmos Vbiasn2 Vbiasp Vbiasp2 Vinn -+ Vinp Voutp -*.PININFO Vbiasn2:I Vbiasp:I Vbiasp2:I Vinn:I Vinp:I Voutp:O -MM14 net025 net012 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM13 net024 net012 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Voutp Vbiasp2 net025 vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net012 Vbiasp2 net024 vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net11 Vinn net14 net27 pmos_rvt w=WA l=LA nfin=nA -MM6 net16 Vinp net14 net27 pmos_rvt w=WA l=LA nfin=nA -MM5 net14 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM12 net29 net11 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM11 net32 net16 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 net33 net11 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net26 net16 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Voutp Vbiasn2 net29 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net012 Vbiasn2 net32 gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net11 Vbiasn2 net33 gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net16 Vbiasn2 net26 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasn_LV Vbiasn2 Biasp -*.PININFO Biasp:I Vbiasn2:O -MM13 net9 Vbiasn2 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM15 Vbiasn2 Vbiasn2 net9 gnd! nmos_rvt w=WA l=LA nfin=nA -MM14 Vbiasn2 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR14_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net010 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 Vbiasn net010 res=rK -.ENDS - - -xiota LG_Vbiasn2 LG_Vbiasp LG_Vbiasp2 Vinn single_ended_cascode_current_mirror_pmos -xiLG_load_biasn_LV Biasp LG_Vbiasn2 LG_load_biasn_LV -xibCR14_2 Biasn Biasp CR14_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_current_mirror_pmos_LG_load_biasn_LV_cr15_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_current_mirror_pmos_LG_load_biasn_LV_cr15_1.sp deleted file mode 100644 index fd760887ee..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_current_mirror_pmos_LG_load_biasn_LV_cr15_1.sp +++ /dev/null @@ -1,71 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_cascode_current_mirror_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:41:22 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_cascode_current_mirror_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_cascode_current_mirror_pmos Vbiasn2 Vbiasp Vbiasp2 Vinn -+ Vinp Voutp -*.PININFO Vbiasn2:I Vbiasp:I Vbiasp2:I Vinn:I Vinp:I Voutp:O -MM14 net025 net012 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM13 net024 net012 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Voutp Vbiasp2 net025 vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net012 Vbiasp2 net024 vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net11 Vinn net14 net27 pmos_rvt w=WA l=LA nfin=nA -MM6 net16 Vinp net14 net27 pmos_rvt w=WA l=LA nfin=nA -MM5 net14 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM12 net29 net11 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM11 net32 net16 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 net33 net11 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net26 net16 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Voutp Vbiasn2 net29 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net012 Vbiasn2 net32 gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net11 Vbiasn2 net33 gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net16 Vbiasn2 net26 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasn_LV Vbiasn2 Biasp -*.PININFO Biasp:I Vbiasn2:O -MM13 net9 Vbiasn2 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM15 Vbiasn2 Vbiasn2 net9 gnd! nmos_rvt w=WA l=LA nfin=nA -MM14 Vbiasn2 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR15_1 Vbiasp -*.PININFO Vbiasp:O -RR1 Vbiasp gnd! res=rK -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn2 LG_Vbiasp LG_Vbiasp2 Vinn single_ended_cascode_current_mirror_pmos -xiLG_load_biasn_LV Biasp LG_Vbiasn2 LG_load_biasn_LV -xibCR15_1 Biasp CR15_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_current_mirror_pmos_LG_load_biasn_LV_cr16_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_current_mirror_pmos_LG_load_biasn_LV_cr16_1.sp deleted file mode 100644 index 7651d559d1..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_current_mirror_pmos_LG_load_biasn_LV_cr16_1.sp +++ /dev/null @@ -1,72 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_cascode_current_mirror_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:41:22 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_cascode_current_mirror_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_cascode_current_mirror_pmos Vbiasn2 Vbiasp Vbiasp2 Vinn -+ Vinp Voutp -*.PININFO Vbiasn2:I Vbiasp:I Vbiasp2:I Vinn:I Vinp:I Voutp:O -MM14 net025 net012 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM13 net024 net012 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Voutp Vbiasp2 net025 vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net012 Vbiasp2 net024 vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net11 Vinn net14 net27 pmos_rvt w=WA l=LA nfin=nA -MM6 net16 Vinp net14 net27 pmos_rvt w=WA l=LA nfin=nA -MM5 net14 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM12 net29 net11 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM11 net32 net16 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 net33 net11 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net26 net16 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Voutp Vbiasn2 net29 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net012 Vbiasn2 net32 gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net11 Vbiasn2 net33 gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net16 Vbiasn2 net26 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasn_LV Vbiasn2 Biasp -*.PININFO Biasp:I Vbiasn2:O -MM13 net9 Vbiasn2 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM15 Vbiasn2 Vbiasn2 net9 gnd! nmos_rvt w=WA l=LA nfin=nA -MM14 Vbiasn2 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR16_1 Vbiasp -*.PININFO Vbiasp:O -RR0 vdd! net6 res=rK -RR1 Vbiasp gnd! res=rK -MM2 Vbiasp Vbiasp net6 vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn2 LG_Vbiasp LG_Vbiasp2 Vinn single_ended_cascode_current_mirror_pmos -xiLG_load_biasn_LV Biasp LG_Vbiasn2 LG_load_biasn_LV -xibCR16_1 Biasp CR16_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_current_mirror_pmos_LG_load_biasn_LV_cr2_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_current_mirror_pmos_LG_load_biasn_LV_cr2_2.sp deleted file mode 100644 index 5819292f0d..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_current_mirror_pmos_LG_load_biasn_LV_cr2_2.sp +++ /dev/null @@ -1,74 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_cascode_current_mirror_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:41:22 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_cascode_current_mirror_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_cascode_current_mirror_pmos Vbiasn2 Vbiasp Vbiasp2 Vinn -+ Vinp Voutp -*.PININFO Vbiasn2:I Vbiasp:I Vbiasp2:I Vinn:I Vinp:I Voutp:O -MM14 net025 net012 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM13 net024 net012 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Voutp Vbiasp2 net025 vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net012 Vbiasp2 net024 vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net11 Vinn net14 net27 pmos_rvt w=WA l=LA nfin=nA -MM6 net16 Vinp net14 net27 pmos_rvt w=WA l=LA nfin=nA -MM5 net14 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM12 net29 net11 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM11 net32 net16 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 net33 net11 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net26 net16 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Voutp Vbiasn2 net29 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net012 Vbiasn2 net32 gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net11 Vbiasn2 net33 gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net16 Vbiasn2 net26 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasn_LV Vbiasn2 Biasp -*.PININFO Biasp:I Vbiasn2:O -MM13 net9 Vbiasn2 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM15 Vbiasn2 Vbiasn2 net9 gnd! nmos_rvt w=WA l=LA nfin=nA -MM14 Vbiasn2 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR2_2_wilson Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -RR0 Vbiasn gnd! res=rK -MM2 Vbiasp net12 Vbiasn gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn2 LG_Vbiasp LG_Vbiasp2 Vinn single_ended_cascode_current_mirror_pmos -xiLG_load_biasn_LV Biasp LG_Vbiasn2 LG_load_biasn_LV -xibCR2_2_wilson Biasn Biasp CR2_2_wilson -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_current_mirror_pmos_LG_load_biasn_LV_cr3_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_current_mirror_pmos_LG_load_biasn_LV_cr3_2.sp deleted file mode 100644 index 069e880589..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_current_mirror_pmos_LG_load_biasn_LV_cr3_2.sp +++ /dev/null @@ -1,74 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_cascode_current_mirror_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:41:22 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_cascode_current_mirror_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_cascode_current_mirror_pmos Vbiasn2 Vbiasp Vbiasp2 Vinn -+ Vinp Voutp -*.PININFO Vbiasn2:I Vbiasp:I Vbiasp2:I Vinn:I Vinp:I Voutp:O -MM14 net025 net012 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM13 net024 net012 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Voutp Vbiasp2 net025 vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net012 Vbiasp2 net024 vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net11 Vinn net14 net27 pmos_rvt w=WA l=LA nfin=nA -MM6 net16 Vinp net14 net27 pmos_rvt w=WA l=LA nfin=nA -MM5 net14 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM12 net29 net11 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM11 net32 net16 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 net33 net11 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net26 net16 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Voutp Vbiasn2 net29 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net012 Vbiasn2 net32 gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net11 Vbiasn2 net33 gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net16 Vbiasn2 net26 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasn_LV Vbiasn2 Biasp -*.PININFO Biasp:I Vbiasn2:O -MM13 net9 Vbiasn2 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM15 Vbiasn2 Vbiasn2 net9 gnd! nmos_rvt w=WA l=LA nfin=nA -MM14 Vbiasn2 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR3_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 net15 gnd! res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn2 LG_Vbiasp LG_Vbiasp2 Vinn single_ended_cascode_current_mirror_pmos -xiLG_load_biasn_LV Biasp LG_Vbiasn2 LG_load_biasn_LV -xibCR3_2 Biasn Biasp CR3_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_current_mirror_pmos_LG_load_biasn_LV_cr4_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_current_mirror_pmos_LG_load_biasn_LV_cr4_2.sp deleted file mode 100644 index 71e721d7ef..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_current_mirror_pmos_LG_load_biasn_LV_cr4_2.sp +++ /dev/null @@ -1,79 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_cascode_current_mirror_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:41:22 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_cascode_current_mirror_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_cascode_current_mirror_pmos Vbiasn2 Vbiasp Vbiasp2 Vinn -+ Vinp Voutp -*.PININFO Vbiasn2:I Vbiasp:I Vbiasp2:I Vinn:I Vinp:I Voutp:O -MM14 net025 net012 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM13 net024 net012 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Voutp Vbiasp2 net025 vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net012 Vbiasp2 net024 vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net11 Vinn net14 net27 pmos_rvt w=WA l=LA nfin=nA -MM6 net16 Vinp net14 net27 pmos_rvt w=WA l=LA nfin=nA -MM5 net14 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM12 net29 net11 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM11 net32 net16 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 net33 net11 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net26 net16 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Voutp Vbiasn2 net29 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net012 Vbiasn2 net32 gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net11 Vbiasn2 net33 gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net16 Vbiasn2 net26 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasn_LV Vbiasn2 Biasp -*.PININFO Biasp:I Vbiasn2:O -MM13 net9 Vbiasn2 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM15 Vbiasn2 Vbiasn2 net9 gnd! nmos_rvt w=WA l=LA nfin=nA -MM14 Vbiasn2 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR4_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM11 net023 net024 Vbiasn gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM8 net025 net010 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM9 net024 net024 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM7 net010 net010 net025 gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net025 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 net024 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net010 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn2 LG_Vbiasp LG_Vbiasp2 Vinn single_ended_cascode_current_mirror_pmos -xiLG_load_biasn_LV Biasp LG_Vbiasn2 LG_load_biasn_LV -xibCR4_2 Biasn Biasp CR4_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_current_mirror_pmos_LG_load_biasn_LV_cr5_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_current_mirror_pmos_LG_load_biasn_LV_cr5_2.sp deleted file mode 100644 index 254dddc208..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_current_mirror_pmos_LG_load_biasn_LV_cr5_2.sp +++ /dev/null @@ -1,76 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_cascode_current_mirror_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:41:22 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_cascode_current_mirror_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_cascode_current_mirror_pmos Vbiasn2 Vbiasp Vbiasp2 Vinn -+ Vinp Voutp -*.PININFO Vbiasn2:I Vbiasp:I Vbiasp2:I Vinn:I Vinp:I Voutp:O -MM14 net025 net012 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM13 net024 net012 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Voutp Vbiasp2 net025 vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net012 Vbiasp2 net024 vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net11 Vinn net14 net27 pmos_rvt w=WA l=LA nfin=nA -MM6 net16 Vinp net14 net27 pmos_rvt w=WA l=LA nfin=nA -MM5 net14 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM12 net29 net11 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM11 net32 net16 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 net33 net11 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net26 net16 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Voutp Vbiasn2 net29 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net012 Vbiasn2 net32 gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net11 Vbiasn2 net33 gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net16 Vbiasn2 net26 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasn_LV Vbiasn2 Biasp -*.PININFO Biasp:I Vbiasn2:O -MM13 net9 Vbiasn2 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM15 Vbiasn2 Vbiasn2 net9 gnd! nmos_rvt w=WA l=LA nfin=nA -MM14 Vbiasn2 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR5_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM5 net014 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net014 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn2 LG_Vbiasp LG_Vbiasp2 Vinn single_ended_cascode_current_mirror_pmos -xiLG_load_biasn_LV Biasp LG_Vbiasn2 LG_load_biasn_LV -xibCR5_2 Biasn Biasp CR5_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_current_mirror_pmos_LG_load_biasn_LV_cr6_3.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_current_mirror_pmos_LG_load_biasn_LV_cr6_3.sp deleted file mode 100644 index dee0155425..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_current_mirror_pmos_LG_load_biasn_LV_cr6_3.sp +++ /dev/null @@ -1,76 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_cascode_current_mirror_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:41:22 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_cascode_current_mirror_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_cascode_current_mirror_pmos Vbiasn2 Vbiasp Vbiasp2 Vinn -+ Vinp Voutp -*.PININFO Vbiasn2:I Vbiasp:I Vbiasp2:I Vinn:I Vinp:I Voutp:O -MM14 net025 net012 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM13 net024 net012 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Voutp Vbiasp2 net025 vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net012 Vbiasp2 net024 vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net11 Vinn net14 net27 pmos_rvt w=WA l=LA nfin=nA -MM6 net16 Vinp net14 net27 pmos_rvt w=WA l=LA nfin=nA -MM5 net14 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM12 net29 net11 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM11 net32 net16 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 net33 net11 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net26 net16 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Voutp Vbiasn2 net29 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net012 Vbiasn2 net32 gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net11 Vbiasn2 net33 gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net16 Vbiasn2 net26 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasn_LV Vbiasn2 Biasp -*.PININFO Biasp:I Vbiasn2:O -MM13 net9 Vbiasn2 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM15 Vbiasn2 Vbiasn2 net9 gnd! nmos_rvt w=WA l=LA nfin=nA -MM14 Vbiasn2 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR6_3 Vbiasn1 Vbiasn2 Vbiasp -*.PININFO Vbiasn1:O Vbiasn2:O Vbiasp:O -MM2 Vbiasp Vbiasn2 Vbiasn1 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn2 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 Vbiasn1 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM5 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn2 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn2 LG_Vbiasp LG_Vbiasp2 Vinn single_ended_cascode_current_mirror_pmos -xiLG_load_biasn_LV Biasp LG_Vbiasn2 LG_load_biasn_LV -xibCR6_3 Biasn1 Biasn2 Biasp CR6_3 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_pmos_LG_load_biasn_LV_cr13_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_pmos_LG_load_biasn_LV_cr13_1.sp deleted file mode 100644 index d8a1227872..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_pmos_LG_load_biasn_LV_cr13_1.sp +++ /dev/null @@ -1,69 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_cascode_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:07:21 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_cascode_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_cascode_pmos Vbiasn1 Vbiasn2 Vbiasp1 Vbiasp2 Vinn Vinp -+ Voutp -*.PININFO Vbiasp1:I Vbiasp2:I Vinn:I Vinp:I Vbiasn1:O Vbiasn2:O Voutp:O -MM4 net28 Vinn net12 net22 pmos_rvt w=WA l=LA nfin=nA -MM3 net29 Vinp net12 net22 pmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM6 net16 Vbiasp2 net25 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp Vbiasp2 net24 vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net25 net16 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net24 net16 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net29 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net28 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net16 Vbiasn2 net29 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp Vbiasn2 net28 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasn_LV Vbiasn2 Biasp -*.PININFO Biasp:I Vbiasn2:O -MM13 net9 Vbiasn2 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM15 Vbiasn2 Vbiasn2 net9 gnd! nmos_rvt w=WA l=LA nfin=nA -MM14 Vbiasn2 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn1 LG_Vbiasn2 LG_Vbiasp1 LG_Vbiasp2 Vinn Vinp single_ended_cascode_pmos -xiLG_load_biasn_LV Biasp LG_Vbiasn2 LG_load_biasn_LV -xibCR13_2 Biasn Biasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_pmos_LG_load_biasn_LV_cr13_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_pmos_LG_load_biasn_LV_cr13_2.sp deleted file mode 100644 index d8a1227872..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_pmos_LG_load_biasn_LV_cr13_2.sp +++ /dev/null @@ -1,69 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_cascode_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:07:21 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_cascode_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_cascode_pmos Vbiasn1 Vbiasn2 Vbiasp1 Vbiasp2 Vinn Vinp -+ Voutp -*.PININFO Vbiasp1:I Vbiasp2:I Vinn:I Vinp:I Vbiasn1:O Vbiasn2:O Voutp:O -MM4 net28 Vinn net12 net22 pmos_rvt w=WA l=LA nfin=nA -MM3 net29 Vinp net12 net22 pmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM6 net16 Vbiasp2 net25 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp Vbiasp2 net24 vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net25 net16 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net24 net16 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net29 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net28 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net16 Vbiasn2 net29 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp Vbiasn2 net28 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasn_LV Vbiasn2 Biasp -*.PININFO Biasp:I Vbiasn2:O -MM13 net9 Vbiasn2 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM15 Vbiasn2 Vbiasn2 net9 gnd! nmos_rvt w=WA l=LA nfin=nA -MM14 Vbiasn2 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn1 LG_Vbiasn2 LG_Vbiasp1 LG_Vbiasp2 Vinn Vinp single_ended_cascode_pmos -xiLG_load_biasn_LV Biasp LG_Vbiasn2 LG_load_biasn_LV -xibCR13_2 Biasn Biasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_pmos_LG_load_biasn_LV_cr14_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_pmos_LG_load_biasn_LV_cr14_2.sp deleted file mode 100644 index 0f5d39cb62..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_pmos_LG_load_biasn_LV_cr14_2.sp +++ /dev/null @@ -1,70 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_cascode_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:07:21 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_cascode_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_cascode_pmos Vbiasn1 Vbiasn2 Vbiasp1 Vbiasp2 Vinn Vinp -+ Voutp -*.PININFO Vbiasp1:I Vbiasp2:I Vinn:I Vinp:I Vbiasn1:O Vbiasn2:O Voutp:O -MM4 net28 Vinn net12 net22 pmos_rvt w=WA l=LA nfin=nA -MM3 net29 Vinp net12 net22 pmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM6 net16 Vbiasp2 net25 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp Vbiasp2 net24 vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net25 net16 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net24 net16 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net29 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net28 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net16 Vbiasn2 net29 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp Vbiasn2 net28 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasn_LV Vbiasn2 Biasp -*.PININFO Biasp:I Vbiasn2:O -MM13 net9 Vbiasn2 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM15 Vbiasn2 Vbiasn2 net9 gnd! nmos_rvt w=WA l=LA nfin=nA -MM14 Vbiasn2 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR14_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net010 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 Vbiasn net010 res=rK -.ENDS - - -xiota LG_Vbiasn1 LG_Vbiasn2 LG_Vbiasp1 LG_Vbiasp2 Vinn Vinp single_ended_cascode_pmos -xiLG_load_biasn_LV Biasp LG_Vbiasn2 LG_load_biasn_LV -xibCR14_2 Biasn Biasp CR14_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_pmos_LG_load_biasn_LV_cr15_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_pmos_LG_load_biasn_LV_cr15_1.sp deleted file mode 100644 index 524a14d1a4..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_pmos_LG_load_biasn_LV_cr15_1.sp +++ /dev/null @@ -1,67 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_cascode_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:07:21 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_cascode_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_cascode_pmos Vbiasn1 Vbiasn2 Vbiasp1 Vbiasp2 Vinn Vinp -+ Voutp -*.PININFO Vbiasp1:I Vbiasp2:I Vinn:I Vinp:I Vbiasn1:O Vbiasn2:O Voutp:O -MM4 net28 Vinn net12 net22 pmos_rvt w=WA l=LA nfin=nA -MM3 net29 Vinp net12 net22 pmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM6 net16 Vbiasp2 net25 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp Vbiasp2 net24 vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net25 net16 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net24 net16 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net29 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net28 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net16 Vbiasn2 net29 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp Vbiasn2 net28 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasn_LV Vbiasn2 Biasp -*.PININFO Biasp:I Vbiasn2:O -MM13 net9 Vbiasn2 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM15 Vbiasn2 Vbiasn2 net9 gnd! nmos_rvt w=WA l=LA nfin=nA -MM14 Vbiasn2 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR15_1 Vbiasp -*.PININFO Vbiasp:O -RR1 Vbiasp gnd! res=rK -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn1 LG_Vbiasn2 LG_Vbiasp1 LG_Vbiasp2 Vinn Vinp single_ended_cascode_pmos -xiLG_load_biasn_LV Biasp LG_Vbiasn2 LG_load_biasn_LV -xibCR15_1 Biasp CR15_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_pmos_LG_load_biasn_LV_cr16_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_pmos_LG_load_biasn_LV_cr16_1.sp deleted file mode 100644 index 090a78773a..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_pmos_LG_load_biasn_LV_cr16_1.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_cascode_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:07:21 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_cascode_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_cascode_pmos Vbiasn1 Vbiasn2 Vbiasp1 Vbiasp2 Vinn Vinp -+ Voutp -*.PININFO Vbiasp1:I Vbiasp2:I Vinn:I Vinp:I Vbiasn1:O Vbiasn2:O Voutp:O -MM4 net28 Vinn net12 net22 pmos_rvt w=WA l=LA nfin=nA -MM3 net29 Vinp net12 net22 pmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM6 net16 Vbiasp2 net25 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp Vbiasp2 net24 vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net25 net16 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net24 net16 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net29 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net28 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net16 Vbiasn2 net29 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp Vbiasn2 net28 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasn_LV Vbiasn2 Biasp -*.PININFO Biasp:I Vbiasn2:O -MM13 net9 Vbiasn2 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM15 Vbiasn2 Vbiasn2 net9 gnd! nmos_rvt w=WA l=LA nfin=nA -MM14 Vbiasn2 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR16_1 Vbiasp -*.PININFO Vbiasp:O -RR0 vdd! net6 res=rK -RR1 Vbiasp gnd! res=rK -MM2 Vbiasp Vbiasp net6 vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn1 LG_Vbiasn2 LG_Vbiasp1 LG_Vbiasp2 Vinn Vinp single_ended_cascode_pmos -xiLG_load_biasn_LV Biasp LG_Vbiasn2 LG_load_biasn_LV -xibCR16_1 Biasp CR16_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_pmos_LG_load_biasn_LV_cr2_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_pmos_LG_load_biasn_LV_cr2_2.sp deleted file mode 100644 index ebf83be61c..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_pmos_LG_load_biasn_LV_cr2_2.sp +++ /dev/null @@ -1,70 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_cascode_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:07:21 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_cascode_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_cascode_pmos Vbiasn1 Vbiasn2 Vbiasp1 Vbiasp2 Vinn Vinp -+ Voutp -*.PININFO Vbiasp1:I Vbiasp2:I Vinn:I Vinp:I Vbiasn1:O Vbiasn2:O Voutp:O -MM4 net28 Vinn net12 net22 pmos_rvt w=WA l=LA nfin=nA -MM3 net29 Vinp net12 net22 pmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM6 net16 Vbiasp2 net25 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp Vbiasp2 net24 vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net25 net16 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net24 net16 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net29 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net28 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net16 Vbiasn2 net29 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp Vbiasn2 net28 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasn_LV Vbiasn2 Biasp -*.PININFO Biasp:I Vbiasn2:O -MM13 net9 Vbiasn2 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM15 Vbiasn2 Vbiasn2 net9 gnd! nmos_rvt w=WA l=LA nfin=nA -MM14 Vbiasn2 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR2_2_wilson Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -RR0 Vbiasn gnd! res=rK -MM2 Vbiasp net12 Vbiasn gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn1 LG_Vbiasn2 LG_Vbiasp1 LG_Vbiasp2 Vinn Vinp single_ended_cascode_pmos -xiLG_load_biasn_LV Biasp LG_Vbiasn2 LG_load_biasn_LV -xibCR2_2_wilson Biasn Biasp CR2_2_wilson -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_pmos_LG_load_biasn_LV_cr3_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_pmos_LG_load_biasn_LV_cr3_2.sp deleted file mode 100644 index 0046a66a02..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_pmos_LG_load_biasn_LV_cr3_2.sp +++ /dev/null @@ -1,70 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_cascode_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:07:21 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_cascode_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_cascode_pmos Vbiasn1 Vbiasn2 Vbiasp1 Vbiasp2 Vinn Vinp -+ Voutp -*.PININFO Vbiasp1:I Vbiasp2:I Vinn:I Vinp:I Vbiasn1:O Vbiasn2:O Voutp:O -MM4 net28 Vinn net12 net22 pmos_rvt w=WA l=LA nfin=nA -MM3 net29 Vinp net12 net22 pmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM6 net16 Vbiasp2 net25 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp Vbiasp2 net24 vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net25 net16 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net24 net16 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net29 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net28 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net16 Vbiasn2 net29 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp Vbiasn2 net28 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasn_LV Vbiasn2 Biasp -*.PININFO Biasp:I Vbiasn2:O -MM13 net9 Vbiasn2 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM15 Vbiasn2 Vbiasn2 net9 gnd! nmos_rvt w=WA l=LA nfin=nA -MM14 Vbiasn2 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR3_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 net15 gnd! res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn1 LG_Vbiasn2 LG_Vbiasp1 LG_Vbiasp2 Vinn Vinp single_ended_cascode_pmos -xiLG_load_biasn_LV Biasp LG_Vbiasn2 LG_load_biasn_LV -xibCR3_2 Biasn Biasp CR3_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_pmos_LG_load_biasn_LV_cr4_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_pmos_LG_load_biasn_LV_cr4_2.sp deleted file mode 100644 index 190233d142..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_pmos_LG_load_biasn_LV_cr4_2.sp +++ /dev/null @@ -1,75 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_cascode_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:07:21 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_cascode_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_cascode_pmos Vbiasn1 Vbiasn2 Vbiasp1 Vbiasp2 Vinn Vinp -+ Voutp -*.PININFO Vbiasp1:I Vbiasp2:I Vinn:I Vinp:I Vbiasn1:O Vbiasn2:O Voutp:O -MM4 net28 Vinn net12 net22 pmos_rvt w=WA l=LA nfin=nA -MM3 net29 Vinp net12 net22 pmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM6 net16 Vbiasp2 net25 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp Vbiasp2 net24 vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net25 net16 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net24 net16 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net29 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net28 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net16 Vbiasn2 net29 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp Vbiasn2 net28 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasn_LV Vbiasn2 Biasp -*.PININFO Biasp:I Vbiasn2:O -MM13 net9 Vbiasn2 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM15 Vbiasn2 Vbiasn2 net9 gnd! nmos_rvt w=WA l=LA nfin=nA -MM14 Vbiasn2 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR4_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM11 net023 net024 Vbiasn gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM8 net025 net010 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM9 net024 net024 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM7 net010 net010 net025 gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net025 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 net024 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net010 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn1 LG_Vbiasn2 LG_Vbiasp1 LG_Vbiasp2 Vinn Vinp single_ended_cascode_pmos -xiLG_load_biasn_LV Biasp LG_Vbiasn2 LG_load_biasn_LV -xibCR4_2 Biasn Biasp CR4_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_pmos_LG_load_biasn_LV_cr5_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_pmos_LG_load_biasn_LV_cr5_2.sp deleted file mode 100644 index 0330681871..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_pmos_LG_load_biasn_LV_cr5_2.sp +++ /dev/null @@ -1,72 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_cascode_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:07:21 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_cascode_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_cascode_pmos Vbiasn1 Vbiasn2 Vbiasp1 Vbiasp2 Vinn Vinp -+ Voutp -*.PININFO Vbiasp1:I Vbiasp2:I Vinn:I Vinp:I Vbiasn1:O Vbiasn2:O Voutp:O -MM4 net28 Vinn net12 net22 pmos_rvt w=WA l=LA nfin=nA -MM3 net29 Vinp net12 net22 pmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM6 net16 Vbiasp2 net25 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp Vbiasp2 net24 vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net25 net16 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net24 net16 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net29 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net28 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net16 Vbiasn2 net29 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp Vbiasn2 net28 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasn_LV Vbiasn2 Biasp -*.PININFO Biasp:I Vbiasn2:O -MM13 net9 Vbiasn2 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM15 Vbiasn2 Vbiasn2 net9 gnd! nmos_rvt w=WA l=LA nfin=nA -MM14 Vbiasn2 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR5_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM5 net014 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net014 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn1 LG_Vbiasn2 LG_Vbiasp1 LG_Vbiasp2 Vinn Vinp single_ended_cascode_pmos -xiLG_load_biasn_LV Biasp LG_Vbiasn2 LG_load_biasn_LV -xibCR5_2 Biasn Biasp CR5_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_pmos_LG_load_biasn_LV_cr6_3.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_pmos_LG_load_biasn_LV_cr6_3.sp deleted file mode 100644 index 26492178a6..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_pmos_LG_load_biasn_LV_cr6_3.sp +++ /dev/null @@ -1,72 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_cascode_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:07:21 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_cascode_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_cascode_pmos Vbiasn1 Vbiasn2 Vbiasp1 Vbiasp2 Vinn Vinp -+ Voutp -*.PININFO Vbiasp1:I Vbiasp2:I Vinn:I Vinp:I Vbiasn1:O Vbiasn2:O Voutp:O -MM4 net28 Vinn net12 net22 pmos_rvt w=WA l=LA nfin=nA -MM3 net29 Vinp net12 net22 pmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM6 net16 Vbiasp2 net25 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp Vbiasp2 net24 vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net25 net16 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net24 net16 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net29 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net28 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net16 Vbiasn2 net29 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp Vbiasn2 net28 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasn_LV Vbiasn2 Biasp -*.PININFO Biasp:I Vbiasn2:O -MM13 net9 Vbiasn2 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM15 Vbiasn2 Vbiasn2 net9 gnd! nmos_rvt w=WA l=LA nfin=nA -MM14 Vbiasn2 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR6_3 Vbiasn1 Vbiasn2 Vbiasp -*.PININFO Vbiasn1:O Vbiasn2:O Vbiasp:O -MM2 Vbiasp Vbiasn2 Vbiasn1 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn2 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 Vbiasn1 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM5 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn2 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn1 LG_Vbiasn2 LG_Vbiasp1 LG_Vbiasp2 Vinn Vinp single_ended_cascode_pmos -xiLG_load_biasn_LV Biasp LG_Vbiasn2 LG_load_biasn_LV -xibCR6_3 Biasn1 Biasn2 Biasp CR6_3 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_pmos_LG_load_biasn_cr13_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_pmos_LG_load_biasn_cr13_1.sp deleted file mode 100644 index 9bcdd0ad72..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_pmos_LG_load_biasn_cr13_1.sp +++ /dev/null @@ -1,69 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_cascode_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:07:21 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_cascode_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_cascode_pmos Vbiasn1 Vbiasn2 Vbiasp1 Vbiasp2 Vinn Vinp -+ Voutp -*.PININFO Vbiasp1:I Vbiasp2:I Vinn:I Vinp:I Vbiasn1:O Vbiasn2:O Voutp:O -MM4 net28 Vinn net12 net22 pmos_rvt w=WA l=LA nfin=nA -MM3 net29 Vinp net12 net22 pmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM6 net16 Vbiasp2 net25 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp Vbiasp2 net24 vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net25 net16 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net24 net16 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net29 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net28 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net16 Vbiasn2 net29 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp Vbiasn2 net28 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasn Vbiasn1 Vbiasn2 Biasp -*.PININFO Biasp:I Vbiasn1:O Vbiasn2:O -MM15 Vbiasn2 Vbiasn2 Vbiasn1 gnd! nmos_rvt w=WA l=LA nfin=nA -MM13 Vbiasn1 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM14 Vbiasn2 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn1 LG_Vbiasn2 LG_Vbiasp1 LG_Vbiasp2 Vinn Vinp single_ended_cascode_pmos -xiLG_load_biasn Biasp LG_Vbiasn1 LG_Vbiasn2 LG_load_biasn -xibCR13_2 Biasn Biasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_pmos_LG_load_biasn_cr13_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_pmos_LG_load_biasn_cr13_2.sp deleted file mode 100644 index 9bcdd0ad72..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_pmos_LG_load_biasn_cr13_2.sp +++ /dev/null @@ -1,69 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_cascode_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:07:21 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_cascode_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_cascode_pmos Vbiasn1 Vbiasn2 Vbiasp1 Vbiasp2 Vinn Vinp -+ Voutp -*.PININFO Vbiasp1:I Vbiasp2:I Vinn:I Vinp:I Vbiasn1:O Vbiasn2:O Voutp:O -MM4 net28 Vinn net12 net22 pmos_rvt w=WA l=LA nfin=nA -MM3 net29 Vinp net12 net22 pmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM6 net16 Vbiasp2 net25 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp Vbiasp2 net24 vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net25 net16 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net24 net16 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net29 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net28 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net16 Vbiasn2 net29 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp Vbiasn2 net28 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasn Vbiasn1 Vbiasn2 Biasp -*.PININFO Biasp:I Vbiasn1:O Vbiasn2:O -MM15 Vbiasn2 Vbiasn2 Vbiasn1 gnd! nmos_rvt w=WA l=LA nfin=nA -MM13 Vbiasn1 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM14 Vbiasn2 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn1 LG_Vbiasn2 LG_Vbiasp1 LG_Vbiasp2 Vinn Vinp single_ended_cascode_pmos -xiLG_load_biasn Biasp LG_Vbiasn1 LG_Vbiasn2 LG_load_biasn -xibCR13_2 Biasn Biasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_pmos_LG_load_biasn_cr14_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_pmos_LG_load_biasn_cr14_2.sp deleted file mode 100644 index c47dbd4f6d..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_pmos_LG_load_biasn_cr14_2.sp +++ /dev/null @@ -1,70 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_cascode_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:07:21 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_cascode_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_cascode_pmos Vbiasn1 Vbiasn2 Vbiasp1 Vbiasp2 Vinn Vinp -+ Voutp -*.PININFO Vbiasp1:I Vbiasp2:I Vinn:I Vinp:I Vbiasn1:O Vbiasn2:O Voutp:O -MM4 net28 Vinn net12 net22 pmos_rvt w=WA l=LA nfin=nA -MM3 net29 Vinp net12 net22 pmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM6 net16 Vbiasp2 net25 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp Vbiasp2 net24 vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net25 net16 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net24 net16 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net29 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net28 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net16 Vbiasn2 net29 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp Vbiasn2 net28 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasn Vbiasn1 Vbiasn2 Biasp -*.PININFO Biasp:I Vbiasn1:O Vbiasn2:O -MM15 Vbiasn2 Vbiasn2 Vbiasn1 gnd! nmos_rvt w=WA l=LA nfin=nA -MM13 Vbiasn1 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM14 Vbiasn2 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR14_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net010 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 Vbiasn net010 res=rK -.ENDS - - -xiota LG_Vbiasn1 LG_Vbiasn2 LG_Vbiasp1 LG_Vbiasp2 Vinn Vinp single_ended_cascode_pmos -xiLG_load_biasn Biasp LG_Vbiasn1 LG_Vbiasn2 LG_load_biasn -xibCR14_2 Biasn Biasp CR14_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_pmos_LG_load_biasn_cr15_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_pmos_LG_load_biasn_cr15_1.sp deleted file mode 100644 index ad913d62c5..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_pmos_LG_load_biasn_cr15_1.sp +++ /dev/null @@ -1,67 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_cascode_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:07:21 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_cascode_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_cascode_pmos Vbiasn1 Vbiasn2 Vbiasp1 Vbiasp2 Vinn Vinp -+ Voutp -*.PININFO Vbiasp1:I Vbiasp2:I Vinn:I Vinp:I Vbiasn1:O Vbiasn2:O Voutp:O -MM4 net28 Vinn net12 net22 pmos_rvt w=WA l=LA nfin=nA -MM3 net29 Vinp net12 net22 pmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM6 net16 Vbiasp2 net25 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp Vbiasp2 net24 vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net25 net16 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net24 net16 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net29 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net28 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net16 Vbiasn2 net29 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp Vbiasn2 net28 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasn Vbiasn1 Vbiasn2 Biasp -*.PININFO Biasp:I Vbiasn1:O Vbiasn2:O -MM15 Vbiasn2 Vbiasn2 Vbiasn1 gnd! nmos_rvt w=WA l=LA nfin=nA -MM13 Vbiasn1 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM14 Vbiasn2 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR15_1 Vbiasp -*.PININFO Vbiasp:O -RR1 Vbiasp gnd! res=rK -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn1 LG_Vbiasn2 LG_Vbiasp1 LG_Vbiasp2 Vinn Vinp single_ended_cascode_pmos -xiLG_load_biasn Biasp LG_Vbiasn1 LG_Vbiasn2 LG_load_biasn -xibCR15_1 Biasp CR15_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_pmos_LG_load_biasn_cr16_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_pmos_LG_load_biasn_cr16_1.sp deleted file mode 100644 index 37d0736617..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_pmos_LG_load_biasn_cr16_1.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_cascode_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:07:21 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_cascode_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_cascode_pmos Vbiasn1 Vbiasn2 Vbiasp1 Vbiasp2 Vinn Vinp -+ Voutp -*.PININFO Vbiasp1:I Vbiasp2:I Vinn:I Vinp:I Vbiasn1:O Vbiasn2:O Voutp:O -MM4 net28 Vinn net12 net22 pmos_rvt w=WA l=LA nfin=nA -MM3 net29 Vinp net12 net22 pmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM6 net16 Vbiasp2 net25 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp Vbiasp2 net24 vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net25 net16 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net24 net16 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net29 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net28 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net16 Vbiasn2 net29 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp Vbiasn2 net28 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasn Vbiasn1 Vbiasn2 Biasp -*.PININFO Biasp:I Vbiasn1:O Vbiasn2:O -MM15 Vbiasn2 Vbiasn2 Vbiasn1 gnd! nmos_rvt w=WA l=LA nfin=nA -MM13 Vbiasn1 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM14 Vbiasn2 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR16_1 Vbiasp -*.PININFO Vbiasp:O -RR0 vdd! net6 res=rK -RR1 Vbiasp gnd! res=rK -MM2 Vbiasp Vbiasp net6 vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn1 LG_Vbiasn2 LG_Vbiasp1 LG_Vbiasp2 Vinn Vinp single_ended_cascode_pmos -xiLG_load_biasn Biasp LG_Vbiasn1 LG_Vbiasn2 LG_load_biasn -xibCR16_1 Biasp CR16_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_pmos_LG_load_biasn_cr2_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_pmos_LG_load_biasn_cr2_2.sp deleted file mode 100644 index 9c2f58180e..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_pmos_LG_load_biasn_cr2_2.sp +++ /dev/null @@ -1,70 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_cascode_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:07:21 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_cascode_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_cascode_pmos Vbiasn1 Vbiasn2 Vbiasp1 Vbiasp2 Vinn Vinp -+ Voutp -*.PININFO Vbiasp1:I Vbiasp2:I Vinn:I Vinp:I Vbiasn1:O Vbiasn2:O Voutp:O -MM4 net28 Vinn net12 net22 pmos_rvt w=WA l=LA nfin=nA -MM3 net29 Vinp net12 net22 pmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM6 net16 Vbiasp2 net25 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp Vbiasp2 net24 vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net25 net16 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net24 net16 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net29 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net28 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net16 Vbiasn2 net29 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp Vbiasn2 net28 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasn Vbiasn1 Vbiasn2 Biasp -*.PININFO Biasp:I Vbiasn1:O Vbiasn2:O -MM15 Vbiasn2 Vbiasn2 Vbiasn1 gnd! nmos_rvt w=WA l=LA nfin=nA -MM13 Vbiasn1 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM14 Vbiasn2 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR2_2_wilson Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -RR0 Vbiasn gnd! res=rK -MM2 Vbiasp net12 Vbiasn gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn1 LG_Vbiasn2 LG_Vbiasp1 LG_Vbiasp2 Vinn Vinp single_ended_cascode_pmos -xiLG_load_biasn Biasp LG_Vbiasn1 LG_Vbiasn2 LG_load_biasn -xibCR2_2_wilson Biasn Biasp CR2_2_wilson -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_pmos_LG_load_biasn_cr3_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_pmos_LG_load_biasn_cr3_2.sp deleted file mode 100644 index c997a28632..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_pmos_LG_load_biasn_cr3_2.sp +++ /dev/null @@ -1,70 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_cascode_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:07:21 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_cascode_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_cascode_pmos Vbiasn1 Vbiasn2 Vbiasp1 Vbiasp2 Vinn Vinp -+ Voutp -*.PININFO Vbiasp1:I Vbiasp2:I Vinn:I Vinp:I Vbiasn1:O Vbiasn2:O Voutp:O -MM4 net28 Vinn net12 net22 pmos_rvt w=WA l=LA nfin=nA -MM3 net29 Vinp net12 net22 pmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM6 net16 Vbiasp2 net25 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp Vbiasp2 net24 vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net25 net16 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net24 net16 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net29 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net28 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net16 Vbiasn2 net29 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp Vbiasn2 net28 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasn Vbiasn1 Vbiasn2 Biasp -*.PININFO Biasp:I Vbiasn1:O Vbiasn2:O -MM15 Vbiasn2 Vbiasn2 Vbiasn1 gnd! nmos_rvt w=WA l=LA nfin=nA -MM13 Vbiasn1 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM14 Vbiasn2 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR3_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 net15 gnd! res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn1 LG_Vbiasn2 LG_Vbiasp1 LG_Vbiasp2 Vinn Vinp single_ended_cascode_pmos -xiLG_load_biasn Biasp LG_Vbiasn1 LG_Vbiasn2 LG_load_biasn -xibCR3_2 Biasn Biasp CR3_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_pmos_LG_load_biasn_cr4_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_pmos_LG_load_biasn_cr4_2.sp deleted file mode 100644 index 18dcc7c388..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_pmos_LG_load_biasn_cr4_2.sp +++ /dev/null @@ -1,75 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_cascode_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:07:21 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_cascode_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_cascode_pmos Vbiasn1 Vbiasn2 Vbiasp1 Vbiasp2 Vinn Vinp -+ Voutp -*.PININFO Vbiasp1:I Vbiasp2:I Vinn:I Vinp:I Vbiasn1:O Vbiasn2:O Voutp:O -MM4 net28 Vinn net12 net22 pmos_rvt w=WA l=LA nfin=nA -MM3 net29 Vinp net12 net22 pmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM6 net16 Vbiasp2 net25 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp Vbiasp2 net24 vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net25 net16 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net24 net16 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net29 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net28 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net16 Vbiasn2 net29 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp Vbiasn2 net28 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasn Vbiasn1 Vbiasn2 Biasp -*.PININFO Biasp:I Vbiasn1:O Vbiasn2:O -MM15 Vbiasn2 Vbiasn2 Vbiasn1 gnd! nmos_rvt w=WA l=LA nfin=nA -MM13 Vbiasn1 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM14 Vbiasn2 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR4_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM11 net023 net024 Vbiasn gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM8 net025 net010 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM9 net024 net024 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM7 net010 net010 net025 gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net025 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 net024 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net010 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn1 LG_Vbiasn2 LG_Vbiasp1 LG_Vbiasp2 Vinn Vinp single_ended_cascode_pmos -xiLG_load_biasn Biasp LG_Vbiasn1 LG_Vbiasn2 LG_load_biasn -xibCR4_2 Biasn Biasp CR4_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_pmos_LG_load_biasn_cr5_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_pmos_LG_load_biasn_cr5_2.sp deleted file mode 100644 index 8555583cfb..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_pmos_LG_load_biasn_cr5_2.sp +++ /dev/null @@ -1,72 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_cascode_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:07:21 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_cascode_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_cascode_pmos Vbiasn1 Vbiasn2 Vbiasp1 Vbiasp2 Vinn Vinp -+ Voutp -*.PININFO Vbiasp1:I Vbiasp2:I Vinn:I Vinp:I Vbiasn1:O Vbiasn2:O Voutp:O -MM4 net28 Vinn net12 net22 pmos_rvt w=WA l=LA nfin=nA -MM3 net29 Vinp net12 net22 pmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM6 net16 Vbiasp2 net25 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp Vbiasp2 net24 vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net25 net16 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net24 net16 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net29 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net28 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net16 Vbiasn2 net29 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp Vbiasn2 net28 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasn Vbiasn1 Vbiasn2 Biasp -*.PININFO Biasp:I Vbiasn1:O Vbiasn2:O -MM15 Vbiasn2 Vbiasn2 Vbiasn1 gnd! nmos_rvt w=WA l=LA nfin=nA -MM13 Vbiasn1 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM14 Vbiasn2 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR5_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM5 net014 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net014 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn1 LG_Vbiasn2 LG_Vbiasp1 LG_Vbiasp2 Vinn Vinp single_ended_cascode_pmos -xiLG_load_biasn Biasp LG_Vbiasn1 LG_Vbiasn2 LG_load_biasn -xibCR5_2 Biasn Biasp CR5_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_pmos_LG_load_biasn_cr6_3.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_pmos_LG_load_biasn_cr6_3.sp deleted file mode 100644 index 9103dbc5cf..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_cascode_pmos_LG_load_biasn_cr6_3.sp +++ /dev/null @@ -1,72 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_cascode_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:07:21 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_cascode_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_cascode_pmos Vbiasn1 Vbiasn2 Vbiasp1 Vbiasp2 Vinn Vinp -+ Voutp -*.PININFO Vbiasp1:I Vbiasp2:I Vinn:I Vinp:I Vbiasn1:O Vbiasn2:O Voutp:O -MM4 net28 Vinn net12 net22 pmos_rvt w=WA l=LA nfin=nA -MM3 net29 Vinp net12 net22 pmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM6 net16 Vbiasp2 net25 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp Vbiasp2 net24 vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net25 net16 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net24 net16 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net29 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net28 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net16 Vbiasn2 net29 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp Vbiasn2 net28 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasn Vbiasn1 Vbiasn2 Biasp -*.PININFO Biasp:I Vbiasn1:O Vbiasn2:O -MM15 Vbiasn2 Vbiasn2 Vbiasn1 gnd! nmos_rvt w=WA l=LA nfin=nA -MM13 Vbiasn1 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM14 Vbiasn2 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR6_3 Vbiasn1 Vbiasn2 Vbiasp -*.PININFO Vbiasn1:O Vbiasn2:O Vbiasp:O -MM2 Vbiasp Vbiasn2 Vbiasn1 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn2 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 Vbiasn1 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM5 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn2 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn1 LG_Vbiasn2 LG_Vbiasp1 LG_Vbiasp2 Vinn Vinp single_ended_cascode_pmos -xiLG_load_biasn Biasp LG_Vbiasn1 LG_Vbiasn2 LG_load_biasn -xibCR6_3 Biasn1 Biasn2 Biasp CR6_3 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_nmos_cr13_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_nmos_cr13_1.sp deleted file mode 100644 index 95adb31a9a..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_nmos_cr13_1.sp +++ /dev/null @@ -1,65 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:07:33 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM8 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutn net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net20 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net9 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net11 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos Biasp Vbiasn -*.PININFO Biasp:I Vbiasn:O -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_current_mirror -xiLG_nmos Biasp LG_Vbiasn LG_nmos -xibCR13_2 Biasn Biasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_nmos_cr13_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_nmos_cr13_2.sp deleted file mode 100644 index 95adb31a9a..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_nmos_cr13_2.sp +++ /dev/null @@ -1,65 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:07:33 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM8 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutn net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net20 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net9 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net11 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos Biasp Vbiasn -*.PININFO Biasp:I Vbiasn:O -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_current_mirror -xiLG_nmos Biasp LG_Vbiasn LG_nmos -xibCR13_2 Biasn Biasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_nmos_cr14_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_nmos_cr14_2.sp deleted file mode 100644 index 468e92dcc8..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_nmos_cr14_2.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:07:33 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM8 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutn net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net20 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net9 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net11 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos Biasp Vbiasn -*.PININFO Biasp:I Vbiasn:O -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR14_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net010 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 Vbiasn net010 res=rK -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_current_mirror -xiLG_nmos Biasp LG_Vbiasn LG_nmos -xibCR14_2 Biasn Biasp CR14_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_nmos_cr15_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_nmos_cr15_1.sp deleted file mode 100644 index cb8fe86e50..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_nmos_cr15_1.sp +++ /dev/null @@ -1,63 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:07:33 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM8 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutn net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net20 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net9 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net11 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos Biasp Vbiasn -*.PININFO Biasp:I Vbiasn:O -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR15_1 Vbiasp -*.PININFO Vbiasp:O -RR1 Vbiasp gnd! res=rK -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_current_mirror -xiLG_nmos Biasp LG_Vbiasn LG_nmos -xibCR15_1 Biasp CR15_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_nmos_cr16_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_nmos_cr16_1.sp deleted file mode 100644 index 9ba9e96da8..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_nmos_cr16_1.sp +++ /dev/null @@ -1,64 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:07:33 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM8 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutn net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net20 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net9 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net11 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos Biasp Vbiasn -*.PININFO Biasp:I Vbiasn:O -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR16_1 Vbiasp -*.PININFO Vbiasp:O -RR0 vdd! net6 res=rK -RR1 Vbiasp gnd! res=rK -MM2 Vbiasp Vbiasp net6 vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_current_mirror -xiLG_nmos Biasp LG_Vbiasn LG_nmos -xibCR16_1 Biasp CR16_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_nmos_cr2_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_nmos_cr2_2.sp deleted file mode 100644 index a8201ba070..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_nmos_cr2_2.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:07:33 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM8 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutn net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net20 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net9 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net11 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos Biasp Vbiasn -*.PININFO Biasp:I Vbiasn:O -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR2_2_wilson Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -RR0 Vbiasn gnd! res=rK -MM2 Vbiasp net12 Vbiasn gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_current_mirror -xiLG_nmos Biasp LG_Vbiasn LG_nmos -xibCR2_2_wilson Biasn Biasp CR2_2_wilson -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_nmos_cr3_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_nmos_cr3_2.sp deleted file mode 100644 index 0b60ac2082..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_nmos_cr3_2.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:07:33 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM8 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutn net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net20 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net9 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net11 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos Biasp Vbiasn -*.PININFO Biasp:I Vbiasn:O -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR3_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 net15 gnd! res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_current_mirror -xiLG_nmos Biasp LG_Vbiasn LG_nmos -xibCR3_2 Biasn Biasp CR3_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_nmos_cr4_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_nmos_cr4_2.sp deleted file mode 100644 index c1f0c1ff43..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_nmos_cr4_2.sp +++ /dev/null @@ -1,71 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:07:33 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM8 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutn net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net20 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net9 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net11 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos Biasp Vbiasn -*.PININFO Biasp:I Vbiasn:O -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR4_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM11 net023 net024 Vbiasn gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM8 net025 net010 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM9 net024 net024 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM7 net010 net010 net025 gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net025 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 net024 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net010 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_current_mirror -xiLG_nmos Biasp LG_Vbiasn LG_nmos -xibCR4_2 Biasn Biasp CR4_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_nmos_cr5_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_nmos_cr5_2.sp deleted file mode 100644 index 11302ea237..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_nmos_cr5_2.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:07:33 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM8 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutn net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net20 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net9 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net11 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos Biasp Vbiasn -*.PININFO Biasp:I Vbiasn:O -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR5_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM5 net014 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net014 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_current_mirror -xiLG_nmos Biasp LG_Vbiasn LG_nmos -xibCR5_2 Biasn Biasp CR5_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_nmos_cr6_3.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_nmos_cr6_3.sp deleted file mode 100644 index 188749ed68..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_nmos_cr6_3.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:07:33 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM8 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutn net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net20 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net9 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net11 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos Biasp Vbiasn -*.PININFO Biasp:I Vbiasn:O -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR6_3 Vbiasn1 Vbiasn2 Vbiasp -*.PININFO Vbiasn1:O Vbiasn2:O Vbiasp:O -MM2 Vbiasp Vbiasn2 Vbiasn1 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn2 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 Vbiasn1 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM5 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn2 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_current_mirror -xiLG_nmos Biasp LG_Vbiasn LG_nmos -xibCR6_3 Biasn1 Biasn2 Biasp CR6_3 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_nmos_l1_cr11_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_nmos_l1_cr11_1.sp deleted file mode 100644 index 2167684411..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_nmos_l1_cr11_1.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:07:33 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM8 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutn net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net20 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net9 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net11 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR11_1 Vbiasn -*.PININFO Vbiasn:O -RRF vdd! Vbiasn res=rK -MM1 net9 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net9 net9 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn net9 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_current_mirror -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR11_1 Biasn CR11_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_nmos_l1_cr12_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_nmos_l1_cr12_1.sp deleted file mode 100644 index a0b79ab4cd..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_nmos_l1_cr12_1.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:07:33 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM8 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutn net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net20 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net9 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net11 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR12_1 Vbiasn -*.PININFO Vbiasn:O -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 net10 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn net10 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RRF vdd! Vbiasn res=rK -RR0 vdd! net10 res=rK -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_current_mirror -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR12_1 Biasn CR12_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_nmos_l1_cr13_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_nmos_l1_cr13_1.sp deleted file mode 100644 index 02ec026f22..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_nmos_l1_cr13_1.sp +++ /dev/null @@ -1,67 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:07:33 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM8 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutn net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net20 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net9 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net11 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_current_mirror -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR13_2 Biasn Vbiasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_nmos_l1_cr13_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_nmos_l1_cr13_2.sp deleted file mode 100644 index 02ec026f22..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_nmos_l1_cr13_2.sp +++ /dev/null @@ -1,67 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:07:33 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM8 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutn net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net20 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net9 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net11 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_current_mirror -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR13_2 Biasn Vbiasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_nmos_l1_cr14_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_nmos_l1_cr14_2.sp deleted file mode 100644 index fbece06cda..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_nmos_l1_cr14_2.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:07:33 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM8 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutn net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net20 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net9 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net11 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR14_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net010 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 Vbiasn net010 res=rK -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_current_mirror -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR14_2 Biasn Vbiasp CR14_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_nmos_l1_cr1_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_nmos_l1_cr1_1.sp deleted file mode 100644 index 05d91cb3fe..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_nmos_l1_cr1_1.sp +++ /dev/null @@ -1,65 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:07:33 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM8 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutn net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net20 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net9 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net11 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR1_1 Vbiasn -*.PININFO Vbiasn:O -RRF vdd! Vbiasn res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_current_mirror -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR1_1 Biasn CR1_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_nmos_l1_cr2_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_nmos_l1_cr2_2.sp deleted file mode 100644 index af6597944a..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_nmos_l1_cr2_2.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:07:33 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM8 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutn net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net20 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net9 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net11 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR2_2_wilson Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -RR0 Vbiasn gnd! res=rK -MM2 Vbiasp net12 Vbiasn gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_current_mirror -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR2_2_wilson Biasn Vbiasp CR2_2_wilson -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_nmos_l1_cr3_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_nmos_l1_cr3_2.sp deleted file mode 100644 index 9d4c1b2415..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_nmos_l1_cr3_2.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:07:33 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM8 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutn net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net20 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net9 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net11 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR3_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 net15 gnd! res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_current_mirror -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR3_2 Biasn Vbiasp CR3_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_nmos_l1_cr4_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_nmos_l1_cr4_2.sp deleted file mode 100644 index 2c7d726e58..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_nmos_l1_cr4_2.sp +++ /dev/null @@ -1,73 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:07:33 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM8 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutn net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net20 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net9 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net11 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR4_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM11 net023 net024 Vbiasn gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM8 net025 net010 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM9 net024 net024 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM7 net010 net010 net025 gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net025 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 net024 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net010 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_current_mirror -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR4_2 Biasn Vbiasp CR4_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_nmos_l1_cr5_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_nmos_l1_cr5_2.sp deleted file mode 100644 index 6f2bccd77a..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_nmos_l1_cr5_2.sp +++ /dev/null @@ -1,70 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:07:33 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM8 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutn net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net20 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net9 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net11 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR5_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM5 net014 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net014 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_current_mirror -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR5_2 Biasn Vbiasp CR5_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_nmos_l1_cr7_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_nmos_l1_cr7_1.sp deleted file mode 100644 index 9f1cbdb6b6..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_nmos_l1_cr7_1.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:07:33 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM8 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutn net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net20 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net9 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net11 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR7_1 Vbiasn -*.PININFO Vbiasn:O -RR1 Vbiasn net7 res=rK -RR0 vdd! net7 res=rK -RRF vdd! Vbiasn res=rK -MM1 net7 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_current_mirror -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR7_1 Biasn CR7_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_nmos_l1_cr9_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_nmos_l1_cr9_1.sp deleted file mode 100644 index a2efa506e7..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_nmos_l1_cr9_1.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:07:33 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM8 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutn net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net20 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net9 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net11 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR9_1 Vbiasn -*.PININFO Vbiasn:O -RR1 net05 gnd! res=rK -RRF vdd! Vbiasn res=rK -MM0 Vbiasn Vbiasn net05 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_current_mirror -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR9_1 Biasn CR9_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_npmos_cr11_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_npmos_cr11_1.sp deleted file mode 100644 index 3a8cf8fe07..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_npmos_cr11_1.sp +++ /dev/null @@ -1,70 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:07:33 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM8 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutn net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net20 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net9 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net11 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR11_1 Vbiasn -*.PININFO Vbiasn:O -RRF vdd! Vbiasn res=rK -MM1 net9 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net9 net9 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn net9 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_current_mirror -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR11_1 Biasn CR11_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_npmos_cr12_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_npmos_cr12_1.sp deleted file mode 100644 index d775f4dbb5..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_npmos_cr12_1.sp +++ /dev/null @@ -1,70 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:07:33 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM8 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutn net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net20 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net9 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net11 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR12_1 Vbiasn -*.PININFO Vbiasn:O -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 net10 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn net10 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RRF vdd! Vbiasn res=rK -RR0 vdd! net10 res=rK -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_current_mirror -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR12_1 Biasn CR12_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_npmos_cr13_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_npmos_cr13_1.sp deleted file mode 100644 index d36119dab0..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_npmos_cr13_1.sp +++ /dev/null @@ -1,69 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:07:33 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM8 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutn net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net20 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net9 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net11 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_current_mirror -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR13_2 Biasn Vbiasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_npmos_cr13_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_npmos_cr13_2.sp deleted file mode 100644 index d36119dab0..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_npmos_cr13_2.sp +++ /dev/null @@ -1,69 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:07:33 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM8 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutn net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net20 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net9 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net11 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_current_mirror -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR13_2 Biasn Vbiasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_npmos_cr14_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_npmos_cr14_2.sp deleted file mode 100644 index 838844a9ce..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_npmos_cr14_2.sp +++ /dev/null @@ -1,70 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:07:33 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM8 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutn net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net20 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net9 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net11 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR14_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net010 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 Vbiasn net010 res=rK -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_current_mirror -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR14_2 Biasn Vbiasp CR14_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_npmos_cr1_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_npmos_cr1_1.sp deleted file mode 100644 index 34b14a2b5e..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_npmos_cr1_1.sp +++ /dev/null @@ -1,67 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:07:33 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM8 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutn net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net20 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net9 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net11 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR1_1 Vbiasn -*.PININFO Vbiasn:O -RRF vdd! Vbiasn res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_current_mirror -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR1_1 Biasn CR1_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_npmos_cr2_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_npmos_cr2_2.sp deleted file mode 100644 index ae2667a4a0..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_npmos_cr2_2.sp +++ /dev/null @@ -1,70 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:07:33 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM8 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutn net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net20 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net9 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net11 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR2_2_wilson Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -RR0 Vbiasn gnd! res=rK -MM2 Vbiasp net12 Vbiasn gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_current_mirror -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR2_2_wilson Biasn Vbiasp CR2_2_wilson -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_npmos_cr3_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_npmos_cr3_2.sp deleted file mode 100644 index 30b6ed8827..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_npmos_cr3_2.sp +++ /dev/null @@ -1,70 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:07:33 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM8 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutn net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net20 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net9 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net11 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR3_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 net15 gnd! res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_current_mirror -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR3_2 Biasn Vbiasp CR3_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_npmos_cr4_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_npmos_cr4_2.sp deleted file mode 100644 index ed76c9dbb6..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_npmos_cr4_2.sp +++ /dev/null @@ -1,75 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:07:33 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM8 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutn net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net20 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net9 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net11 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR4_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM11 net023 net024 Vbiasn gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM8 net025 net010 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM9 net024 net024 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM7 net010 net010 net025 gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net025 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 net024 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net010 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_current_mirror -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR4_2 Biasn Vbiasp CR4_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_npmos_cr5_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_npmos_cr5_2.sp deleted file mode 100644 index 56033f2efc..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_npmos_cr5_2.sp +++ /dev/null @@ -1,72 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:07:33 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM8 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutn net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net20 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net9 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net11 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR5_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM5 net014 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net014 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_current_mirror -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR5_2 Biasn Vbiasp CR5_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_npmos_cr7_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_npmos_cr7_1.sp deleted file mode 100644 index b4538e289e..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_npmos_cr7_1.sp +++ /dev/null @@ -1,70 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:07:33 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM8 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutn net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net20 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net9 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net11 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR7_1 Vbiasn -*.PININFO Vbiasn:O -RR1 Vbiasn net7 res=rK -RR0 vdd! net7 res=rK -RRF vdd! Vbiasn res=rK -MM1 net7 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_current_mirror -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR7_1 Biasn CR7_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_npmos_cr9_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_npmos_cr9_1.sp deleted file mode 100644 index c7e575ebf8..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_npmos_cr9_1.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:07:33 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM8 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutn net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net20 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net9 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net11 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR9_1 Vbiasn -*.PININFO Vbiasn:O -RR1 net05 gnd! res=rK -RRF vdd! Vbiasn res=rK -MM0 Vbiasn Vbiasn net05 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_current_mirror -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR9_1 Biasn CR9_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_pmos_l1_cr13_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_pmos_l1_cr13_1.sp deleted file mode 100644 index 424f9265e7..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_pmos_l1_cr13_1.sp +++ /dev/null @@ -1,67 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:07:33 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM8 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutn net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net20 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net9 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net11 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_current_mirror -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR13_2 Biasn Biasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_pmos_l1_cr13_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_pmos_l1_cr13_2.sp deleted file mode 100644 index 424f9265e7..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_pmos_l1_cr13_2.sp +++ /dev/null @@ -1,67 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:07:33 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM8 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutn net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net20 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net9 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net11 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_current_mirror -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR13_2 Biasn Biasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_pmos_l1_cr14_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_pmos_l1_cr14_2.sp deleted file mode 100644 index 88f722a9bc..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_pmos_l1_cr14_2.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:07:33 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM8 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutn net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net20 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net9 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net11 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR14_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net010 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 Vbiasn net010 res=rK -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_current_mirror -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR14_2 Biasn Biasp CR14_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_pmos_l1_cr15_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_pmos_l1_cr15_1.sp deleted file mode 100644 index e25437c00a..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_pmos_l1_cr15_1.sp +++ /dev/null @@ -1,65 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:07:33 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM8 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutn net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net20 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net9 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net11 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR15_1 Vbiasp -*.PININFO Vbiasp:O -RR1 Vbiasp gnd! res=rK -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_current_mirror -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR15_1 Biasp CR15_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_pmos_l1_cr16_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_pmos_l1_cr16_1.sp deleted file mode 100644 index a061bad118..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_pmos_l1_cr16_1.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:07:33 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM8 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutn net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net20 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net9 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net11 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR16_1 Vbiasp -*.PININFO Vbiasp:O -RR0 vdd! net6 res=rK -RR1 Vbiasp gnd! res=rK -MM2 Vbiasp Vbiasp net6 vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_current_mirror -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR16_1 Biasp CR16_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_pmos_l1_cr2_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_pmos_l1_cr2_2.sp deleted file mode 100644 index 50d1b3f8f4..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_pmos_l1_cr2_2.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:07:33 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM8 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutn net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net20 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net9 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net11 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR2_2_wilson Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -RR0 Vbiasn gnd! res=rK -MM2 Vbiasp net12 Vbiasn gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_current_mirror -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR2_2_wilson Biasn Biasp CR2_2_wilson -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_pmos_l1_cr3_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_pmos_l1_cr3_2.sp deleted file mode 100644 index a4031a5850..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_pmos_l1_cr3_2.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:07:33 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM8 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutn net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net20 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net9 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net11 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR3_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 net15 gnd! res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_current_mirror -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR3_2 Biasn Biasp CR3_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_pmos_l1_cr4_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_pmos_l1_cr4_2.sp deleted file mode 100644 index 793acf08a9..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_pmos_l1_cr4_2.sp +++ /dev/null @@ -1,73 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:07:33 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM8 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutn net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net20 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net9 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net11 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR4_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM11 net023 net024 Vbiasn gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM8 net025 net010 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM9 net024 net024 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM7 net010 net010 net025 gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net025 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 net024 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net010 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_current_mirror -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR4_2 Biasn Biasp CR4_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_pmos_l1_cr5_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_pmos_l1_cr5_2.sp deleted file mode 100644 index 588fe02b86..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_pmos_l1_cr5_2.sp +++ /dev/null @@ -1,70 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:07:33 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM8 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutn net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net20 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net9 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net11 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR5_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM5 net014 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net014 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_current_mirror -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR5_2 Biasn Biasp CR5_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_pmos_l1_cr6_3.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_pmos_l1_cr6_3.sp deleted file mode 100644 index 81a2516dfe..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_pmos_l1_cr6_3.sp +++ /dev/null @@ -1,70 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:07:33 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM8 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutn net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net20 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net9 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net11 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR6_3 Vbiasn1 Vbiasn2 Vbiasp -*.PININFO Vbiasn1:O Vbiasn2:O Vbiasp:O -MM2 Vbiasp Vbiasn2 Vbiasn1 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn2 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 Vbiasn1 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM5 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn2 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_current_mirror -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR6_3 Biasn1 Biasn2 Biasp CR6_3 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_pnmos_4_cr13_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_pnmos_4_cr13_1.sp deleted file mode 100644 index 57b2cbdc6f..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_pnmos_4_cr13_1.sp +++ /dev/null @@ -1,69 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:07:33 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM8 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutn net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net20 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net9 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net11 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_current_mirror -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR13_2 Biasn Biasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_pnmos_4_cr13_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_pnmos_4_cr13_2.sp deleted file mode 100644 index 57b2cbdc6f..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_pnmos_4_cr13_2.sp +++ /dev/null @@ -1,69 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:07:33 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM8 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutn net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net20 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net9 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net11 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_current_mirror -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR13_2 Biasn Biasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_pnmos_4_cr14_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_pnmos_4_cr14_2.sp deleted file mode 100644 index db159c45e8..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_pnmos_4_cr14_2.sp +++ /dev/null @@ -1,70 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:07:33 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM8 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutn net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net20 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net9 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net11 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR14_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net010 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 Vbiasn net010 res=rK -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_current_mirror -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR14_2 Biasn Biasp CR14_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_pnmos_4_cr15_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_pnmos_4_cr15_1.sp deleted file mode 100644 index 530631b9bb..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_pnmos_4_cr15_1.sp +++ /dev/null @@ -1,67 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:07:33 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM8 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutn net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net20 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net9 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net11 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR15_1 Vbiasp -*.PININFO Vbiasp:O -RR1 Vbiasp gnd! res=rK -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_current_mirror -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR15_1 Biasp CR15_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_pnmos_4_cr16_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_pnmos_4_cr16_1.sp deleted file mode 100644 index 9fb13cb508..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_pnmos_4_cr16_1.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:07:33 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM8 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutn net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net20 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net9 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net11 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR16_1 Vbiasp -*.PININFO Vbiasp:O -RR0 vdd! net6 res=rK -RR1 Vbiasp gnd! res=rK -MM2 Vbiasp Vbiasp net6 vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_current_mirror -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR16_1 Biasp CR16_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_pnmos_4_cr2_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_pnmos_4_cr2_2.sp deleted file mode 100644 index 12dd4d874c..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_pnmos_4_cr2_2.sp +++ /dev/null @@ -1,70 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:07:33 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM8 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutn net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net20 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net9 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net11 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR2_2_wilson Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -RR0 Vbiasn gnd! res=rK -MM2 Vbiasp net12 Vbiasn gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_current_mirror -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR2_2_wilson Biasn Biasp CR2_2_wilson -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_pnmos_4_cr3_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_pnmos_4_cr3_2.sp deleted file mode 100644 index a61855ca32..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_pnmos_4_cr3_2.sp +++ /dev/null @@ -1,70 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:07:33 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM8 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutn net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net20 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net9 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net11 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR3_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 net15 gnd! res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_current_mirror -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR3_2 Biasn Biasp CR3_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_pnmos_4_cr4_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_pnmos_4_cr4_2.sp deleted file mode 100644 index a1389ece91..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_pnmos_4_cr4_2.sp +++ /dev/null @@ -1,75 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:07:33 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM8 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutn net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net20 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net9 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net11 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR4_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM11 net023 net024 Vbiasn gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM8 net025 net010 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM9 net024 net024 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM7 net010 net010 net025 gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net025 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 net024 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net010 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_current_mirror -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR4_2 Biasn Biasp CR4_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_pnmos_4_cr5_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_pnmos_4_cr5_2.sp deleted file mode 100644 index 7c9a2acc54..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_pnmos_4_cr5_2.sp +++ /dev/null @@ -1,72 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:07:33 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM8 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutn net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net20 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net9 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net11 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR5_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM5 net014 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net014 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_current_mirror -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR5_2 Biasn Biasp CR5_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_pnmos_4_cr6_3.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_pnmos_4_cr6_3.sp deleted file mode 100644 index a7de6afdb2..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_pnmos_4_cr6_3.sp +++ /dev/null @@ -1,72 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:07:33 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM8 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutn net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net20 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net9 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net11 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR6_3 Vbiasn1 Vbiasn2 Vbiasp -*.PININFO Vbiasn1:O Vbiasn2:O Vbiasp:O -MM2 Vbiasp Vbiasn2 Vbiasn1 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn2 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 Vbiasn1 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM5 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn2 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_current_mirror -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR6_3 Biasn1 Biasn2 Biasp CR6_3 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_pnmos_cr13_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_pnmos_cr13_1.sp deleted file mode 100644 index 26cea8fa81..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_pnmos_cr13_1.sp +++ /dev/null @@ -1,69 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:07:33 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM8 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutn net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net20 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net9 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net11 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_current_mirror -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR13_2 Biasn Biasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_pnmos_cr13_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_pnmos_cr13_2.sp deleted file mode 100644 index 26cea8fa81..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_pnmos_cr13_2.sp +++ /dev/null @@ -1,69 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:07:33 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM8 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutn net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net20 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net9 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net11 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_current_mirror -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR13_2 Biasn Biasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_pnmos_cr14_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_pnmos_cr14_2.sp deleted file mode 100644 index 4969307054..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_pnmos_cr14_2.sp +++ /dev/null @@ -1,70 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:07:33 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM8 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutn net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net20 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net9 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net11 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR14_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net010 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 Vbiasn net010 res=rK -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_current_mirror -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR14_2 Biasn Biasp CR14_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_pnmos_cr15_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_pnmos_cr15_1.sp deleted file mode 100644 index 432eada33b..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_pnmos_cr15_1.sp +++ /dev/null @@ -1,67 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:07:33 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM8 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutn net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net20 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net9 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net11 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR15_1 Vbiasp -*.PININFO Vbiasp:O -RR1 Vbiasp gnd! res=rK -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_current_mirror -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR15_1 Biasp CR15_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_pnmos_cr16_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_pnmos_cr16_1.sp deleted file mode 100644 index 456f5b2eb2..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_pnmos_cr16_1.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:07:33 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM8 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutn net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net20 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net9 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net11 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR16_1 Vbiasp -*.PININFO Vbiasp:O -RR0 vdd! net6 res=rK -RR1 Vbiasp gnd! res=rK -MM2 Vbiasp Vbiasp net6 vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_current_mirror -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR16_1 Biasp CR16_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_pnmos_cr2_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_pnmos_cr2_2.sp deleted file mode 100644 index 8c8bf321b4..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_pnmos_cr2_2.sp +++ /dev/null @@ -1,70 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:07:33 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM8 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutn net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net20 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net9 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net11 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR2_2_wilson Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -RR0 Vbiasn gnd! res=rK -MM2 Vbiasp net12 Vbiasn gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_current_mirror -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR2_2_wilson Biasn Biasp CR2_2_wilson -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_pnmos_cr3_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_pnmos_cr3_2.sp deleted file mode 100644 index 009ed6e5db..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_pnmos_cr3_2.sp +++ /dev/null @@ -1,70 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:07:33 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM8 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutn net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net20 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net9 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net11 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR3_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 net15 gnd! res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_current_mirror -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR3_2 Biasn Biasp CR3_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_pnmos_cr4_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_pnmos_cr4_2.sp deleted file mode 100644 index 696953cddc..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_pnmos_cr4_2.sp +++ /dev/null @@ -1,75 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:07:33 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM8 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutn net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net20 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net9 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net11 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR4_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM11 net023 net024 Vbiasn gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM8 net025 net010 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM9 net024 net024 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM7 net010 net010 net025 gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net025 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 net024 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net010 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_current_mirror -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR4_2 Biasn Biasp CR4_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_pnmos_cr5_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_pnmos_cr5_2.sp deleted file mode 100644 index caa0306d80..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_pnmos_cr5_2.sp +++ /dev/null @@ -1,72 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:07:33 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM8 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutn net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net20 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net9 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net11 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR5_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM5 net014 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net014 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_current_mirror -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR5_2 Biasn Biasp CR5_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_pnmos_cr6_3.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_pnmos_cr6_3.sp deleted file mode 100644 index 348eab5d78..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_LG_pnmos_cr6_3.sp +++ /dev/null @@ -1,72 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:07:33 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM8 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutn net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net20 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net9 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net11 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR6_3 Vbiasn1 Vbiasn2 Vbiasp -*.PININFO Vbiasn1:O Vbiasn2:O Vbiasp:O -MM2 Vbiasp Vbiasn2 Vbiasn1 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn2 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 Vbiasn1 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM5 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn2 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_current_mirror -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR6_3 Biasn1 Biasn2 Biasp CR6_3 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_nmos_l1_cr11_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_nmos_l1_cr11_1.sp deleted file mode 100644 index d432bed26d..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_nmos_l1_cr11_1.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:07:49 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM3 Voutp net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net17 net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 Vinn net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vinp net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM5 net13 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net17 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR11_1 Vbiasn -*.PININFO Vbiasn:O -RRF vdd! Vbiasn res=rK -MM1 net9 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net9 net9 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn net9 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_current_mirror_pmos -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR11_1 Biasn CR11_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_nmos_l1_cr12_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_nmos_l1_cr12_1.sp deleted file mode 100644 index eec137c7d1..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_nmos_l1_cr12_1.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:07:49 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM3 Voutp net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net17 net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 Vinn net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vinp net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM5 net13 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net17 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR12_1 Vbiasn -*.PININFO Vbiasn:O -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 net10 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn net10 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RRF vdd! Vbiasn res=rK -RR0 vdd! net10 res=rK -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_current_mirror_pmos -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR12_1 Biasn CR12_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_nmos_l1_cr13_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_nmos_l1_cr13_1.sp deleted file mode 100644 index 71c14ce883..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_nmos_l1_cr13_1.sp +++ /dev/null @@ -1,67 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:07:49 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM3 Voutp net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net17 net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 Vinn net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vinp net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM5 net13 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net17 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_current_mirror_pmos -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR13_2 Biasn Vbiasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_nmos_l1_cr13_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_nmos_l1_cr13_2.sp deleted file mode 100644 index 71c14ce883..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_nmos_l1_cr13_2.sp +++ /dev/null @@ -1,67 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:07:49 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM3 Voutp net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net17 net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 Vinn net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vinp net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM5 net13 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net17 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_current_mirror_pmos -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR13_2 Biasn Vbiasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_nmos_l1_cr14_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_nmos_l1_cr14_2.sp deleted file mode 100644 index 0214644c1a..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_nmos_l1_cr14_2.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:07:49 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM3 Voutp net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net17 net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 Vinn net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vinp net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM5 net13 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net17 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR14_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net010 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 Vbiasn net010 res=rK -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_current_mirror_pmos -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR14_2 Biasn Vbiasp CR14_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_nmos_l1_cr1_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_nmos_l1_cr1_1.sp deleted file mode 100644 index 4cc355bad6..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_nmos_l1_cr1_1.sp +++ /dev/null @@ -1,65 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:07:49 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM3 Voutp net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net17 net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 Vinn net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vinp net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM5 net13 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net17 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR1_1 Vbiasn -*.PININFO Vbiasn:O -RRF vdd! Vbiasn res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_current_mirror_pmos -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR1_1 Biasn CR1_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_nmos_l1_cr2_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_nmos_l1_cr2_2.sp deleted file mode 100644 index 6150c3d500..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_nmos_l1_cr2_2.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:07:49 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM3 Voutp net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net17 net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 Vinn net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vinp net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM5 net13 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net17 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR2_2_wilson Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -RR0 Vbiasn gnd! res=rK -MM2 Vbiasp net12 Vbiasn gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_current_mirror_pmos -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR2_2_wilson Biasn Vbiasp CR2_2_wilson -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_nmos_l1_cr3_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_nmos_l1_cr3_2.sp deleted file mode 100644 index bcd41a614b..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_nmos_l1_cr3_2.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:07:49 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM3 Voutp net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net17 net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 Vinn net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vinp net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM5 net13 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net17 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR3_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 net15 gnd! res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_current_mirror_pmos -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR3_2 Biasn Vbiasp CR3_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_nmos_l1_cr4_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_nmos_l1_cr4_2.sp deleted file mode 100644 index e1f203a3bb..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_nmos_l1_cr4_2.sp +++ /dev/null @@ -1,73 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:07:49 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM3 Voutp net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net17 net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 Vinn net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vinp net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM5 net13 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net17 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR4_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM11 net023 net024 Vbiasn gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM8 net025 net010 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM9 net024 net024 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM7 net010 net010 net025 gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net025 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 net024 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net010 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_current_mirror_pmos -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR4_2 Biasn Vbiasp CR4_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_nmos_l1_cr5_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_nmos_l1_cr5_2.sp deleted file mode 100644 index adf911b1b7..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_nmos_l1_cr5_2.sp +++ /dev/null @@ -1,70 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:07:49 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM3 Voutp net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net17 net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 Vinn net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vinp net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM5 net13 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net17 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR5_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM5 net014 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net014 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_current_mirror_pmos -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR5_2 Biasn Vbiasp CR5_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_nmos_l1_cr7_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_nmos_l1_cr7_1.sp deleted file mode 100644 index 6eb1b66998..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_nmos_l1_cr7_1.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:07:49 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM3 Voutp net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net17 net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 Vinn net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vinp net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM5 net13 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net17 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR7_1 Vbiasn -*.PININFO Vbiasn:O -RR1 Vbiasn net7 res=rK -RR0 vdd! net7 res=rK -RRF vdd! Vbiasn res=rK -MM1 net7 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_current_mirror_pmos -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR7_1 Biasn CR7_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_nmos_l1_cr9_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_nmos_l1_cr9_1.sp deleted file mode 100644 index 365236dd8e..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_nmos_l1_cr9_1.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:07:49 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM3 Voutp net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net17 net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 Vinn net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vinp net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM5 net13 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net17 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR9_1 Vbiasn -*.PININFO Vbiasn:O -RR1 net05 gnd! res=rK -RRF vdd! Vbiasn res=rK -MM0 Vbiasn Vbiasn net05 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_current_mirror_pmos -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR9_1 Biasn CR9_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_npmos_cr11_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_npmos_cr11_1.sp deleted file mode 100644 index bc0e46c22a..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_npmos_cr11_1.sp +++ /dev/null @@ -1,70 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:07:49 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM3 Voutp net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net17 net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 Vinn net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vinp net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM5 net13 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net17 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR11_1 Vbiasn -*.PININFO Vbiasn:O -RRF vdd! Vbiasn res=rK -MM1 net9 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net9 net9 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn net9 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_current_mirror_pmos -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR11_1 Biasn CR11_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_npmos_cr12_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_npmos_cr12_1.sp deleted file mode 100644 index 875ba2ed86..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_npmos_cr12_1.sp +++ /dev/null @@ -1,70 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:07:49 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM3 Voutp net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net17 net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 Vinn net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vinp net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM5 net13 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net17 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR12_1 Vbiasn -*.PININFO Vbiasn:O -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 net10 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn net10 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RRF vdd! Vbiasn res=rK -RR0 vdd! net10 res=rK -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_current_mirror_pmos -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR12_1 Biasn CR12_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_npmos_cr13_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_npmos_cr13_1.sp deleted file mode 100644 index b3a6b10213..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_npmos_cr13_1.sp +++ /dev/null @@ -1,69 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:07:49 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM3 Voutp net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net17 net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 Vinn net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vinp net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM5 net13 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net17 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_current_mirror_pmos -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR13_2 Biasn Vbiasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_npmos_cr13_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_npmos_cr13_2.sp deleted file mode 100644 index b3a6b10213..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_npmos_cr13_2.sp +++ /dev/null @@ -1,69 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:07:49 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM3 Voutp net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net17 net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 Vinn net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vinp net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM5 net13 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net17 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_current_mirror_pmos -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR13_2 Biasn Vbiasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_npmos_cr14_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_npmos_cr14_2.sp deleted file mode 100644 index d7f60f7fd1..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_npmos_cr14_2.sp +++ /dev/null @@ -1,70 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:07:49 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM3 Voutp net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net17 net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 Vinn net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vinp net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM5 net13 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net17 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR14_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net010 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 Vbiasn net010 res=rK -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_current_mirror_pmos -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR14_2 Biasn Vbiasp CR14_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_npmos_cr1_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_npmos_cr1_1.sp deleted file mode 100644 index 1765236053..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_npmos_cr1_1.sp +++ /dev/null @@ -1,67 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:07:49 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM3 Voutp net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net17 net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 Vinn net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vinp net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM5 net13 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net17 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR1_1 Vbiasn -*.PININFO Vbiasn:O -RRF vdd! Vbiasn res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_current_mirror_pmos -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR1_1 Biasn CR1_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_npmos_cr2_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_npmos_cr2_2.sp deleted file mode 100644 index 55f5dc6e71..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_npmos_cr2_2.sp +++ /dev/null @@ -1,70 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:07:49 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM3 Voutp net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net17 net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 Vinn net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vinp net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM5 net13 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net17 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR2_2_wilson Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -RR0 Vbiasn gnd! res=rK -MM2 Vbiasp net12 Vbiasn gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_current_mirror_pmos -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR2_2_wilson Biasn Vbiasp CR2_2_wilson -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_npmos_cr3_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_npmos_cr3_2.sp deleted file mode 100644 index ab335bd560..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_npmos_cr3_2.sp +++ /dev/null @@ -1,70 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:07:49 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM3 Voutp net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net17 net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 Vinn net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vinp net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM5 net13 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net17 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR3_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 net15 gnd! res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_current_mirror_pmos -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR3_2 Biasn Vbiasp CR3_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_npmos_cr4_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_npmos_cr4_2.sp deleted file mode 100644 index 42a1dc6b71..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_npmos_cr4_2.sp +++ /dev/null @@ -1,75 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:07:49 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM3 Voutp net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net17 net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 Vinn net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vinp net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM5 net13 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net17 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR4_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM11 net023 net024 Vbiasn gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM8 net025 net010 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM9 net024 net024 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM7 net010 net010 net025 gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net025 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 net024 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net010 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_current_mirror_pmos -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR4_2 Biasn Vbiasp CR4_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_npmos_cr5_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_npmos_cr5_2.sp deleted file mode 100644 index 00528e5d17..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_npmos_cr5_2.sp +++ /dev/null @@ -1,72 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:07:49 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM3 Voutp net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net17 net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 Vinn net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vinp net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM5 net13 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net17 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR5_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM5 net014 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net014 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_current_mirror_pmos -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR5_2 Biasn Vbiasp CR5_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_npmos_cr7_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_npmos_cr7_1.sp deleted file mode 100644 index e5f6217a8b..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_npmos_cr7_1.sp +++ /dev/null @@ -1,70 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:07:49 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM3 Voutp net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net17 net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 Vinn net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vinp net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM5 net13 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net17 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR7_1 Vbiasn -*.PININFO Vbiasn:O -RR1 Vbiasn net7 res=rK -RR0 vdd! net7 res=rK -RRF vdd! Vbiasn res=rK -MM1 net7 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_current_mirror_pmos -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR7_1 Biasn CR7_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_npmos_cr9_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_npmos_cr9_1.sp deleted file mode 100644 index c68262972d..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_npmos_cr9_1.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:07:49 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM3 Voutp net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net17 net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 Vinn net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vinp net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM5 net13 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net17 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR9_1 Vbiasn -*.PININFO Vbiasn:O -RR1 net05 gnd! res=rK -RRF vdd! Vbiasn res=rK -MM0 Vbiasn Vbiasn net05 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_current_mirror_pmos -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR9_1 Biasn CR9_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pmos_cr11_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pmos_cr11_1.sp deleted file mode 100644 index 87ff8dddb7..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pmos_cr11_1.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:07:49 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM3 Voutp net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net17 net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 Vinn net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vinp net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM5 net13 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net17 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos Biasn Vbiasp -*.PININFO Biasn:I Vbiasp:O -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR11_1 Vbiasn -*.PININFO Vbiasn:O -RRF vdd! Vbiasn res=rK -MM1 net9 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net9 net9 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn net9 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_current_mirror_pmos -xiLG_pmos Biasn LG_Vbiasp LG_pmos -xibCR11_1 Biasn CR11_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pmos_cr12_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pmos_cr12_1.sp deleted file mode 100644 index 23ab6ef542..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pmos_cr12_1.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:07:49 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM3 Voutp net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net17 net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 Vinn net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vinp net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM5 net13 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net17 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos Biasn Vbiasp -*.PININFO Biasn:I Vbiasp:O -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR12_1 Vbiasn -*.PININFO Vbiasn:O -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 net10 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn net10 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RRF vdd! Vbiasn res=rK -RR0 vdd! net10 res=rK -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_current_mirror_pmos -xiLG_pmos Biasn LG_Vbiasp LG_pmos -xibCR12_1 Biasn CR12_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pmos_cr13_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pmos_cr13_1.sp deleted file mode 100644 index 471bac4a4f..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pmos_cr13_1.sp +++ /dev/null @@ -1,65 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:07:49 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM3 Voutp net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net17 net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 Vinn net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vinp net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM5 net13 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net17 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos Biasn Vbiasp -*.PININFO Biasn:I Vbiasp:O -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_current_mirror_pmos -xiLG_pmos Biasn LG_Vbiasp LG_pmos -xibCR13_2 Biasn Vbiasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pmos_cr13_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pmos_cr13_2.sp deleted file mode 100644 index 471bac4a4f..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pmos_cr13_2.sp +++ /dev/null @@ -1,65 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:07:49 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM3 Voutp net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net17 net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 Vinn net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vinp net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM5 net13 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net17 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos Biasn Vbiasp -*.PININFO Biasn:I Vbiasp:O -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_current_mirror_pmos -xiLG_pmos Biasn LG_Vbiasp LG_pmos -xibCR13_2 Biasn Vbiasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pmos_cr14_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pmos_cr14_2.sp deleted file mode 100644 index 0d8bd261b2..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pmos_cr14_2.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:07:49 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM3 Voutp net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net17 net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 Vinn net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vinp net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM5 net13 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net17 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos Biasn Vbiasp -*.PININFO Biasn:I Vbiasp:O -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR14_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net010 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 Vbiasn net010 res=rK -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_current_mirror_pmos -xiLG_pmos Biasn LG_Vbiasp LG_pmos -xibCR14_2 Biasn Vbiasp CR14_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pmos_cr1_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pmos_cr1_1.sp deleted file mode 100644 index 86fd838135..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pmos_cr1_1.sp +++ /dev/null @@ -1,63 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:07:49 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM3 Voutp net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net17 net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 Vinn net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vinp net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM5 net13 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net17 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos Biasn Vbiasp -*.PININFO Biasn:I Vbiasp:O -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR1_1 Vbiasn -*.PININFO Vbiasn:O -RRF vdd! Vbiasn res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_current_mirror_pmos -xiLG_pmos Biasn LG_Vbiasp LG_pmos -xibCR1_1 Biasn CR1_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pmos_cr2_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pmos_cr2_2.sp deleted file mode 100644 index 3a021c5301..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pmos_cr2_2.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:07:49 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM3 Voutp net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net17 net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 Vinn net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vinp net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM5 net13 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net17 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos Biasn Vbiasp -*.PININFO Biasn:I Vbiasp:O -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR2_2_wilson Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -RR0 Vbiasn gnd! res=rK -MM2 Vbiasp net12 Vbiasn gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_current_mirror_pmos -xiLG_pmos Biasn LG_Vbiasp LG_pmos -xibCR2_2_wilson Biasn Vbiasp CR2_2_wilson -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pmos_cr3_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pmos_cr3_2.sp deleted file mode 100644 index 30606790cf..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pmos_cr3_2.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:07:49 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM3 Voutp net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net17 net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 Vinn net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vinp net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM5 net13 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net17 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos Biasn Vbiasp -*.PININFO Biasn:I Vbiasp:O -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR3_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 net15 gnd! res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_current_mirror_pmos -xiLG_pmos Biasn LG_Vbiasp LG_pmos -xibCR3_2 Biasn Vbiasp CR3_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pmos_cr4_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pmos_cr4_2.sp deleted file mode 100644 index 92c443fd99..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pmos_cr4_2.sp +++ /dev/null @@ -1,71 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:07:49 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM3 Voutp net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net17 net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 Vinn net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vinp net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM5 net13 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net17 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos Biasn Vbiasp -*.PININFO Biasn:I Vbiasp:O -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR4_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM11 net023 net024 Vbiasn gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM8 net025 net010 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM9 net024 net024 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM7 net010 net010 net025 gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net025 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 net024 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net010 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_current_mirror_pmos -xiLG_pmos Biasn LG_Vbiasp LG_pmos -xibCR4_2 Biasn Vbiasp CR4_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pmos_cr5_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pmos_cr5_2.sp deleted file mode 100644 index e920d75c10..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pmos_cr5_2.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:07:49 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM3 Voutp net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net17 net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 Vinn net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vinp net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM5 net13 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net17 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos Biasn Vbiasp -*.PININFO Biasn:I Vbiasp:O -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR5_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM5 net014 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net014 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_current_mirror_pmos -xiLG_pmos Biasn LG_Vbiasp LG_pmos -xibCR5_2 Biasn Vbiasp CR5_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pmos_cr7_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pmos_cr7_1.sp deleted file mode 100644 index b5e55ed518..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pmos_cr7_1.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:07:49 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM3 Voutp net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net17 net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 Vinn net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vinp net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM5 net13 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net17 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos Biasn Vbiasp -*.PININFO Biasn:I Vbiasp:O -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR7_1 Vbiasn -*.PININFO Vbiasn:O -RR1 Vbiasn net7 res=rK -RR0 vdd! net7 res=rK -RRF vdd! Vbiasn res=rK -MM1 net7 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_current_mirror_pmos -xiLG_pmos Biasn LG_Vbiasp LG_pmos -xibCR7_1 Biasn CR7_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pmos_cr9_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pmos_cr9_1.sp deleted file mode 100644 index e96e63e261..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pmos_cr9_1.sp +++ /dev/null @@ -1,64 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:07:49 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM3 Voutp net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net17 net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 Vinn net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vinp net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM5 net13 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net17 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos Biasn Vbiasp -*.PININFO Biasn:I Vbiasp:O -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR9_1 Vbiasn -*.PININFO Vbiasn:O -RR1 net05 gnd! res=rK -RRF vdd! Vbiasn res=rK -MM0 Vbiasn Vbiasn net05 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_current_mirror_pmos -xiLG_pmos Biasn LG_Vbiasp LG_pmos -xibCR9_1 Biasn CR9_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pmos_l1_cr13_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pmos_l1_cr13_1.sp deleted file mode 100644 index afb872e5b7..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pmos_l1_cr13_1.sp +++ /dev/null @@ -1,67 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:07:49 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM3 Voutp net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net17 net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 Vinn net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vinp net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM5 net13 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net17 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_current_mirror_pmos -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR13_2 Biasn Biasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pmos_l1_cr13_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pmos_l1_cr13_2.sp deleted file mode 100644 index afb872e5b7..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pmos_l1_cr13_2.sp +++ /dev/null @@ -1,67 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:07:49 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM3 Voutp net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net17 net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 Vinn net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vinp net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM5 net13 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net17 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_current_mirror_pmos -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR13_2 Biasn Biasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pmos_l1_cr14_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pmos_l1_cr14_2.sp deleted file mode 100644 index cc71d4d139..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pmos_l1_cr14_2.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:07:49 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM3 Voutp net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net17 net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 Vinn net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vinp net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM5 net13 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net17 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR14_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net010 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 Vbiasn net010 res=rK -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_current_mirror_pmos -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR14_2 Biasn Biasp CR14_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pmos_l1_cr15_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pmos_l1_cr15_1.sp deleted file mode 100644 index 5a71fd89d7..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pmos_l1_cr15_1.sp +++ /dev/null @@ -1,65 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:07:49 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM3 Voutp net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net17 net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 Vinn net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vinp net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM5 net13 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net17 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR15_1 Vbiasp -*.PININFO Vbiasp:O -RR1 Vbiasp gnd! res=rK -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_current_mirror_pmos -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR15_1 Biasp CR15_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pmos_l1_cr16_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pmos_l1_cr16_1.sp deleted file mode 100644 index 3fbb2d0fb0..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pmos_l1_cr16_1.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:07:49 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM3 Voutp net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net17 net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 Vinn net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vinp net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM5 net13 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net17 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR16_1 Vbiasp -*.PININFO Vbiasp:O -RR0 vdd! net6 res=rK -RR1 Vbiasp gnd! res=rK -MM2 Vbiasp Vbiasp net6 vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_current_mirror_pmos -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR16_1 Biasp CR16_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pmos_l1_cr2_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pmos_l1_cr2_2.sp deleted file mode 100644 index ea0b1ff4ac..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pmos_l1_cr2_2.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:07:49 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM3 Voutp net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net17 net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 Vinn net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vinp net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM5 net13 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net17 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR2_2_wilson Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -RR0 Vbiasn gnd! res=rK -MM2 Vbiasp net12 Vbiasn gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_current_mirror_pmos -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR2_2_wilson Biasn Biasp CR2_2_wilson -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pmos_l1_cr3_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pmos_l1_cr3_2.sp deleted file mode 100644 index a15f1ca549..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pmos_l1_cr3_2.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:07:49 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM3 Voutp net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net17 net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 Vinn net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vinp net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM5 net13 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net17 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR3_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 net15 gnd! res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_current_mirror_pmos -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR3_2 Biasn Biasp CR3_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pmos_l1_cr4_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pmos_l1_cr4_2.sp deleted file mode 100644 index db84d31f10..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pmos_l1_cr4_2.sp +++ /dev/null @@ -1,73 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:07:49 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM3 Voutp net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net17 net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 Vinn net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vinp net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM5 net13 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net17 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR4_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM11 net023 net024 Vbiasn gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM8 net025 net010 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM9 net024 net024 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM7 net010 net010 net025 gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net025 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 net024 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net010 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_current_mirror_pmos -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR4_2 Biasn Biasp CR4_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pmos_l1_cr5_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pmos_l1_cr5_2.sp deleted file mode 100644 index af5595a4ae..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pmos_l1_cr5_2.sp +++ /dev/null @@ -1,70 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:07:49 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM3 Voutp net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net17 net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 Vinn net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vinp net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM5 net13 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net17 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR5_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM5 net014 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net014 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_current_mirror_pmos -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR5_2 Biasn Biasp CR5_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pmos_l1_cr6_3.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pmos_l1_cr6_3.sp deleted file mode 100644 index f4e5802570..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pmos_l1_cr6_3.sp +++ /dev/null @@ -1,70 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:07:49 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM3 Voutp net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net17 net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 Vinn net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vinp net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM5 net13 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net17 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR6_3 Vbiasn1 Vbiasn2 Vbiasp -*.PININFO Vbiasn1:O Vbiasn2:O Vbiasp:O -MM2 Vbiasp Vbiasn2 Vbiasn1 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn2 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 Vbiasn1 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM5 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn2 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_current_mirror_pmos -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR6_3 Biasn1 Biasn2 Biasp CR6_3 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pnmos_4_cr13_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pnmos_4_cr13_1.sp deleted file mode 100644 index eb7562d37a..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pnmos_4_cr13_1.sp +++ /dev/null @@ -1,69 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:07:49 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM3 Voutp net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net17 net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 Vinn net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vinp net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM5 net13 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net17 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_current_mirror_pmos -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR13_2 Biasn Biasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pnmos_4_cr13_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pnmos_4_cr13_2.sp deleted file mode 100644 index eb7562d37a..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pnmos_4_cr13_2.sp +++ /dev/null @@ -1,69 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:07:49 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM3 Voutp net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net17 net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 Vinn net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vinp net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM5 net13 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net17 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_current_mirror_pmos -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR13_2 Biasn Biasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pnmos_4_cr14_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pnmos_4_cr14_2.sp deleted file mode 100644 index 31a5f6e308..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pnmos_4_cr14_2.sp +++ /dev/null @@ -1,70 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:07:49 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM3 Voutp net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net17 net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 Vinn net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vinp net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM5 net13 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net17 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR14_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net010 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 Vbiasn net010 res=rK -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_current_mirror_pmos -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR14_2 Biasn Biasp CR14_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pnmos_4_cr15_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pnmos_4_cr15_1.sp deleted file mode 100644 index 1afee6b2bf..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pnmos_4_cr15_1.sp +++ /dev/null @@ -1,67 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:07:49 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM3 Voutp net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net17 net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 Vinn net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vinp net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM5 net13 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net17 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR15_1 Vbiasp -*.PININFO Vbiasp:O -RR1 Vbiasp gnd! res=rK -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_current_mirror_pmos -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR15_1 Biasp CR15_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pnmos_4_cr16_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pnmos_4_cr16_1.sp deleted file mode 100644 index a0585cd18d..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pnmos_4_cr16_1.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:07:49 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM3 Voutp net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net17 net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 Vinn net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vinp net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM5 net13 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net17 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR16_1 Vbiasp -*.PININFO Vbiasp:O -RR0 vdd! net6 res=rK -RR1 Vbiasp gnd! res=rK -MM2 Vbiasp Vbiasp net6 vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_current_mirror_pmos -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR16_1 Biasp CR16_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pnmos_4_cr2_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pnmos_4_cr2_2.sp deleted file mode 100644 index 43bb298e92..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pnmos_4_cr2_2.sp +++ /dev/null @@ -1,70 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:07:49 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM3 Voutp net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net17 net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 Vinn net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vinp net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM5 net13 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net17 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR2_2_wilson Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -RR0 Vbiasn gnd! res=rK -MM2 Vbiasp net12 Vbiasn gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_current_mirror_pmos -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR2_2_wilson Biasn Biasp CR2_2_wilson -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pnmos_4_cr3_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pnmos_4_cr3_2.sp deleted file mode 100644 index f18c5990ca..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pnmos_4_cr3_2.sp +++ /dev/null @@ -1,70 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:07:49 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM3 Voutp net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net17 net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 Vinn net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vinp net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM5 net13 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net17 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR3_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 net15 gnd! res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_current_mirror_pmos -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR3_2 Biasn Biasp CR3_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pnmos_4_cr4_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pnmos_4_cr4_2.sp deleted file mode 100644 index 61eda63571..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pnmos_4_cr4_2.sp +++ /dev/null @@ -1,75 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:07:49 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM3 Voutp net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net17 net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 Vinn net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vinp net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM5 net13 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net17 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR4_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM11 net023 net024 Vbiasn gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM8 net025 net010 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM9 net024 net024 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM7 net010 net010 net025 gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net025 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 net024 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net010 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_current_mirror_pmos -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR4_2 Biasn Biasp CR4_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pnmos_4_cr5_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pnmos_4_cr5_2.sp deleted file mode 100644 index 5de39fe951..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pnmos_4_cr5_2.sp +++ /dev/null @@ -1,72 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:07:49 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM3 Voutp net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net17 net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 Vinn net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vinp net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM5 net13 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net17 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR5_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM5 net014 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net014 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_current_mirror_pmos -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR5_2 Biasn Biasp CR5_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pnmos_4_cr6_3.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pnmos_4_cr6_3.sp deleted file mode 100644 index 3295955657..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pnmos_4_cr6_3.sp +++ /dev/null @@ -1,72 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:07:49 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM3 Voutp net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net17 net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 Vinn net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vinp net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM5 net13 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net17 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR6_3 Vbiasn1 Vbiasn2 Vbiasp -*.PININFO Vbiasn1:O Vbiasn2:O Vbiasp:O -MM2 Vbiasp Vbiasn2 Vbiasn1 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn2 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 Vbiasn1 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM5 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn2 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_current_mirror_pmos -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR6_3 Biasn1 Biasn2 Biasp CR6_3 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pnmos_cr13_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pnmos_cr13_1.sp deleted file mode 100644 index 1d9e32fefa..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pnmos_cr13_1.sp +++ /dev/null @@ -1,69 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:07:49 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM3 Voutp net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net17 net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 Vinn net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vinp net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM5 net13 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net17 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_current_mirror_pmos -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR13_2 Biasn Biasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pnmos_cr13_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pnmos_cr13_2.sp deleted file mode 100644 index 1d9e32fefa..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pnmos_cr13_2.sp +++ /dev/null @@ -1,69 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:07:49 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM3 Voutp net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net17 net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 Vinn net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vinp net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM5 net13 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net17 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_current_mirror_pmos -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR13_2 Biasn Biasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pnmos_cr14_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pnmos_cr14_2.sp deleted file mode 100644 index 2ce6fe3d51..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pnmos_cr14_2.sp +++ /dev/null @@ -1,70 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:07:49 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM3 Voutp net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net17 net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 Vinn net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vinp net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM5 net13 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net17 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR14_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net010 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 Vbiasn net010 res=rK -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_current_mirror_pmos -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR14_2 Biasn Biasp CR14_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pnmos_cr15_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pnmos_cr15_1.sp deleted file mode 100644 index f1cb35792a..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pnmos_cr15_1.sp +++ /dev/null @@ -1,67 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:07:49 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM3 Voutp net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net17 net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 Vinn net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vinp net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM5 net13 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net17 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR15_1 Vbiasp -*.PININFO Vbiasp:O -RR1 Vbiasp gnd! res=rK -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_current_mirror_pmos -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR15_1 Biasp CR15_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pnmos_cr16_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pnmos_cr16_1.sp deleted file mode 100644 index 1ee380b866..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pnmos_cr16_1.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:07:49 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM3 Voutp net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net17 net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 Vinn net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vinp net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM5 net13 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net17 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR16_1 Vbiasp -*.PININFO Vbiasp:O -RR0 vdd! net6 res=rK -RR1 Vbiasp gnd! res=rK -MM2 Vbiasp Vbiasp net6 vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_current_mirror_pmos -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR16_1 Biasp CR16_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pnmos_cr2_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pnmos_cr2_2.sp deleted file mode 100644 index 59918c4c20..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pnmos_cr2_2.sp +++ /dev/null @@ -1,70 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:07:49 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM3 Voutp net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net17 net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 Vinn net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vinp net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM5 net13 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net17 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR2_2_wilson Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -RR0 Vbiasn gnd! res=rK -MM2 Vbiasp net12 Vbiasn gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_current_mirror_pmos -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR2_2_wilson Biasn Biasp CR2_2_wilson -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pnmos_cr3_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pnmos_cr3_2.sp deleted file mode 100644 index 380c100763..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pnmos_cr3_2.sp +++ /dev/null @@ -1,70 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:07:49 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM3 Voutp net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net17 net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 Vinn net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vinp net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM5 net13 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net17 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR3_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 net15 gnd! res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_current_mirror_pmos -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR3_2 Biasn Biasp CR3_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pnmos_cr4_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pnmos_cr4_2.sp deleted file mode 100644 index 75e34b03e7..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pnmos_cr4_2.sp +++ /dev/null @@ -1,75 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:07:49 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM3 Voutp net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net17 net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 Vinn net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vinp net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM5 net13 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net17 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR4_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM11 net023 net024 Vbiasn gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM8 net025 net010 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM9 net024 net024 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM7 net010 net010 net025 gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net025 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 net024 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net010 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_current_mirror_pmos -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR4_2 Biasn Biasp CR4_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pnmos_cr5_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pnmos_cr5_2.sp deleted file mode 100644 index 486df672d0..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pnmos_cr5_2.sp +++ /dev/null @@ -1,72 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:07:49 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM3 Voutp net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net17 net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 Vinn net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vinp net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM5 net13 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net17 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR5_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM5 net014 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net014 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_current_mirror_pmos -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR5_2 Biasn Biasp CR5_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pnmos_cr6_3.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pnmos_cr6_3.sp deleted file mode 100644 index e7930a0cba..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_current_mirror_pmos_LG_pnmos_cr6_3.sp +++ /dev/null @@ -1,72 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:07:49 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM3 Voutp net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net17 net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 Vinn net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vinp net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM5 net13 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net17 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR6_3 Vbiasn1 Vbiasn2 Vbiasp -*.PININFO Vbiasn1:O Vbiasn2:O Vbiasp:O -MM2 Vbiasp Vbiasn2 Vbiasn1 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn2 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 Vbiasn1 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM5 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn2 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_current_mirror_pmos -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR6_3 Biasn1 Biasn2 Biasp CR6_3 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_nmos_cr13_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_nmos_cr13_1.sp deleted file mode 100644 index 8a89550a38..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_nmos_cr13_1.sp +++ /dev/null @@ -1,63 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:08:07 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_current_mirror Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net13 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net11 net18 net19 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net18 net20 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net19 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos Biasp Vbiasn -*.PININFO Biasp:I Vbiasn:O -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_low_voltage_cascode_current_mirror -xiLG_nmos Biasp LG_Vbiasn LG_nmos -xibCR13_2 Biasn Biasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_nmos_cr13_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_nmos_cr13_2.sp deleted file mode 100644 index 8a89550a38..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_nmos_cr13_2.sp +++ /dev/null @@ -1,63 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:08:07 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_current_mirror Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net13 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net11 net18 net19 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net18 net20 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net19 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos Biasp Vbiasn -*.PININFO Biasp:I Vbiasn:O -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_low_voltage_cascode_current_mirror -xiLG_nmos Biasp LG_Vbiasn LG_nmos -xibCR13_2 Biasn Biasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_nmos_cr14_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_nmos_cr14_2.sp deleted file mode 100644 index 2ada3eaa03..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_nmos_cr14_2.sp +++ /dev/null @@ -1,64 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:08:07 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_current_mirror Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net13 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net11 net18 net19 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net18 net20 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net19 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos Biasp Vbiasn -*.PININFO Biasp:I Vbiasn:O -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR14_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net010 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 Vbiasn net010 res=rK -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_low_voltage_cascode_current_mirror -xiLG_nmos Biasp LG_Vbiasn LG_nmos -xibCR14_2 Biasn Biasp CR14_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_nmos_cr15_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_nmos_cr15_1.sp deleted file mode 100644 index 13281e2546..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_nmos_cr15_1.sp +++ /dev/null @@ -1,61 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:08:07 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_current_mirror Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net13 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net11 net18 net19 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net18 net20 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net19 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos Biasp Vbiasn -*.PININFO Biasp:I Vbiasn:O -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR15_1 Vbiasp -*.PININFO Vbiasp:O -RR1 Vbiasp gnd! res=rK -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_low_voltage_cascode_current_mirror -xiLG_nmos Biasp LG_Vbiasn LG_nmos -xibCR15_1 Biasp CR15_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_nmos_cr16_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_nmos_cr16_1.sp deleted file mode 100644 index 2c1b7a0887..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_nmos_cr16_1.sp +++ /dev/null @@ -1,62 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:08:07 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_current_mirror Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net13 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net11 net18 net19 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net18 net20 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net19 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos Biasp Vbiasn -*.PININFO Biasp:I Vbiasn:O -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR16_1 Vbiasp -*.PININFO Vbiasp:O -RR0 vdd! net6 res=rK -RR1 Vbiasp gnd! res=rK -MM2 Vbiasp Vbiasp net6 vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_low_voltage_cascode_current_mirror -xiLG_nmos Biasp LG_Vbiasn LG_nmos -xibCR16_1 Biasp CR16_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_nmos_cr2_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_nmos_cr2_2.sp deleted file mode 100644 index ed8801087d..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_nmos_cr2_2.sp +++ /dev/null @@ -1,64 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:08:07 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_current_mirror Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net13 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net11 net18 net19 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net18 net20 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net19 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos Biasp Vbiasn -*.PININFO Biasp:I Vbiasn:O -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR2_2_wilson Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -RR0 Vbiasn gnd! res=rK -MM2 Vbiasp net12 Vbiasn gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_low_voltage_cascode_current_mirror -xiLG_nmos Biasp LG_Vbiasn LG_nmos -xibCR2_2_wilson Biasn Biasp CR2_2_wilson -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_nmos_cr3_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_nmos_cr3_2.sp deleted file mode 100644 index 8939cf998c..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_nmos_cr3_2.sp +++ /dev/null @@ -1,64 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:08:07 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_current_mirror Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net13 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net11 net18 net19 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net18 net20 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net19 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos Biasp Vbiasn -*.PININFO Biasp:I Vbiasn:O -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR3_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 net15 gnd! res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_low_voltage_cascode_current_mirror -xiLG_nmos Biasp LG_Vbiasn LG_nmos -xibCR3_2 Biasn Biasp CR3_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_nmos_cr4_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_nmos_cr4_2.sp deleted file mode 100644 index cb84755bb9..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_nmos_cr4_2.sp +++ /dev/null @@ -1,69 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:08:07 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_current_mirror Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net13 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net11 net18 net19 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net18 net20 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net19 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos Biasp Vbiasn -*.PININFO Biasp:I Vbiasn:O -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR4_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM11 net023 net024 Vbiasn gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM8 net025 net010 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM9 net024 net024 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM7 net010 net010 net025 gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net025 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 net024 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net010 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_low_voltage_cascode_current_mirror -xiLG_nmos Biasp LG_Vbiasn LG_nmos -xibCR4_2 Biasn Biasp CR4_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_nmos_cr5_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_nmos_cr5_2.sp deleted file mode 100644 index ddb9bd1090..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_nmos_cr5_2.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:08:07 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_current_mirror Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net13 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net11 net18 net19 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net18 net20 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net19 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos Biasp Vbiasn -*.PININFO Biasp:I Vbiasn:O -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR5_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM5 net014 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net014 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_low_voltage_cascode_current_mirror -xiLG_nmos Biasp LG_Vbiasn LG_nmos -xibCR5_2 Biasn Biasp CR5_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_nmos_cr6_3.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_nmos_cr6_3.sp deleted file mode 100644 index 37b87eadac..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_nmos_cr6_3.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:08:07 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_current_mirror Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net13 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net11 net18 net19 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net18 net20 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net19 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos Biasp Vbiasn -*.PININFO Biasp:I Vbiasn:O -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR6_3 Vbiasn1 Vbiasn2 Vbiasp -*.PININFO Vbiasn1:O Vbiasn2:O Vbiasp:O -MM2 Vbiasp Vbiasn2 Vbiasn1 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn2 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 Vbiasn1 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM5 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn2 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_low_voltage_cascode_current_mirror -xiLG_nmos Biasp LG_Vbiasn LG_nmos -xibCR6_3 Biasn1 Biasn2 Biasp CR6_3 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_nmos_l1_cr11_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_nmos_l1_cr11_1.sp deleted file mode 100644 index e1117cf310..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_nmos_l1_cr11_1.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:08:07 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_current_mirror Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net13 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net11 net18 net19 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net18 net20 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net19 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR11_1 Vbiasn -*.PININFO Vbiasn:O -RRF vdd! Vbiasn res=rK -MM1 net9 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net9 net9 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn net9 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_low_voltage_cascode_current_mirror -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR11_1 Biasn CR11_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_nmos_l1_cr12_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_nmos_l1_cr12_1.sp deleted file mode 100644 index 4a7997165c..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_nmos_l1_cr12_1.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:08:07 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_current_mirror Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net13 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net11 net18 net19 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net18 net20 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net19 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR12_1 Vbiasn -*.PININFO Vbiasn:O -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 net10 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn net10 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RRF vdd! Vbiasn res=rK -RR0 vdd! net10 res=rK -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_low_voltage_cascode_current_mirror -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR12_1 Biasn CR12_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_nmos_l1_cr13_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_nmos_l1_cr13_1.sp deleted file mode 100644 index 5b8b555a91..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_nmos_l1_cr13_1.sp +++ /dev/null @@ -1,65 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:08:07 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_current_mirror Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net13 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net11 net18 net19 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net18 net20 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net19 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_low_voltage_cascode_current_mirror -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR13_2 Biasn Vbiasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_nmos_l1_cr13_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_nmos_l1_cr13_2.sp deleted file mode 100644 index 5b8b555a91..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_nmos_l1_cr13_2.sp +++ /dev/null @@ -1,65 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:08:07 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_current_mirror Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net13 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net11 net18 net19 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net18 net20 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net19 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_low_voltage_cascode_current_mirror -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR13_2 Biasn Vbiasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_nmos_l1_cr14_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_nmos_l1_cr14_2.sp deleted file mode 100644 index a86f300dd2..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_nmos_l1_cr14_2.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:08:07 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_current_mirror Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net13 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net11 net18 net19 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net18 net20 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net19 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR14_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net010 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 Vbiasn net010 res=rK -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_low_voltage_cascode_current_mirror -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR14_2 Biasn Vbiasp CR14_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_nmos_l1_cr1_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_nmos_l1_cr1_1.sp deleted file mode 100644 index e70d04ea74..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_nmos_l1_cr1_1.sp +++ /dev/null @@ -1,63 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:08:07 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_current_mirror Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net13 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net11 net18 net19 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net18 net20 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net19 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR1_1 Vbiasn -*.PININFO Vbiasn:O -RRF vdd! Vbiasn res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_low_voltage_cascode_current_mirror -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR1_1 Biasn CR1_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_nmos_l1_cr2_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_nmos_l1_cr2_2.sp deleted file mode 100644 index ae442cfc98..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_nmos_l1_cr2_2.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:08:07 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_current_mirror Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net13 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net11 net18 net19 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net18 net20 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net19 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR2_2_wilson Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -RR0 Vbiasn gnd! res=rK -MM2 Vbiasp net12 Vbiasn gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_low_voltage_cascode_current_mirror -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR2_2_wilson Biasn Vbiasp CR2_2_wilson -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_nmos_l1_cr3_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_nmos_l1_cr3_2.sp deleted file mode 100644 index 357d9a7753..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_nmos_l1_cr3_2.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:08:07 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_current_mirror Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net13 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net11 net18 net19 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net18 net20 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net19 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR3_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 net15 gnd! res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_low_voltage_cascode_current_mirror -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR3_2 Biasn Vbiasp CR3_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_nmos_l1_cr4_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_nmos_l1_cr4_2.sp deleted file mode 100644 index ba55793a82..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_nmos_l1_cr4_2.sp +++ /dev/null @@ -1,71 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:08:07 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_current_mirror Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net13 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net11 net18 net19 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net18 net20 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net19 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR4_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM11 net023 net024 Vbiasn gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM8 net025 net010 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM9 net024 net024 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM7 net010 net010 net025 gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net025 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 net024 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net010 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_low_voltage_cascode_current_mirror -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR4_2 Biasn Vbiasp CR4_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_nmos_l1_cr5_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_nmos_l1_cr5_2.sp deleted file mode 100644 index adfd869a2e..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_nmos_l1_cr5_2.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:08:07 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_current_mirror Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net13 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net11 net18 net19 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net18 net20 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net19 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR5_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM5 net014 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net014 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_low_voltage_cascode_current_mirror -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR5_2 Biasn Vbiasp CR5_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_nmos_l1_cr7_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_nmos_l1_cr7_1.sp deleted file mode 100644 index 10817fd534..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_nmos_l1_cr7_1.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:08:07 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_current_mirror Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net13 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net11 net18 net19 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net18 net20 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net19 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR7_1 Vbiasn -*.PININFO Vbiasn:O -RR1 Vbiasn net7 res=rK -RR0 vdd! net7 res=rK -RRF vdd! Vbiasn res=rK -MM1 net7 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_low_voltage_cascode_current_mirror -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR7_1 Biasn CR7_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_nmos_l1_cr9_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_nmos_l1_cr9_1.sp deleted file mode 100644 index 5b7556f94f..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_nmos_l1_cr9_1.sp +++ /dev/null @@ -1,64 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:08:07 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_current_mirror Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net13 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net11 net18 net19 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net18 net20 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net19 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR9_1 Vbiasn -*.PININFO Vbiasn:O -RR1 net05 gnd! res=rK -RRF vdd! Vbiasn res=rK -MM0 Vbiasn Vbiasn net05 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_low_voltage_cascode_current_mirror -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR9_1 Biasn CR9_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_npmos_cr11_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_npmos_cr11_1.sp deleted file mode 100644 index bc1e6ef3b9..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_npmos_cr11_1.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:08:07 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_current_mirror Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net13 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net11 net18 net19 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net18 net20 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net19 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR11_1 Vbiasn -*.PININFO Vbiasn:O -RRF vdd! Vbiasn res=rK -MM1 net9 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net9 net9 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn net9 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_low_voltage_cascode_current_mirror -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR11_1 Biasn CR11_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_npmos_cr12_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_npmos_cr12_1.sp deleted file mode 100644 index 9782f42348..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_npmos_cr12_1.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:08:07 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_current_mirror Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net13 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net11 net18 net19 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net18 net20 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net19 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR12_1 Vbiasn -*.PININFO Vbiasn:O -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 net10 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn net10 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RRF vdd! Vbiasn res=rK -RR0 vdd! net10 res=rK -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_low_voltage_cascode_current_mirror -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR12_1 Biasn CR12_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_npmos_cr13_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_npmos_cr13_1.sp deleted file mode 100644 index 7369388e0e..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_npmos_cr13_1.sp +++ /dev/null @@ -1,67 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:08:07 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_current_mirror Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net13 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net11 net18 net19 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net18 net20 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net19 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_low_voltage_cascode_current_mirror -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR13_2 Biasn Vbiasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_npmos_cr13_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_npmos_cr13_2.sp deleted file mode 100644 index 7369388e0e..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_npmos_cr13_2.sp +++ /dev/null @@ -1,67 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:08:07 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_current_mirror Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net13 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net11 net18 net19 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net18 net20 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net19 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_low_voltage_cascode_current_mirror -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR13_2 Biasn Vbiasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_npmos_cr14_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_npmos_cr14_2.sp deleted file mode 100644 index de6a9186c1..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_npmos_cr14_2.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:08:07 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_current_mirror Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net13 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net11 net18 net19 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net18 net20 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net19 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR14_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net010 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 Vbiasn net010 res=rK -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_low_voltage_cascode_current_mirror -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR14_2 Biasn Vbiasp CR14_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_npmos_cr1_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_npmos_cr1_1.sp deleted file mode 100644 index 131a51e3ed..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_npmos_cr1_1.sp +++ /dev/null @@ -1,65 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:08:07 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_current_mirror Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net13 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net11 net18 net19 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net18 net20 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net19 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR1_1 Vbiasn -*.PININFO Vbiasn:O -RRF vdd! Vbiasn res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_low_voltage_cascode_current_mirror -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR1_1 Biasn CR1_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_npmos_cr2_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_npmos_cr2_2.sp deleted file mode 100644 index db3a46d3c1..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_npmos_cr2_2.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:08:07 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_current_mirror Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net13 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net11 net18 net19 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net18 net20 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net19 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR2_2_wilson Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -RR0 Vbiasn gnd! res=rK -MM2 Vbiasp net12 Vbiasn gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_low_voltage_cascode_current_mirror -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR2_2_wilson Biasn Vbiasp CR2_2_wilson -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_npmos_cr3_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_npmos_cr3_2.sp deleted file mode 100644 index a96dcf0275..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_npmos_cr3_2.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:08:07 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_current_mirror Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net13 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net11 net18 net19 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net18 net20 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net19 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR3_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 net15 gnd! res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_low_voltage_cascode_current_mirror -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR3_2 Biasn Vbiasp CR3_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_npmos_cr4_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_npmos_cr4_2.sp deleted file mode 100644 index 1950a4bb8b..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_npmos_cr4_2.sp +++ /dev/null @@ -1,73 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:08:07 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_current_mirror Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net13 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net11 net18 net19 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net18 net20 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net19 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR4_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM11 net023 net024 Vbiasn gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM8 net025 net010 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM9 net024 net024 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM7 net010 net010 net025 gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net025 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 net024 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net010 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_low_voltage_cascode_current_mirror -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR4_2 Biasn Vbiasp CR4_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_npmos_cr5_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_npmos_cr5_2.sp deleted file mode 100644 index 35a9cd9ec3..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_npmos_cr5_2.sp +++ /dev/null @@ -1,70 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:08:07 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_current_mirror Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net13 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net11 net18 net19 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net18 net20 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net19 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR5_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM5 net014 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net014 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_low_voltage_cascode_current_mirror -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR5_2 Biasn Vbiasp CR5_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_npmos_cr7_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_npmos_cr7_1.sp deleted file mode 100644 index fa641cdcbb..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_npmos_cr7_1.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:08:07 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_current_mirror Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net13 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net11 net18 net19 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net18 net20 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net19 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR7_1 Vbiasn -*.PININFO Vbiasn:O -RR1 Vbiasn net7 res=rK -RR0 vdd! net7 res=rK -RRF vdd! Vbiasn res=rK -MM1 net7 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_low_voltage_cascode_current_mirror -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR7_1 Biasn CR7_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_npmos_cr9_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_npmos_cr9_1.sp deleted file mode 100644 index 92ba6652d3..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_npmos_cr9_1.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:08:07 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_current_mirror Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net13 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net11 net18 net19 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net18 net20 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net19 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR9_1 Vbiasn -*.PININFO Vbiasn:O -RR1 net05 gnd! res=rK -RRF vdd! Vbiasn res=rK -MM0 Vbiasn Vbiasn net05 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_low_voltage_cascode_current_mirror -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR9_1 Biasn CR9_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_pmos_l1_cr13_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_pmos_l1_cr13_1.sp deleted file mode 100644 index 6cb191910e..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_pmos_l1_cr13_1.sp +++ /dev/null @@ -1,65 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:08:07 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_current_mirror Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net13 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net11 net18 net19 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net18 net20 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net19 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_low_voltage_cascode_current_mirror -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR13_2 Biasn Biasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_pmos_l1_cr13_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_pmos_l1_cr13_2.sp deleted file mode 100644 index 6cb191910e..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_pmos_l1_cr13_2.sp +++ /dev/null @@ -1,65 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:08:07 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_current_mirror Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net13 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net11 net18 net19 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net18 net20 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net19 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_low_voltage_cascode_current_mirror -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR13_2 Biasn Biasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_pmos_l1_cr14_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_pmos_l1_cr14_2.sp deleted file mode 100644 index 65e6016c7e..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_pmos_l1_cr14_2.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:08:07 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_current_mirror Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net13 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net11 net18 net19 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net18 net20 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net19 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR14_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net010 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 Vbiasn net010 res=rK -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_low_voltage_cascode_current_mirror -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR14_2 Biasn Biasp CR14_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_pmos_l1_cr15_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_pmos_l1_cr15_1.sp deleted file mode 100644 index 2b947623fd..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_pmos_l1_cr15_1.sp +++ /dev/null @@ -1,63 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:08:07 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_current_mirror Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net13 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net11 net18 net19 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net18 net20 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net19 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR15_1 Vbiasp -*.PININFO Vbiasp:O -RR1 Vbiasp gnd! res=rK -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_low_voltage_cascode_current_mirror -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR15_1 Biasp CR15_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_pmos_l1_cr16_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_pmos_l1_cr16_1.sp deleted file mode 100644 index 2dec67c40f..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_pmos_l1_cr16_1.sp +++ /dev/null @@ -1,64 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:08:07 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_current_mirror Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net13 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net11 net18 net19 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net18 net20 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net19 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR16_1 Vbiasp -*.PININFO Vbiasp:O -RR0 vdd! net6 res=rK -RR1 Vbiasp gnd! res=rK -MM2 Vbiasp Vbiasp net6 vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_low_voltage_cascode_current_mirror -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR16_1 Biasp CR16_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_pmos_l1_cr2_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_pmos_l1_cr2_2.sp deleted file mode 100644 index 2999751578..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_pmos_l1_cr2_2.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:08:07 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_current_mirror Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net13 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net11 net18 net19 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net18 net20 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net19 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR2_2_wilson Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -RR0 Vbiasn gnd! res=rK -MM2 Vbiasp net12 Vbiasn gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_low_voltage_cascode_current_mirror -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR2_2_wilson Biasn Biasp CR2_2_wilson -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_pmos_l1_cr3_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_pmos_l1_cr3_2.sp deleted file mode 100644 index f223079c96..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_pmos_l1_cr3_2.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:08:07 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_current_mirror Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net13 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net11 net18 net19 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net18 net20 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net19 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR3_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 net15 gnd! res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_low_voltage_cascode_current_mirror -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR3_2 Biasn Biasp CR3_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_pmos_l1_cr4_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_pmos_l1_cr4_2.sp deleted file mode 100644 index 13d3d6e5ed..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_pmos_l1_cr4_2.sp +++ /dev/null @@ -1,71 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:08:07 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_current_mirror Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net13 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net11 net18 net19 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net18 net20 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net19 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR4_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM11 net023 net024 Vbiasn gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM8 net025 net010 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM9 net024 net024 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM7 net010 net010 net025 gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net025 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 net024 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net010 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_low_voltage_cascode_current_mirror -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR4_2 Biasn Biasp CR4_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_pmos_l1_cr5_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_pmos_l1_cr5_2.sp deleted file mode 100644 index 2d19e3dede..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_pmos_l1_cr5_2.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:08:07 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_current_mirror Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net13 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net11 net18 net19 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net18 net20 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net19 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR5_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM5 net014 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net014 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_low_voltage_cascode_current_mirror -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR5_2 Biasn Biasp CR5_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_pmos_l1_cr6_3.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_pmos_l1_cr6_3.sp deleted file mode 100644 index 063ccac3d9..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_pmos_l1_cr6_3.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:08:07 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_current_mirror Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net13 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net11 net18 net19 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net18 net20 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net19 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR6_3 Vbiasn1 Vbiasn2 Vbiasp -*.PININFO Vbiasn1:O Vbiasn2:O Vbiasp:O -MM2 Vbiasp Vbiasn2 Vbiasn1 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn2 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 Vbiasn1 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM5 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn2 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_low_voltage_cascode_current_mirror -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR6_3 Biasn1 Biasn2 Biasp CR6_3 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_pnmos_4_cr13_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_pnmos_4_cr13_1.sp deleted file mode 100644 index ec2ecf092e..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_pnmos_4_cr13_1.sp +++ /dev/null @@ -1,67 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:08:07 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_current_mirror Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net13 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net11 net18 net19 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net18 net20 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net19 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_low_voltage_cascode_current_mirror -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR13_2 Biasn Biasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_pnmos_4_cr13_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_pnmos_4_cr13_2.sp deleted file mode 100644 index ec2ecf092e..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_pnmos_4_cr13_2.sp +++ /dev/null @@ -1,67 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:08:07 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_current_mirror Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net13 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net11 net18 net19 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net18 net20 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net19 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_low_voltage_cascode_current_mirror -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR13_2 Biasn Biasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_pnmos_4_cr14_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_pnmos_4_cr14_2.sp deleted file mode 100644 index 2c1a566a03..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_pnmos_4_cr14_2.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:08:07 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_current_mirror Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net13 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net11 net18 net19 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net18 net20 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net19 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR14_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net010 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 Vbiasn net010 res=rK -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_low_voltage_cascode_current_mirror -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR14_2 Biasn Biasp CR14_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_pnmos_4_cr15_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_pnmos_4_cr15_1.sp deleted file mode 100644 index 09e05a6dca..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_pnmos_4_cr15_1.sp +++ /dev/null @@ -1,65 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:08:07 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_current_mirror Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net13 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net11 net18 net19 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net18 net20 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net19 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR15_1 Vbiasp -*.PININFO Vbiasp:O -RR1 Vbiasp gnd! res=rK -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_low_voltage_cascode_current_mirror -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR15_1 Biasp CR15_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_pnmos_4_cr16_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_pnmos_4_cr16_1.sp deleted file mode 100644 index a314db3768..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_pnmos_4_cr16_1.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:08:07 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_current_mirror Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net13 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net11 net18 net19 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net18 net20 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net19 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR16_1 Vbiasp -*.PININFO Vbiasp:O -RR0 vdd! net6 res=rK -RR1 Vbiasp gnd! res=rK -MM2 Vbiasp Vbiasp net6 vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_low_voltage_cascode_current_mirror -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR16_1 Biasp CR16_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_pnmos_4_cr2_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_pnmos_4_cr2_2.sp deleted file mode 100644 index 373e3b35db..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_pnmos_4_cr2_2.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:08:07 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_current_mirror Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net13 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net11 net18 net19 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net18 net20 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net19 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR2_2_wilson Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -RR0 Vbiasn gnd! res=rK -MM2 Vbiasp net12 Vbiasn gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_low_voltage_cascode_current_mirror -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR2_2_wilson Biasn Biasp CR2_2_wilson -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_pnmos_4_cr3_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_pnmos_4_cr3_2.sp deleted file mode 100644 index 3376cb8f94..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_pnmos_4_cr3_2.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:08:07 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_current_mirror Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net13 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net11 net18 net19 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net18 net20 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net19 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR3_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 net15 gnd! res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_low_voltage_cascode_current_mirror -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR3_2 Biasn Biasp CR3_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_pnmos_4_cr4_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_pnmos_4_cr4_2.sp deleted file mode 100644 index 073fea7d85..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_pnmos_4_cr4_2.sp +++ /dev/null @@ -1,73 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:08:07 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_current_mirror Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net13 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net11 net18 net19 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net18 net20 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net19 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR4_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM11 net023 net024 Vbiasn gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM8 net025 net010 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM9 net024 net024 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM7 net010 net010 net025 gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net025 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 net024 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net010 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_low_voltage_cascode_current_mirror -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR4_2 Biasn Biasp CR4_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_pnmos_4_cr5_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_pnmos_4_cr5_2.sp deleted file mode 100644 index 86f3a0a05b..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_pnmos_4_cr5_2.sp +++ /dev/null @@ -1,70 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:08:07 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_current_mirror Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net13 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net11 net18 net19 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net18 net20 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net19 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR5_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM5 net014 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net014 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_low_voltage_cascode_current_mirror -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR5_2 Biasn Biasp CR5_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_pnmos_4_cr6_3.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_pnmos_4_cr6_3.sp deleted file mode 100644 index d36cc9d554..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_pnmos_4_cr6_3.sp +++ /dev/null @@ -1,70 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:08:07 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_current_mirror Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net13 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net11 net18 net19 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net18 net20 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net19 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR6_3 Vbiasn1 Vbiasn2 Vbiasp -*.PININFO Vbiasn1:O Vbiasn2:O Vbiasp:O -MM2 Vbiasp Vbiasn2 Vbiasn1 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn2 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 Vbiasn1 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM5 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn2 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_low_voltage_cascode_current_mirror -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR6_3 Biasn1 Biasn2 Biasp CR6_3 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_pnmos_cr13_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_pnmos_cr13_1.sp deleted file mode 100644 index c2ee1bced3..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_pnmos_cr13_1.sp +++ /dev/null @@ -1,67 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:08:07 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_current_mirror Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net13 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net11 net18 net19 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net18 net20 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net19 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_low_voltage_cascode_current_mirror -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR13_2 Biasn Biasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_pnmos_cr13_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_pnmos_cr13_2.sp deleted file mode 100644 index c2ee1bced3..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_pnmos_cr13_2.sp +++ /dev/null @@ -1,67 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:08:07 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_current_mirror Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net13 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net11 net18 net19 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net18 net20 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net19 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_low_voltage_cascode_current_mirror -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR13_2 Biasn Biasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_pnmos_cr14_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_pnmos_cr14_2.sp deleted file mode 100644 index fd43821e8e..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_pnmos_cr14_2.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:08:07 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_current_mirror Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net13 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net11 net18 net19 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net18 net20 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net19 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR14_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net010 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 Vbiasn net010 res=rK -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_low_voltage_cascode_current_mirror -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR14_2 Biasn Biasp CR14_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_pnmos_cr15_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_pnmos_cr15_1.sp deleted file mode 100644 index d61c035a54..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_pnmos_cr15_1.sp +++ /dev/null @@ -1,65 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:08:07 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_current_mirror Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net13 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net11 net18 net19 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net18 net20 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net19 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR15_1 Vbiasp -*.PININFO Vbiasp:O -RR1 Vbiasp gnd! res=rK -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_low_voltage_cascode_current_mirror -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR15_1 Biasp CR15_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_pnmos_cr16_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_pnmos_cr16_1.sp deleted file mode 100644 index f1027f90c7..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_pnmos_cr16_1.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:08:07 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_current_mirror Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net13 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net11 net18 net19 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net18 net20 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net19 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR16_1 Vbiasp -*.PININFO Vbiasp:O -RR0 vdd! net6 res=rK -RR1 Vbiasp gnd! res=rK -MM2 Vbiasp Vbiasp net6 vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_low_voltage_cascode_current_mirror -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR16_1 Biasp CR16_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_pnmos_cr2_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_pnmos_cr2_2.sp deleted file mode 100644 index 5ae362c4e6..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_pnmos_cr2_2.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:08:07 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_current_mirror Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net13 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net11 net18 net19 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net18 net20 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net19 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR2_2_wilson Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -RR0 Vbiasn gnd! res=rK -MM2 Vbiasp net12 Vbiasn gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_low_voltage_cascode_current_mirror -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR2_2_wilson Biasn Biasp CR2_2_wilson -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_pnmos_cr3_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_pnmos_cr3_2.sp deleted file mode 100644 index 5a1ff6dade..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_pnmos_cr3_2.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:08:07 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_current_mirror Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net13 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net11 net18 net19 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net18 net20 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net19 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR3_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 net15 gnd! res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_low_voltage_cascode_current_mirror -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR3_2 Biasn Biasp CR3_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_pnmos_cr4_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_pnmos_cr4_2.sp deleted file mode 100644 index 1e7039f253..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_pnmos_cr4_2.sp +++ /dev/null @@ -1,73 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:08:07 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_current_mirror Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net13 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net11 net18 net19 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net18 net20 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net19 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR4_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM11 net023 net024 Vbiasn gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM8 net025 net010 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM9 net024 net024 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM7 net010 net010 net025 gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net025 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 net024 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net010 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_low_voltage_cascode_current_mirror -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR4_2 Biasn Biasp CR4_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_pnmos_cr5_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_pnmos_cr5_2.sp deleted file mode 100644 index b61a5c5f01..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_pnmos_cr5_2.sp +++ /dev/null @@ -1,70 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:08:07 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_current_mirror Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net13 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net11 net18 net19 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net18 net20 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net19 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR5_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM5 net014 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net014 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_low_voltage_cascode_current_mirror -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR5_2 Biasn Biasp CR5_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_pnmos_cr6_3.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_pnmos_cr6_3.sp deleted file mode 100644 index 075a5b61d3..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_current_mirror_LG_pnmos_cr6_3.sp +++ /dev/null @@ -1,70 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:08:07 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_current_mirror Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net13 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net11 net18 net19 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net18 net20 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net19 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR6_3 Vbiasn1 Vbiasn2 Vbiasp -*.PININFO Vbiasn1:O Vbiasn2:O Vbiasp:O -MM2 Vbiasp Vbiasn2 Vbiasn1 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn2 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 Vbiasn1 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM5 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn2 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_low_voltage_cascode_current_mirror -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR6_3 Biasn1 Biasn2 Biasp CR6_3 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_nmos_l1_cr11_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_nmos_l1_cr11_1.sp deleted file mode 100644 index 2a41e6b2ca..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_nmos_l1_cr11_1.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:08:22 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM7 Voutp Vinn net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM6 net13 Vinp net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM5 net11 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net17 net20 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net13 net17 net19 gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net20 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net19 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR11_1 Vbiasn -*.PININFO Vbiasn:O -RRF vdd! Vbiasn res=rK -MM1 net9 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net9 net9 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn net9 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_low_voltage_cascode_pmos -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR11_1 Biasn CR11_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_nmos_l1_cr12_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_nmos_l1_cr12_1.sp deleted file mode 100644 index 4179bc9c09..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_nmos_l1_cr12_1.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:08:22 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM7 Voutp Vinn net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM6 net13 Vinp net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM5 net11 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net17 net20 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net13 net17 net19 gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net20 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net19 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR12_1 Vbiasn -*.PININFO Vbiasn:O -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 net10 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn net10 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RRF vdd! Vbiasn res=rK -RR0 vdd! net10 res=rK -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_low_voltage_cascode_pmos -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR12_1 Biasn CR12_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_nmos_l1_cr13_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_nmos_l1_cr13_1.sp deleted file mode 100644 index 1ec4fc57b0..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_nmos_l1_cr13_1.sp +++ /dev/null @@ -1,65 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:08:22 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM7 Voutp Vinn net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM6 net13 Vinp net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM5 net11 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net17 net20 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net13 net17 net19 gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net20 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net19 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_low_voltage_cascode_pmos -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR13_2 Biasn Vbiasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_nmos_l1_cr13_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_nmos_l1_cr13_2.sp deleted file mode 100644 index 1ec4fc57b0..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_nmos_l1_cr13_2.sp +++ /dev/null @@ -1,65 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:08:22 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM7 Voutp Vinn net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM6 net13 Vinp net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM5 net11 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net17 net20 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net13 net17 net19 gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net20 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net19 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_low_voltage_cascode_pmos -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR13_2 Biasn Vbiasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_nmos_l1_cr14_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_nmos_l1_cr14_2.sp deleted file mode 100644 index 59c5959f84..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_nmos_l1_cr14_2.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:08:22 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM7 Voutp Vinn net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM6 net13 Vinp net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM5 net11 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net17 net20 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net13 net17 net19 gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net20 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net19 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR14_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net010 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 Vbiasn net010 res=rK -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_low_voltage_cascode_pmos -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR14_2 Biasn Vbiasp CR14_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_nmos_l1_cr1_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_nmos_l1_cr1_1.sp deleted file mode 100644 index 3100c8bbd1..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_nmos_l1_cr1_1.sp +++ /dev/null @@ -1,63 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:08:22 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM7 Voutp Vinn net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM6 net13 Vinp net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM5 net11 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net17 net20 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net13 net17 net19 gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net20 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net19 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR1_1 Vbiasn -*.PININFO Vbiasn:O -RRF vdd! Vbiasn res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_low_voltage_cascode_pmos -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR1_1 Biasn CR1_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_nmos_l1_cr2_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_nmos_l1_cr2_2.sp deleted file mode 100644 index 4e99572082..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_nmos_l1_cr2_2.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:08:22 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM7 Voutp Vinn net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM6 net13 Vinp net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM5 net11 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net17 net20 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net13 net17 net19 gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net20 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net19 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR2_2_wilson Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -RR0 Vbiasn gnd! res=rK -MM2 Vbiasp net12 Vbiasn gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_low_voltage_cascode_pmos -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR2_2_wilson Biasn Vbiasp CR2_2_wilson -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_nmos_l1_cr3_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_nmos_l1_cr3_2.sp deleted file mode 100644 index 440bcdada3..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_nmos_l1_cr3_2.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:08:22 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM7 Voutp Vinn net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM6 net13 Vinp net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM5 net11 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net17 net20 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net13 net17 net19 gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net20 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net19 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR3_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 net15 gnd! res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_low_voltage_cascode_pmos -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR3_2 Biasn Vbiasp CR3_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_nmos_l1_cr4_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_nmos_l1_cr4_2.sp deleted file mode 100644 index 70499d0589..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_nmos_l1_cr4_2.sp +++ /dev/null @@ -1,71 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:08:22 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM7 Voutp Vinn net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM6 net13 Vinp net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM5 net11 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net17 net20 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net13 net17 net19 gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net20 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net19 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR4_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM11 net023 net024 Vbiasn gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM8 net025 net010 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM9 net024 net024 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM7 net010 net010 net025 gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net025 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 net024 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net010 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_low_voltage_cascode_pmos -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR4_2 Biasn Vbiasp CR4_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_nmos_l1_cr5_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_nmos_l1_cr5_2.sp deleted file mode 100644 index 23d014f151..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_nmos_l1_cr5_2.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:08:22 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM7 Voutp Vinn net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM6 net13 Vinp net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM5 net11 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net17 net20 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net13 net17 net19 gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net20 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net19 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR5_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM5 net014 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net014 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_low_voltage_cascode_pmos -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR5_2 Biasn Vbiasp CR5_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_nmos_l1_cr7_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_nmos_l1_cr7_1.sp deleted file mode 100644 index d3e22a0290..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_nmos_l1_cr7_1.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:08:22 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM7 Voutp Vinn net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM6 net13 Vinp net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM5 net11 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net17 net20 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net13 net17 net19 gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net20 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net19 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR7_1 Vbiasn -*.PININFO Vbiasn:O -RR1 Vbiasn net7 res=rK -RR0 vdd! net7 res=rK -RRF vdd! Vbiasn res=rK -MM1 net7 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_low_voltage_cascode_pmos -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR7_1 Biasn CR7_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_nmos_l1_cr9_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_nmos_l1_cr9_1.sp deleted file mode 100644 index 516a7cbafa..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_nmos_l1_cr9_1.sp +++ /dev/null @@ -1,64 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:08:22 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM7 Voutp Vinn net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM6 net13 Vinp net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM5 net11 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net17 net20 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net13 net17 net19 gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net20 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net19 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR9_1 Vbiasn -*.PININFO Vbiasn:O -RR1 net05 gnd! res=rK -RRF vdd! Vbiasn res=rK -MM0 Vbiasn Vbiasn net05 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_low_voltage_cascode_pmos -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR9_1 Biasn CR9_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_npmos_cr11_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_npmos_cr11_1.sp deleted file mode 100644 index 8521fe6c55..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_npmos_cr11_1.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:08:22 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM7 Voutp Vinn net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM6 net13 Vinp net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM5 net11 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net17 net20 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net13 net17 net19 gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net20 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net19 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR11_1 Vbiasn -*.PININFO Vbiasn:O -RRF vdd! Vbiasn res=rK -MM1 net9 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net9 net9 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn net9 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_low_voltage_cascode_pmos -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR11_1 Biasn CR11_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_npmos_cr12_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_npmos_cr12_1.sp deleted file mode 100644 index 9f112ecd65..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_npmos_cr12_1.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:08:22 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM7 Voutp Vinn net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM6 net13 Vinp net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM5 net11 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net17 net20 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net13 net17 net19 gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net20 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net19 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR12_1 Vbiasn -*.PININFO Vbiasn:O -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 net10 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn net10 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RRF vdd! Vbiasn res=rK -RR0 vdd! net10 res=rK -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_low_voltage_cascode_pmos -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR12_1 Biasn CR12_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_npmos_cr13_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_npmos_cr13_1.sp deleted file mode 100644 index 4bad385e7a..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_npmos_cr13_1.sp +++ /dev/null @@ -1,67 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:08:22 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM7 Voutp Vinn net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM6 net13 Vinp net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM5 net11 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net17 net20 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net13 net17 net19 gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net20 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net19 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_low_voltage_cascode_pmos -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR13_2 Biasn Vbiasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_npmos_cr13_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_npmos_cr13_2.sp deleted file mode 100644 index 4bad385e7a..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_npmos_cr13_2.sp +++ /dev/null @@ -1,67 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:08:22 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM7 Voutp Vinn net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM6 net13 Vinp net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM5 net11 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net17 net20 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net13 net17 net19 gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net20 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net19 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_low_voltage_cascode_pmos -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR13_2 Biasn Vbiasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_npmos_cr14_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_npmos_cr14_2.sp deleted file mode 100644 index 44f5e1bfa0..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_npmos_cr14_2.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:08:22 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM7 Voutp Vinn net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM6 net13 Vinp net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM5 net11 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net17 net20 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net13 net17 net19 gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net20 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net19 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR14_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net010 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 Vbiasn net010 res=rK -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_low_voltage_cascode_pmos -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR14_2 Biasn Vbiasp CR14_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_npmos_cr1_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_npmos_cr1_1.sp deleted file mode 100644 index 832ae906ec..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_npmos_cr1_1.sp +++ /dev/null @@ -1,65 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:08:22 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM7 Voutp Vinn net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM6 net13 Vinp net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM5 net11 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net17 net20 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net13 net17 net19 gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net20 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net19 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR1_1 Vbiasn -*.PININFO Vbiasn:O -RRF vdd! Vbiasn res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_low_voltage_cascode_pmos -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR1_1 Biasn CR1_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_npmos_cr2_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_npmos_cr2_2.sp deleted file mode 100644 index 1028c98c1e..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_npmos_cr2_2.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:08:22 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM7 Voutp Vinn net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM6 net13 Vinp net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM5 net11 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net17 net20 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net13 net17 net19 gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net20 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net19 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR2_2_wilson Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -RR0 Vbiasn gnd! res=rK -MM2 Vbiasp net12 Vbiasn gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_low_voltage_cascode_pmos -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR2_2_wilson Biasn Vbiasp CR2_2_wilson -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_npmos_cr3_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_npmos_cr3_2.sp deleted file mode 100644 index f77d31f070..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_npmos_cr3_2.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:08:22 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM7 Voutp Vinn net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM6 net13 Vinp net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM5 net11 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net17 net20 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net13 net17 net19 gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net20 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net19 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR3_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 net15 gnd! res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_low_voltage_cascode_pmos -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR3_2 Biasn Vbiasp CR3_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_npmos_cr4_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_npmos_cr4_2.sp deleted file mode 100644 index 164245931f..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_npmos_cr4_2.sp +++ /dev/null @@ -1,73 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:08:22 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM7 Voutp Vinn net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM6 net13 Vinp net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM5 net11 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net17 net20 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net13 net17 net19 gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net20 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net19 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR4_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM11 net023 net024 Vbiasn gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM8 net025 net010 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM9 net024 net024 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM7 net010 net010 net025 gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net025 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 net024 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net010 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_low_voltage_cascode_pmos -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR4_2 Biasn Vbiasp CR4_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_npmos_cr5_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_npmos_cr5_2.sp deleted file mode 100644 index 7ff8c5b8e3..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_npmos_cr5_2.sp +++ /dev/null @@ -1,70 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:08:22 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM7 Voutp Vinn net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM6 net13 Vinp net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM5 net11 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net17 net20 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net13 net17 net19 gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net20 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net19 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR5_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM5 net014 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net014 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_low_voltage_cascode_pmos -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR5_2 Biasn Vbiasp CR5_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_npmos_cr7_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_npmos_cr7_1.sp deleted file mode 100644 index 500151a178..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_npmos_cr7_1.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:08:22 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM7 Voutp Vinn net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM6 net13 Vinp net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM5 net11 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net17 net20 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net13 net17 net19 gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net20 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net19 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR7_1 Vbiasn -*.PININFO Vbiasn:O -RR1 Vbiasn net7 res=rK -RR0 vdd! net7 res=rK -RRF vdd! Vbiasn res=rK -MM1 net7 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_low_voltage_cascode_pmos -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR7_1 Biasn CR7_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_npmos_cr9_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_npmos_cr9_1.sp deleted file mode 100644 index efc4fedce2..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_npmos_cr9_1.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:08:22 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM7 Voutp Vinn net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM6 net13 Vinp net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM5 net11 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net17 net20 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net13 net17 net19 gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net20 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net19 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR9_1 Vbiasn -*.PININFO Vbiasn:O -RR1 net05 gnd! res=rK -RRF vdd! Vbiasn res=rK -MM0 Vbiasn Vbiasn net05 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_low_voltage_cascode_pmos -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR9_1 Biasn CR9_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pmos_cr11_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pmos_cr11_1.sp deleted file mode 100644 index a250c76520..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pmos_cr11_1.sp +++ /dev/null @@ -1,64 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:08:22 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM7 Voutp Vinn net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM6 net13 Vinp net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM5 net11 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net17 net20 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net13 net17 net19 gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net20 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net19 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos Biasn Vbiasp -*.PININFO Biasn:I Vbiasp:O -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR11_1 Vbiasn -*.PININFO Vbiasn:O -RRF vdd! Vbiasn res=rK -MM1 net9 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net9 net9 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn net9 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_low_voltage_cascode_pmos -xiLG_pmos Biasn LG_Vbiasp LG_pmos -xibCR11_1 Biasn CR11_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pmos_cr12_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pmos_cr12_1.sp deleted file mode 100644 index 46d0c70c7f..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pmos_cr12_1.sp +++ /dev/null @@ -1,64 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:08:22 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM7 Voutp Vinn net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM6 net13 Vinp net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM5 net11 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net17 net20 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net13 net17 net19 gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net20 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net19 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos Biasn Vbiasp -*.PININFO Biasn:I Vbiasp:O -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR12_1 Vbiasn -*.PININFO Vbiasn:O -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 net10 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn net10 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RRF vdd! Vbiasn res=rK -RR0 vdd! net10 res=rK -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_low_voltage_cascode_pmos -xiLG_pmos Biasn LG_Vbiasp LG_pmos -xibCR12_1 Biasn CR12_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pmos_cr13_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pmos_cr13_1.sp deleted file mode 100644 index 037680a805..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pmos_cr13_1.sp +++ /dev/null @@ -1,63 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:08:22 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM7 Voutp Vinn net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM6 net13 Vinp net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM5 net11 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net17 net20 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net13 net17 net19 gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net20 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net19 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos Biasn Vbiasp -*.PININFO Biasn:I Vbiasp:O -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_low_voltage_cascode_pmos -xiLG_pmos Biasn LG_Vbiasp LG_pmos -xibCR13_2 Biasn Vbiasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pmos_cr13_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pmos_cr13_2.sp deleted file mode 100644 index 037680a805..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pmos_cr13_2.sp +++ /dev/null @@ -1,63 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:08:22 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM7 Voutp Vinn net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM6 net13 Vinp net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM5 net11 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net17 net20 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net13 net17 net19 gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net20 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net19 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos Biasn Vbiasp -*.PININFO Biasn:I Vbiasp:O -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_low_voltage_cascode_pmos -xiLG_pmos Biasn LG_Vbiasp LG_pmos -xibCR13_2 Biasn Vbiasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pmos_cr14_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pmos_cr14_2.sp deleted file mode 100644 index a8d34f07bd..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pmos_cr14_2.sp +++ /dev/null @@ -1,64 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:08:22 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM7 Voutp Vinn net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM6 net13 Vinp net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM5 net11 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net17 net20 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net13 net17 net19 gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net20 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net19 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos Biasn Vbiasp -*.PININFO Biasn:I Vbiasp:O -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR14_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net010 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 Vbiasn net010 res=rK -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_low_voltage_cascode_pmos -xiLG_pmos Biasn LG_Vbiasp LG_pmos -xibCR14_2 Biasn Vbiasp CR14_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pmos_cr1_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pmos_cr1_1.sp deleted file mode 100644 index 84c27d76a2..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pmos_cr1_1.sp +++ /dev/null @@ -1,61 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:08:22 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM7 Voutp Vinn net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM6 net13 Vinp net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM5 net11 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net17 net20 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net13 net17 net19 gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net20 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net19 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos Biasn Vbiasp -*.PININFO Biasn:I Vbiasp:O -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR1_1 Vbiasn -*.PININFO Vbiasn:O -RRF vdd! Vbiasn res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_low_voltage_cascode_pmos -xiLG_pmos Biasn LG_Vbiasp LG_pmos -xibCR1_1 Biasn CR1_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pmos_cr2_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pmos_cr2_2.sp deleted file mode 100644 index 633f898114..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pmos_cr2_2.sp +++ /dev/null @@ -1,64 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:08:22 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM7 Voutp Vinn net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM6 net13 Vinp net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM5 net11 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net17 net20 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net13 net17 net19 gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net20 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net19 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos Biasn Vbiasp -*.PININFO Biasn:I Vbiasp:O -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR2_2_wilson Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -RR0 Vbiasn gnd! res=rK -MM2 Vbiasp net12 Vbiasn gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_low_voltage_cascode_pmos -xiLG_pmos Biasn LG_Vbiasp LG_pmos -xibCR2_2_wilson Biasn Vbiasp CR2_2_wilson -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pmos_cr3_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pmos_cr3_2.sp deleted file mode 100644 index 4838eb1f23..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pmos_cr3_2.sp +++ /dev/null @@ -1,64 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:08:22 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM7 Voutp Vinn net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM6 net13 Vinp net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM5 net11 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net17 net20 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net13 net17 net19 gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net20 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net19 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos Biasn Vbiasp -*.PININFO Biasn:I Vbiasp:O -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR3_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 net15 gnd! res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_low_voltage_cascode_pmos -xiLG_pmos Biasn LG_Vbiasp LG_pmos -xibCR3_2 Biasn Vbiasp CR3_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pmos_cr4_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pmos_cr4_2.sp deleted file mode 100644 index efbbf270a6..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pmos_cr4_2.sp +++ /dev/null @@ -1,69 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:08:22 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM7 Voutp Vinn net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM6 net13 Vinp net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM5 net11 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net17 net20 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net13 net17 net19 gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net20 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net19 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos Biasn Vbiasp -*.PININFO Biasn:I Vbiasp:O -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR4_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM11 net023 net024 Vbiasn gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM8 net025 net010 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM9 net024 net024 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM7 net010 net010 net025 gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net025 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 net024 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net010 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_low_voltage_cascode_pmos -xiLG_pmos Biasn LG_Vbiasp LG_pmos -xibCR4_2 Biasn Vbiasp CR4_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pmos_cr5_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pmos_cr5_2.sp deleted file mode 100644 index 0e3bc218ae..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pmos_cr5_2.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:08:22 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM7 Voutp Vinn net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM6 net13 Vinp net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM5 net11 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net17 net20 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net13 net17 net19 gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net20 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net19 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos Biasn Vbiasp -*.PININFO Biasn:I Vbiasp:O -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR5_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM5 net014 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net014 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_low_voltage_cascode_pmos -xiLG_pmos Biasn LG_Vbiasp LG_pmos -xibCR5_2 Biasn Vbiasp CR5_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pmos_cr7_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pmos_cr7_1.sp deleted file mode 100644 index 2f3f03cbe4..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pmos_cr7_1.sp +++ /dev/null @@ -1,64 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:08:22 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM7 Voutp Vinn net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM6 net13 Vinp net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM5 net11 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net17 net20 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net13 net17 net19 gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net20 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net19 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos Biasn Vbiasp -*.PININFO Biasn:I Vbiasp:O -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR7_1 Vbiasn -*.PININFO Vbiasn:O -RR1 Vbiasn net7 res=rK -RR0 vdd! net7 res=rK -RRF vdd! Vbiasn res=rK -MM1 net7 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_low_voltage_cascode_pmos -xiLG_pmos Biasn LG_Vbiasp LG_pmos -xibCR7_1 Biasn CR7_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pmos_cr9_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pmos_cr9_1.sp deleted file mode 100644 index dde677fbfe..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pmos_cr9_1.sp +++ /dev/null @@ -1,62 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:08:22 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM7 Voutp Vinn net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM6 net13 Vinp net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM5 net11 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net17 net20 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net13 net17 net19 gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net20 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net19 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos Biasn Vbiasp -*.PININFO Biasn:I Vbiasp:O -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR9_1 Vbiasn -*.PININFO Vbiasn:O -RR1 net05 gnd! res=rK -RRF vdd! Vbiasn res=rK -MM0 Vbiasn Vbiasn net05 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_low_voltage_cascode_pmos -xiLG_pmos Biasn LG_Vbiasp LG_pmos -xibCR9_1 Biasn CR9_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pmos_l1_cr13_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pmos_l1_cr13_1.sp deleted file mode 100644 index 02b11f420a..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pmos_l1_cr13_1.sp +++ /dev/null @@ -1,65 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:08:22 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM7 Voutp Vinn net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM6 net13 Vinp net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM5 net11 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net17 net20 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net13 net17 net19 gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net20 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net19 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_low_voltage_cascode_pmos -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR13_2 Biasn Biasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pmos_l1_cr13_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pmos_l1_cr13_2.sp deleted file mode 100644 index 02b11f420a..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pmos_l1_cr13_2.sp +++ /dev/null @@ -1,65 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:08:22 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM7 Voutp Vinn net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM6 net13 Vinp net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM5 net11 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net17 net20 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net13 net17 net19 gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net20 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net19 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_low_voltage_cascode_pmos -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR13_2 Biasn Biasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pmos_l1_cr14_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pmos_l1_cr14_2.sp deleted file mode 100644 index 53b676fb4b..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pmos_l1_cr14_2.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:08:22 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM7 Voutp Vinn net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM6 net13 Vinp net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM5 net11 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net17 net20 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net13 net17 net19 gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net20 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net19 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR14_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net010 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 Vbiasn net010 res=rK -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_low_voltage_cascode_pmos -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR14_2 Biasn Biasp CR14_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pmos_l1_cr15_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pmos_l1_cr15_1.sp deleted file mode 100644 index eadd809ade..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pmos_l1_cr15_1.sp +++ /dev/null @@ -1,63 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:08:22 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM7 Voutp Vinn net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM6 net13 Vinp net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM5 net11 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net17 net20 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net13 net17 net19 gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net20 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net19 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR15_1 Vbiasp -*.PININFO Vbiasp:O -RR1 Vbiasp gnd! res=rK -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_low_voltage_cascode_pmos -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR15_1 Biasp CR15_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pmos_l1_cr16_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pmos_l1_cr16_1.sp deleted file mode 100644 index 596252c943..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pmos_l1_cr16_1.sp +++ /dev/null @@ -1,64 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:08:22 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM7 Voutp Vinn net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM6 net13 Vinp net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM5 net11 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net17 net20 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net13 net17 net19 gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net20 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net19 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR16_1 Vbiasp -*.PININFO Vbiasp:O -RR0 vdd! net6 res=rK -RR1 Vbiasp gnd! res=rK -MM2 Vbiasp Vbiasp net6 vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_low_voltage_cascode_pmos -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR16_1 Biasp CR16_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pmos_l1_cr2_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pmos_l1_cr2_2.sp deleted file mode 100644 index e197d946fa..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pmos_l1_cr2_2.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:08:22 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM7 Voutp Vinn net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM6 net13 Vinp net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM5 net11 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net17 net20 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net13 net17 net19 gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net20 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net19 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR2_2_wilson Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -RR0 Vbiasn gnd! res=rK -MM2 Vbiasp net12 Vbiasn gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_low_voltage_cascode_pmos -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR2_2_wilson Biasn Biasp CR2_2_wilson -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pmos_l1_cr3_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pmos_l1_cr3_2.sp deleted file mode 100644 index f98e34e1f9..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pmos_l1_cr3_2.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:08:22 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM7 Voutp Vinn net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM6 net13 Vinp net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM5 net11 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net17 net20 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net13 net17 net19 gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net20 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net19 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR3_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 net15 gnd! res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_low_voltage_cascode_pmos -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR3_2 Biasn Biasp CR3_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pmos_l1_cr4_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pmos_l1_cr4_2.sp deleted file mode 100644 index 46849b3376..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pmos_l1_cr4_2.sp +++ /dev/null @@ -1,71 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:08:22 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM7 Voutp Vinn net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM6 net13 Vinp net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM5 net11 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net17 net20 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net13 net17 net19 gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net20 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net19 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR4_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM11 net023 net024 Vbiasn gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM8 net025 net010 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM9 net024 net024 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM7 net010 net010 net025 gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net025 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 net024 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net010 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_low_voltage_cascode_pmos -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR4_2 Biasn Biasp CR4_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pmos_l1_cr5_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pmos_l1_cr5_2.sp deleted file mode 100644 index 097b829087..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pmos_l1_cr5_2.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:08:22 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM7 Voutp Vinn net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM6 net13 Vinp net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM5 net11 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net17 net20 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net13 net17 net19 gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net20 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net19 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR5_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM5 net014 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net014 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_low_voltage_cascode_pmos -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR5_2 Biasn Biasp CR5_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pmos_l1_cr6_3.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pmos_l1_cr6_3.sp deleted file mode 100644 index 4c4094f7f3..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pmos_l1_cr6_3.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:08:22 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM7 Voutp Vinn net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM6 net13 Vinp net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM5 net11 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net17 net20 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net13 net17 net19 gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net20 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net19 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR6_3 Vbiasn1 Vbiasn2 Vbiasp -*.PININFO Vbiasn1:O Vbiasn2:O Vbiasp:O -MM2 Vbiasp Vbiasn2 Vbiasn1 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn2 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 Vbiasn1 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM5 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn2 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_low_voltage_cascode_pmos -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR6_3 Biasn1 Biasn2 Biasp CR6_3 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pnmos_4_cr13_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pnmos_4_cr13_1.sp deleted file mode 100644 index fee5cf54f3..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pnmos_4_cr13_1.sp +++ /dev/null @@ -1,67 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:08:22 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM7 Voutp Vinn net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM6 net13 Vinp net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM5 net11 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net17 net20 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net13 net17 net19 gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net20 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net19 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_low_voltage_cascode_pmos -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR13_2 Biasn Biasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pnmos_4_cr13_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pnmos_4_cr13_2.sp deleted file mode 100644 index fee5cf54f3..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pnmos_4_cr13_2.sp +++ /dev/null @@ -1,67 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:08:22 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM7 Voutp Vinn net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM6 net13 Vinp net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM5 net11 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net17 net20 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net13 net17 net19 gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net20 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net19 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_low_voltage_cascode_pmos -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR13_2 Biasn Biasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pnmos_4_cr14_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pnmos_4_cr14_2.sp deleted file mode 100644 index 4b5ac347e0..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pnmos_4_cr14_2.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:08:22 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM7 Voutp Vinn net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM6 net13 Vinp net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM5 net11 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net17 net20 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net13 net17 net19 gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net20 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net19 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR14_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net010 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 Vbiasn net010 res=rK -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_low_voltage_cascode_pmos -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR14_2 Biasn Biasp CR14_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pnmos_4_cr15_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pnmos_4_cr15_1.sp deleted file mode 100644 index e07b52241c..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pnmos_4_cr15_1.sp +++ /dev/null @@ -1,65 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:08:22 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM7 Voutp Vinn net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM6 net13 Vinp net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM5 net11 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net17 net20 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net13 net17 net19 gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net20 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net19 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR15_1 Vbiasp -*.PININFO Vbiasp:O -RR1 Vbiasp gnd! res=rK -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_low_voltage_cascode_pmos -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR15_1 Biasp CR15_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pnmos_4_cr16_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pnmos_4_cr16_1.sp deleted file mode 100644 index 2648ac676a..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pnmos_4_cr16_1.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:08:22 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM7 Voutp Vinn net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM6 net13 Vinp net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM5 net11 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net17 net20 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net13 net17 net19 gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net20 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net19 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR16_1 Vbiasp -*.PININFO Vbiasp:O -RR0 vdd! net6 res=rK -RR1 Vbiasp gnd! res=rK -MM2 Vbiasp Vbiasp net6 vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_low_voltage_cascode_pmos -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR16_1 Biasp CR16_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pnmos_4_cr2_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pnmos_4_cr2_2.sp deleted file mode 100644 index a4b4fc4d95..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pnmos_4_cr2_2.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:08:22 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM7 Voutp Vinn net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM6 net13 Vinp net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM5 net11 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net17 net20 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net13 net17 net19 gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net20 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net19 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR2_2_wilson Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -RR0 Vbiasn gnd! res=rK -MM2 Vbiasp net12 Vbiasn gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_low_voltage_cascode_pmos -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR2_2_wilson Biasn Biasp CR2_2_wilson -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pnmos_4_cr3_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pnmos_4_cr3_2.sp deleted file mode 100644 index 20a548ebc5..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pnmos_4_cr3_2.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:08:22 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM7 Voutp Vinn net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM6 net13 Vinp net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM5 net11 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net17 net20 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net13 net17 net19 gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net20 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net19 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR3_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 net15 gnd! res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_low_voltage_cascode_pmos -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR3_2 Biasn Biasp CR3_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pnmos_4_cr4_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pnmos_4_cr4_2.sp deleted file mode 100644 index 876ced7c17..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pnmos_4_cr4_2.sp +++ /dev/null @@ -1,73 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:08:22 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM7 Voutp Vinn net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM6 net13 Vinp net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM5 net11 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net17 net20 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net13 net17 net19 gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net20 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net19 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR4_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM11 net023 net024 Vbiasn gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM8 net025 net010 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM9 net024 net024 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM7 net010 net010 net025 gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net025 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 net024 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net010 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_low_voltage_cascode_pmos -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR4_2 Biasn Biasp CR4_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pnmos_4_cr5_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pnmos_4_cr5_2.sp deleted file mode 100644 index cac4c4c9c9..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pnmos_4_cr5_2.sp +++ /dev/null @@ -1,70 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:08:22 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM7 Voutp Vinn net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM6 net13 Vinp net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM5 net11 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net17 net20 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net13 net17 net19 gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net20 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net19 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR5_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM5 net014 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net014 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_low_voltage_cascode_pmos -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR5_2 Biasn Biasp CR5_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pnmos_4_cr6_3.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pnmos_4_cr6_3.sp deleted file mode 100644 index 02c78892f2..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pnmos_4_cr6_3.sp +++ /dev/null @@ -1,70 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:08:22 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM7 Voutp Vinn net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM6 net13 Vinp net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM5 net11 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net17 net20 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net13 net17 net19 gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net20 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net19 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR6_3 Vbiasn1 Vbiasn2 Vbiasp -*.PININFO Vbiasn1:O Vbiasn2:O Vbiasp:O -MM2 Vbiasp Vbiasn2 Vbiasn1 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn2 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 Vbiasn1 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM5 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn2 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_low_voltage_cascode_pmos -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR6_3 Biasn1 Biasn2 Biasp CR6_3 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pnmos_cr13_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pnmos_cr13_1.sp deleted file mode 100644 index 76b3f23195..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pnmos_cr13_1.sp +++ /dev/null @@ -1,67 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:08:22 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM7 Voutp Vinn net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM6 net13 Vinp net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM5 net11 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net17 net20 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net13 net17 net19 gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net20 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net19 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_low_voltage_cascode_pmos -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR13_2 Biasn Biasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pnmos_cr13_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pnmos_cr13_2.sp deleted file mode 100644 index 76b3f23195..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pnmos_cr13_2.sp +++ /dev/null @@ -1,67 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:08:22 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM7 Voutp Vinn net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM6 net13 Vinp net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM5 net11 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net17 net20 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net13 net17 net19 gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net20 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net19 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_low_voltage_cascode_pmos -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR13_2 Biasn Biasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pnmos_cr14_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pnmos_cr14_2.sp deleted file mode 100644 index 5cec39640e..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pnmos_cr14_2.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:08:22 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM7 Voutp Vinn net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM6 net13 Vinp net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM5 net11 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net17 net20 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net13 net17 net19 gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net20 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net19 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR14_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net010 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 Vbiasn net010 res=rK -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_low_voltage_cascode_pmos -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR14_2 Biasn Biasp CR14_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pnmos_cr15_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pnmos_cr15_1.sp deleted file mode 100644 index 87f7c49a54..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pnmos_cr15_1.sp +++ /dev/null @@ -1,65 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:08:22 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM7 Voutp Vinn net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM6 net13 Vinp net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM5 net11 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net17 net20 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net13 net17 net19 gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net20 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net19 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR15_1 Vbiasp -*.PININFO Vbiasp:O -RR1 Vbiasp gnd! res=rK -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_low_voltage_cascode_pmos -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR15_1 Biasp CR15_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pnmos_cr16_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pnmos_cr16_1.sp deleted file mode 100644 index 8f3ee3afc4..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pnmos_cr16_1.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:08:22 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM7 Voutp Vinn net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM6 net13 Vinp net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM5 net11 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net17 net20 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net13 net17 net19 gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net20 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net19 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR16_1 Vbiasp -*.PININFO Vbiasp:O -RR0 vdd! net6 res=rK -RR1 Vbiasp gnd! res=rK -MM2 Vbiasp Vbiasp net6 vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_low_voltage_cascode_pmos -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR16_1 Biasp CR16_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pnmos_cr2_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pnmos_cr2_2.sp deleted file mode 100644 index 944e27dd5c..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pnmos_cr2_2.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:08:22 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM7 Voutp Vinn net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM6 net13 Vinp net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM5 net11 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net17 net20 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net13 net17 net19 gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net20 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net19 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR2_2_wilson Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -RR0 Vbiasn gnd! res=rK -MM2 Vbiasp net12 Vbiasn gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_low_voltage_cascode_pmos -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR2_2_wilson Biasn Biasp CR2_2_wilson -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pnmos_cr3_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pnmos_cr3_2.sp deleted file mode 100644 index c13bc49e2e..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pnmos_cr3_2.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:08:22 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM7 Voutp Vinn net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM6 net13 Vinp net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM5 net11 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net17 net20 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net13 net17 net19 gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net20 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net19 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR3_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 net15 gnd! res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_low_voltage_cascode_pmos -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR3_2 Biasn Biasp CR3_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pnmos_cr4_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pnmos_cr4_2.sp deleted file mode 100644 index 1ff572583f..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pnmos_cr4_2.sp +++ /dev/null @@ -1,73 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:08:22 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM7 Voutp Vinn net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM6 net13 Vinp net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM5 net11 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net17 net20 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net13 net17 net19 gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net20 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net19 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR4_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM11 net023 net024 Vbiasn gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM8 net025 net010 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM9 net024 net024 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM7 net010 net010 net025 gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net025 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 net024 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net010 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_low_voltage_cascode_pmos -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR4_2 Biasn Biasp CR4_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pnmos_cr5_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pnmos_cr5_2.sp deleted file mode 100644 index 6202873f12..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pnmos_cr5_2.sp +++ /dev/null @@ -1,70 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:08:22 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM7 Voutp Vinn net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM6 net13 Vinp net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM5 net11 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net17 net20 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net13 net17 net19 gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net20 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net19 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR5_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM5 net014 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net014 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_low_voltage_cascode_pmos -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR5_2 Biasn Biasp CR5_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pnmos_cr6_3.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pnmos_cr6_3.sp deleted file mode 100644 index ce5cf34569..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_low_voltage_cascode_pmos_LG_pnmos_cr6_3.sp +++ /dev/null @@ -1,70 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:08:22 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM7 Voutp Vinn net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM6 net13 Vinp net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM5 net11 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net17 net20 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net13 net17 net19 gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net20 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net19 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR6_3 Vbiasn1 Vbiasn2 Vbiasp -*.PININFO Vbiasn1:O Vbiasn2:O Vbiasp:O -MM2 Vbiasp Vbiasn2 Vbiasn1 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn2 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 Vbiasn1 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM5 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn2 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_low_voltage_cascode_pmos -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR6_3 Biasn1 Biasn2 Biasp CR6_3 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_nmos_cr13_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_nmos_cr13_1.sp deleted file mode 100644 index fb2af9f595..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_nmos_cr13_1.sp +++ /dev/null @@ -1,64 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:08:39 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net011 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net07 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 net011 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net07 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net011 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -CC0 Voutn net011 1p $[CP] -.ENDS - - -.SUBCKT LG_nmos Biasp Vbiasn -*.PININFO Biasp:I Vbiasn:O -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_miller_compensated -xiLG_nmos Biasp LG_Vbiasn LG_nmos -xibCR13_2 Biasn Biasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_nmos_cr13_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_nmos_cr13_2.sp deleted file mode 100644 index fb2af9f595..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_nmos_cr13_2.sp +++ /dev/null @@ -1,64 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:08:39 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net011 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net07 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 net011 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net07 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net011 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -CC0 Voutn net011 1p $[CP] -.ENDS - - -.SUBCKT LG_nmos Biasp Vbiasn -*.PININFO Biasp:I Vbiasn:O -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_miller_compensated -xiLG_nmos Biasp LG_Vbiasn LG_nmos -xibCR13_2 Biasn Biasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_nmos_cr14_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_nmos_cr14_2.sp deleted file mode 100644 index 0cd86192c6..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_nmos_cr14_2.sp +++ /dev/null @@ -1,65 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:08:39 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net011 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net07 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 net011 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net07 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net011 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -CC0 Voutn net011 1p $[CP] -.ENDS - - -.SUBCKT LG_nmos Biasp Vbiasn -*.PININFO Biasp:I Vbiasn:O -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR14_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net010 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 Vbiasn net010 res=rK -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_miller_compensated -xiLG_nmos Biasp LG_Vbiasn LG_nmos -xibCR14_2 Biasn Biasp CR14_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_nmos_cr15_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_nmos_cr15_1.sp deleted file mode 100644 index 56178c4fcd..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_nmos_cr15_1.sp +++ /dev/null @@ -1,62 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:08:39 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net011 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net07 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 net011 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net07 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net011 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -CC0 Voutn net011 1p $[CP] -.ENDS - - -.SUBCKT LG_nmos Biasp Vbiasn -*.PININFO Biasp:I Vbiasn:O -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR15_1 Vbiasp -*.PININFO Vbiasp:O -RR1 Vbiasp gnd! res=rK -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_miller_compensated -xiLG_nmos Biasp LG_Vbiasn LG_nmos -xibCR15_1 Biasp CR15_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_nmos_cr16_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_nmos_cr16_1.sp deleted file mode 100644 index 4cf9332612..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_nmos_cr16_1.sp +++ /dev/null @@ -1,63 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:08:39 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net011 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net07 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 net011 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net07 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net011 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -CC0 Voutn net011 1p $[CP] -.ENDS - - -.SUBCKT LG_nmos Biasp Vbiasn -*.PININFO Biasp:I Vbiasn:O -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR16_1 Vbiasp -*.PININFO Vbiasp:O -RR0 vdd! net6 res=rK -RR1 Vbiasp gnd! res=rK -MM2 Vbiasp Vbiasp net6 vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_miller_compensated -xiLG_nmos Biasp LG_Vbiasn LG_nmos -xibCR16_1 Biasp CR16_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_nmos_cr2_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_nmos_cr2_2.sp deleted file mode 100644 index 3555d2c83a..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_nmos_cr2_2.sp +++ /dev/null @@ -1,65 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:08:39 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net011 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net07 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 net011 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net07 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net011 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -CC0 Voutn net011 1p $[CP] -.ENDS - - -.SUBCKT LG_nmos Biasp Vbiasn -*.PININFO Biasp:I Vbiasn:O -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR2_2_wilson Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -RR0 Vbiasn gnd! res=rK -MM2 Vbiasp net12 Vbiasn gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_miller_compensated -xiLG_nmos Biasp LG_Vbiasn LG_nmos -xibCR2_2_wilson Biasn Biasp CR2_2_wilson -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_nmos_cr3_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_nmos_cr3_2.sp deleted file mode 100644 index 44f4712afc..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_nmos_cr3_2.sp +++ /dev/null @@ -1,65 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:08:39 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net011 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net07 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 net011 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net07 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net011 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -CC0 Voutn net011 1p $[CP] -.ENDS - - -.SUBCKT LG_nmos Biasp Vbiasn -*.PININFO Biasp:I Vbiasn:O -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR3_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 net15 gnd! res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_miller_compensated -xiLG_nmos Biasp LG_Vbiasn LG_nmos -xibCR3_2 Biasn Biasp CR3_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_nmos_cr4_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_nmos_cr4_2.sp deleted file mode 100644 index f96be47ad4..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_nmos_cr4_2.sp +++ /dev/null @@ -1,70 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:08:39 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net011 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net07 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 net011 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net07 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net011 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -CC0 Voutn net011 1p $[CP] -.ENDS - - -.SUBCKT LG_nmos Biasp Vbiasn -*.PININFO Biasp:I Vbiasn:O -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR4_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM11 net023 net024 Vbiasn gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM8 net025 net010 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM9 net024 net024 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM7 net010 net010 net025 gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net025 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 net024 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net010 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_miller_compensated -xiLG_nmos Biasp LG_Vbiasn LG_nmos -xibCR4_2 Biasn Biasp CR4_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_nmos_cr5_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_nmos_cr5_2.sp deleted file mode 100644 index 7ed9eb9dc5..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_nmos_cr5_2.sp +++ /dev/null @@ -1,67 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:08:39 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net011 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net07 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 net011 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net07 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net011 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -CC0 Voutn net011 1p $[CP] -.ENDS - - -.SUBCKT LG_nmos Biasp Vbiasn -*.PININFO Biasp:I Vbiasn:O -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR5_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM5 net014 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net014 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_miller_compensated -xiLG_nmos Biasp LG_Vbiasn LG_nmos -xibCR5_2 Biasn Biasp CR5_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_nmos_cr6_3.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_nmos_cr6_3.sp deleted file mode 100644 index 380ce894cf..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_nmos_cr6_3.sp +++ /dev/null @@ -1,67 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:08:39 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net011 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net07 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 net011 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net07 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net011 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -CC0 Voutn net011 1p $[CP] -.ENDS - - -.SUBCKT LG_nmos Biasp Vbiasn -*.PININFO Biasp:I Vbiasn:O -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR6_3 Vbiasn1 Vbiasn2 Vbiasp -*.PININFO Vbiasn1:O Vbiasn2:O Vbiasp:O -MM2 Vbiasp Vbiasn2 Vbiasn1 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn2 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 Vbiasn1 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM5 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn2 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_miller_compensated -xiLG_nmos Biasp LG_Vbiasn LG_nmos -xibCR6_3 Biasn1 Biasn2 Biasp CR6_3 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_nmos_l1_cr11_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_nmos_l1_cr11_1.sp deleted file mode 100644 index c4d4a91b5c..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_nmos_l1_cr11_1.sp +++ /dev/null @@ -1,67 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:08:39 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net011 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net07 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 net011 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net07 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net011 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -CC0 Voutn net011 1p $[CP] -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR11_1 Vbiasn -*.PININFO Vbiasn:O -RRF vdd! Vbiasn res=rK -MM1 net9 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net9 net9 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn net9 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_miller_compensated -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR11_1 Biasn CR11_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_nmos_l1_cr12_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_nmos_l1_cr12_1.sp deleted file mode 100644 index 1c5afae67b..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_nmos_l1_cr12_1.sp +++ /dev/null @@ -1,67 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:08:39 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net011 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net07 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 net011 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net07 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net011 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -CC0 Voutn net011 1p $[CP] -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR12_1 Vbiasn -*.PININFO Vbiasn:O -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 net10 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn net10 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RRF vdd! Vbiasn res=rK -RR0 vdd! net10 res=rK -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_miller_compensated -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR12_1 Biasn CR12_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_nmos_l1_cr13_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_nmos_l1_cr13_1.sp deleted file mode 100644 index f164bcb6c8..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_nmos_l1_cr13_1.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:08:39 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net011 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net07 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 net011 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net07 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net011 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -CC0 Voutn net011 1p $[CP] -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_miller_compensated -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR13_2 Biasn Vbiasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_nmos_l1_cr13_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_nmos_l1_cr13_2.sp deleted file mode 100644 index f164bcb6c8..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_nmos_l1_cr13_2.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:08:39 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net011 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net07 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 net011 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net07 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net011 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -CC0 Voutn net011 1p $[CP] -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_miller_compensated -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR13_2 Biasn Vbiasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_nmos_l1_cr14_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_nmos_l1_cr14_2.sp deleted file mode 100644 index 634766486b..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_nmos_l1_cr14_2.sp +++ /dev/null @@ -1,67 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:08:39 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net011 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net07 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 net011 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net07 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net011 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -CC0 Voutn net011 1p $[CP] -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR14_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net010 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 Vbiasn net010 res=rK -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_miller_compensated -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR14_2 Biasn Vbiasp CR14_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_nmos_l1_cr1_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_nmos_l1_cr1_1.sp deleted file mode 100644 index 4762feefc2..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_nmos_l1_cr1_1.sp +++ /dev/null @@ -1,64 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:08:39 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net011 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net07 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 net011 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net07 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net011 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -CC0 Voutn net011 1p $[CP] -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR1_1 Vbiasn -*.PININFO Vbiasn:O -RRF vdd! Vbiasn res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_miller_compensated -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR1_1 Biasn CR1_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_nmos_l1_cr2_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_nmos_l1_cr2_2.sp deleted file mode 100644 index 2e345beeda..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_nmos_l1_cr2_2.sp +++ /dev/null @@ -1,67 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:08:39 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net011 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net07 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 net011 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net07 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net011 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -CC0 Voutn net011 1p $[CP] -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR2_2_wilson Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -RR0 Vbiasn gnd! res=rK -MM2 Vbiasp net12 Vbiasn gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_miller_compensated -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR2_2_wilson Biasn Vbiasp CR2_2_wilson -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_nmos_l1_cr3_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_nmos_l1_cr3_2.sp deleted file mode 100644 index e8e2da574f..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_nmos_l1_cr3_2.sp +++ /dev/null @@ -1,67 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:08:39 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net011 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net07 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 net011 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net07 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net011 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -CC0 Voutn net011 1p $[CP] -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR3_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 net15 gnd! res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_miller_compensated -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR3_2 Biasn Vbiasp CR3_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_nmos_l1_cr4_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_nmos_l1_cr4_2.sp deleted file mode 100644 index e3e17fe83d..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_nmos_l1_cr4_2.sp +++ /dev/null @@ -1,72 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:08:39 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net011 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net07 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 net011 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net07 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net011 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -CC0 Voutn net011 1p $[CP] -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR4_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM11 net023 net024 Vbiasn gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM8 net025 net010 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM9 net024 net024 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM7 net010 net010 net025 gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net025 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 net024 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net010 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_miller_compensated -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR4_2 Biasn Vbiasp CR4_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_nmos_l1_cr5_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_nmos_l1_cr5_2.sp deleted file mode 100644 index 3b7b162b2c..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_nmos_l1_cr5_2.sp +++ /dev/null @@ -1,69 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:08:39 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net011 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net07 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 net011 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net07 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net011 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -CC0 Voutn net011 1p $[CP] -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR5_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM5 net014 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net014 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_miller_compensated -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR5_2 Biasn Vbiasp CR5_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_nmos_l1_cr7_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_nmos_l1_cr7_1.sp deleted file mode 100644 index 51e2f59139..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_nmos_l1_cr7_1.sp +++ /dev/null @@ -1,67 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:08:39 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net011 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net07 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 net011 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net07 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net011 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -CC0 Voutn net011 1p $[CP] -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR7_1 Vbiasn -*.PININFO Vbiasn:O -RR1 Vbiasn net7 res=rK -RR0 vdd! net7 res=rK -RRF vdd! Vbiasn res=rK -MM1 net7 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_miller_compensated -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR7_1 Biasn CR7_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_nmos_l1_cr9_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_nmos_l1_cr9_1.sp deleted file mode 100644 index f9049338be..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_nmos_l1_cr9_1.sp +++ /dev/null @@ -1,65 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:08:39 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net011 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net07 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 net011 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net07 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net011 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -CC0 Voutn net011 1p $[CP] -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR9_1 Vbiasn -*.PININFO Vbiasn:O -RR1 net05 gnd! res=rK -RRF vdd! Vbiasn res=rK -MM0 Vbiasn Vbiasn net05 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_miller_compensated -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR9_1 Biasn CR9_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_npmos_cr11_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_npmos_cr11_1.sp deleted file mode 100644 index c9642f8b9b..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_npmos_cr11_1.sp +++ /dev/null @@ -1,69 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:08:39 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net011 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net07 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 net011 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net07 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net011 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -CC0 Voutn net011 1p $[CP] -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR11_1 Vbiasn -*.PININFO Vbiasn:O -RRF vdd! Vbiasn res=rK -MM1 net9 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net9 net9 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn net9 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_miller_compensated -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR11_1 Biasn CR11_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_npmos_cr12_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_npmos_cr12_1.sp deleted file mode 100644 index 652da48c48..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_npmos_cr12_1.sp +++ /dev/null @@ -1,69 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:08:39 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net011 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net07 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 net011 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net07 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net011 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -CC0 Voutn net011 1p $[CP] -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR12_1 Vbiasn -*.PININFO Vbiasn:O -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 net10 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn net10 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RRF vdd! Vbiasn res=rK -RR0 vdd! net10 res=rK -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_miller_compensated -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR12_1 Biasn CR12_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_npmos_cr13_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_npmos_cr13_1.sp deleted file mode 100644 index 4272ff3389..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_npmos_cr13_1.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:08:39 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net011 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net07 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 net011 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net07 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net011 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -CC0 Voutn net011 1p $[CP] -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_miller_compensated -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR13_2 Biasn Vbiasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_npmos_cr13_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_npmos_cr13_2.sp deleted file mode 100644 index 4272ff3389..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_npmos_cr13_2.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:08:39 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net011 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net07 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 net011 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net07 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net011 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -CC0 Voutn net011 1p $[CP] -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_miller_compensated -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR13_2 Biasn Vbiasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_npmos_cr14_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_npmos_cr14_2.sp deleted file mode 100644 index e9867958fc..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_npmos_cr14_2.sp +++ /dev/null @@ -1,69 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:08:39 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net011 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net07 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 net011 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net07 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net011 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -CC0 Voutn net011 1p $[CP] -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR14_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net010 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 Vbiasn net010 res=rK -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_miller_compensated -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR14_2 Biasn Vbiasp CR14_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_npmos_cr1_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_npmos_cr1_1.sp deleted file mode 100644 index a5bb08c341..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_npmos_cr1_1.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:08:39 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net011 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net07 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 net011 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net07 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net011 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -CC0 Voutn net011 1p $[CP] -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR1_1 Vbiasn -*.PININFO Vbiasn:O -RRF vdd! Vbiasn res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_miller_compensated -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR1_1 Biasn CR1_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_npmos_cr2_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_npmos_cr2_2.sp deleted file mode 100644 index db0abf1523..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_npmos_cr2_2.sp +++ /dev/null @@ -1,69 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:08:39 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net011 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net07 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 net011 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net07 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net011 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -CC0 Voutn net011 1p $[CP] -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR2_2_wilson Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -RR0 Vbiasn gnd! res=rK -MM2 Vbiasp net12 Vbiasn gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_miller_compensated -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR2_2_wilson Biasn Vbiasp CR2_2_wilson -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_npmos_cr3_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_npmos_cr3_2.sp deleted file mode 100644 index 01c4c7c679..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_npmos_cr3_2.sp +++ /dev/null @@ -1,69 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:08:39 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net011 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net07 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 net011 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net07 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net011 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -CC0 Voutn net011 1p $[CP] -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR3_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 net15 gnd! res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_miller_compensated -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR3_2 Biasn Vbiasp CR3_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_npmos_cr4_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_npmos_cr4_2.sp deleted file mode 100644 index 10266b868f..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_npmos_cr4_2.sp +++ /dev/null @@ -1,74 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:08:39 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net011 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net07 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 net011 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net07 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net011 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -CC0 Voutn net011 1p $[CP] -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR4_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM11 net023 net024 Vbiasn gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM8 net025 net010 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM9 net024 net024 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM7 net010 net010 net025 gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net025 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 net024 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net010 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_miller_compensated -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR4_2 Biasn Vbiasp CR4_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_npmos_cr5_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_npmos_cr5_2.sp deleted file mode 100644 index 9d2cb2263d..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_npmos_cr5_2.sp +++ /dev/null @@ -1,71 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:08:39 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net011 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net07 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 net011 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net07 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net011 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -CC0 Voutn net011 1p $[CP] -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR5_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM5 net014 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net014 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_miller_compensated -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR5_2 Biasn Vbiasp CR5_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_npmos_cr7_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_npmos_cr7_1.sp deleted file mode 100644 index 69e021fc0e..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_npmos_cr7_1.sp +++ /dev/null @@ -1,69 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:08:39 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net011 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net07 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 net011 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net07 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net011 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -CC0 Voutn net011 1p $[CP] -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR7_1 Vbiasn -*.PININFO Vbiasn:O -RR1 Vbiasn net7 res=rK -RR0 vdd! net7 res=rK -RRF vdd! Vbiasn res=rK -MM1 net7 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_miller_compensated -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR7_1 Biasn CR7_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_npmos_cr9_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_npmos_cr9_1.sp deleted file mode 100644 index 1a6acf1cf9..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_npmos_cr9_1.sp +++ /dev/null @@ -1,67 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:08:39 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net011 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net07 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 net011 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net07 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net011 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -CC0 Voutn net011 1p $[CP] -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR9_1 Vbiasn -*.PININFO Vbiasn:O -RR1 net05 gnd! res=rK -RRF vdd! Vbiasn res=rK -MM0 Vbiasn Vbiasn net05 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_miller_compensated -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR9_1 Biasn CR9_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_pmos_l1_cr13_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_pmos_l1_cr13_1.sp deleted file mode 100644 index 6469520042..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_pmos_l1_cr13_1.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:08:39 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net011 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net07 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 net011 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net07 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net011 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -CC0 Voutn net011 1p $[CP] -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_miller_compensated -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR13_2 Biasn Biasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_pmos_l1_cr13_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_pmos_l1_cr13_2.sp deleted file mode 100644 index 6469520042..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_pmos_l1_cr13_2.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:08:39 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net011 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net07 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 net011 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net07 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net011 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -CC0 Voutn net011 1p $[CP] -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_miller_compensated -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR13_2 Biasn Biasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_pmos_l1_cr14_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_pmos_l1_cr14_2.sp deleted file mode 100644 index c566c2a919..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_pmos_l1_cr14_2.sp +++ /dev/null @@ -1,67 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:08:39 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net011 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net07 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 net011 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net07 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net011 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -CC0 Voutn net011 1p $[CP] -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR14_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net010 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 Vbiasn net010 res=rK -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_miller_compensated -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR14_2 Biasn Biasp CR14_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_pmos_l1_cr15_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_pmos_l1_cr15_1.sp deleted file mode 100644 index 44f8e3c3e9..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_pmos_l1_cr15_1.sp +++ /dev/null @@ -1,64 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:08:39 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net011 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net07 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 net011 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net07 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net011 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -CC0 Voutn net011 1p $[CP] -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR15_1 Vbiasp -*.PININFO Vbiasp:O -RR1 Vbiasp gnd! res=rK -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_miller_compensated -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR15_1 Biasp CR15_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_pmos_l1_cr16_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_pmos_l1_cr16_1.sp deleted file mode 100644 index 789a0a14b5..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_pmos_l1_cr16_1.sp +++ /dev/null @@ -1,65 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:08:39 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net011 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net07 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 net011 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net07 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net011 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -CC0 Voutn net011 1p $[CP] -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR16_1 Vbiasp -*.PININFO Vbiasp:O -RR0 vdd! net6 res=rK -RR1 Vbiasp gnd! res=rK -MM2 Vbiasp Vbiasp net6 vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_miller_compensated -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR16_1 Biasp CR16_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_pmos_l1_cr2_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_pmos_l1_cr2_2.sp deleted file mode 100644 index 0051ec9c05..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_pmos_l1_cr2_2.sp +++ /dev/null @@ -1,67 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:08:39 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net011 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net07 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 net011 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net07 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net011 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -CC0 Voutn net011 1p $[CP] -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR2_2_wilson Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -RR0 Vbiasn gnd! res=rK -MM2 Vbiasp net12 Vbiasn gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_miller_compensated -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR2_2_wilson Biasn Biasp CR2_2_wilson -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_pmos_l1_cr3_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_pmos_l1_cr3_2.sp deleted file mode 100644 index d6171d9b66..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_pmos_l1_cr3_2.sp +++ /dev/null @@ -1,67 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:08:39 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net011 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net07 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 net011 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net07 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net011 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -CC0 Voutn net011 1p $[CP] -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR3_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 net15 gnd! res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_miller_compensated -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR3_2 Biasn Biasp CR3_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_pmos_l1_cr4_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_pmos_l1_cr4_2.sp deleted file mode 100644 index b1b081b099..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_pmos_l1_cr4_2.sp +++ /dev/null @@ -1,72 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:08:39 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net011 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net07 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 net011 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net07 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net011 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -CC0 Voutn net011 1p $[CP] -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR4_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM11 net023 net024 Vbiasn gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM8 net025 net010 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM9 net024 net024 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM7 net010 net010 net025 gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net025 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 net024 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net010 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_miller_compensated -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR4_2 Biasn Biasp CR4_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_pmos_l1_cr5_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_pmos_l1_cr5_2.sp deleted file mode 100644 index a3d49d77b0..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_pmos_l1_cr5_2.sp +++ /dev/null @@ -1,69 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:08:39 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net011 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net07 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 net011 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net07 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net011 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -CC0 Voutn net011 1p $[CP] -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR5_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM5 net014 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net014 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_miller_compensated -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR5_2 Biasn Biasp CR5_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_pmos_l1_cr6_3.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_pmos_l1_cr6_3.sp deleted file mode 100644 index aa511961b3..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_pmos_l1_cr6_3.sp +++ /dev/null @@ -1,69 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:08:39 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net011 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net07 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 net011 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net07 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net011 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -CC0 Voutn net011 1p $[CP] -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR6_3 Vbiasn1 Vbiasn2 Vbiasp -*.PININFO Vbiasn1:O Vbiasn2:O Vbiasp:O -MM2 Vbiasp Vbiasn2 Vbiasn1 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn2 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 Vbiasn1 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM5 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn2 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_miller_compensated -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR6_3 Biasn1 Biasn2 Biasp CR6_3 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_pnmos_4_cr13_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_pnmos_4_cr13_1.sp deleted file mode 100644 index d106e8704a..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_pnmos_4_cr13_1.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:08:39 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net011 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net07 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 net011 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net07 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net011 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -CC0 Voutn net011 1p $[CP] -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_miller_compensated -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR13_2 Biasn Biasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_pnmos_4_cr13_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_pnmos_4_cr13_2.sp deleted file mode 100644 index d106e8704a..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_pnmos_4_cr13_2.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:08:39 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net011 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net07 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 net011 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net07 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net011 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -CC0 Voutn net011 1p $[CP] -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_miller_compensated -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR13_2 Biasn Biasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_pnmos_4_cr14_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_pnmos_4_cr14_2.sp deleted file mode 100644 index c50fbb821b..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_pnmos_4_cr14_2.sp +++ /dev/null @@ -1,69 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:08:39 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net011 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net07 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 net011 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net07 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net011 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -CC0 Voutn net011 1p $[CP] -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR14_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net010 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 Vbiasn net010 res=rK -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_miller_compensated -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR14_2 Biasn Biasp CR14_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_pnmos_4_cr15_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_pnmos_4_cr15_1.sp deleted file mode 100644 index 7b80ec5663..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_pnmos_4_cr15_1.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:08:39 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net011 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net07 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 net011 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net07 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net011 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -CC0 Voutn net011 1p $[CP] -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR15_1 Vbiasp -*.PININFO Vbiasp:O -RR1 Vbiasp gnd! res=rK -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_miller_compensated -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR15_1 Biasp CR15_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_pnmos_4_cr16_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_pnmos_4_cr16_1.sp deleted file mode 100644 index d70d3a0ffa..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_pnmos_4_cr16_1.sp +++ /dev/null @@ -1,67 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:08:39 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net011 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net07 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 net011 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net07 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net011 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -CC0 Voutn net011 1p $[CP] -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR16_1 Vbiasp -*.PININFO Vbiasp:O -RR0 vdd! net6 res=rK -RR1 Vbiasp gnd! res=rK -MM2 Vbiasp Vbiasp net6 vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_miller_compensated -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR16_1 Biasp CR16_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_pnmos_4_cr2_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_pnmos_4_cr2_2.sp deleted file mode 100644 index 5def58305a..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_pnmos_4_cr2_2.sp +++ /dev/null @@ -1,69 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:08:39 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net011 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net07 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 net011 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net07 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net011 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -CC0 Voutn net011 1p $[CP] -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR2_2_wilson Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -RR0 Vbiasn gnd! res=rK -MM2 Vbiasp net12 Vbiasn gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_miller_compensated -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR2_2_wilson Biasn Biasp CR2_2_wilson -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_pnmos_4_cr3_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_pnmos_4_cr3_2.sp deleted file mode 100644 index 9984e45810..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_pnmos_4_cr3_2.sp +++ /dev/null @@ -1,69 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:08:39 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net011 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net07 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 net011 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net07 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net011 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -CC0 Voutn net011 1p $[CP] -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR3_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 net15 gnd! res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_miller_compensated -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR3_2 Biasn Biasp CR3_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_pnmos_4_cr4_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_pnmos_4_cr4_2.sp deleted file mode 100644 index 5a836800ad..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_pnmos_4_cr4_2.sp +++ /dev/null @@ -1,74 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:08:39 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net011 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net07 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 net011 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net07 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net011 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -CC0 Voutn net011 1p $[CP] -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR4_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM11 net023 net024 Vbiasn gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM8 net025 net010 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM9 net024 net024 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM7 net010 net010 net025 gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net025 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 net024 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net010 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_miller_compensated -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR4_2 Biasn Biasp CR4_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_pnmos_4_cr5_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_pnmos_4_cr5_2.sp deleted file mode 100644 index bd76cf2878..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_pnmos_4_cr5_2.sp +++ /dev/null @@ -1,71 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:08:39 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net011 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net07 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 net011 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net07 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net011 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -CC0 Voutn net011 1p $[CP] -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR5_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM5 net014 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net014 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_miller_compensated -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR5_2 Biasn Biasp CR5_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_pnmos_4_cr6_3.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_pnmos_4_cr6_3.sp deleted file mode 100644 index c4fe3b9eff..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_pnmos_4_cr6_3.sp +++ /dev/null @@ -1,71 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:08:39 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net011 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net07 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 net011 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net07 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net011 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -CC0 Voutn net011 1p $[CP] -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR6_3 Vbiasn1 Vbiasn2 Vbiasp -*.PININFO Vbiasn1:O Vbiasn2:O Vbiasp:O -MM2 Vbiasp Vbiasn2 Vbiasn1 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn2 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 Vbiasn1 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM5 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn2 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_miller_compensated -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR6_3 Biasn1 Biasn2 Biasp CR6_3 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_pnmos_cr13_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_pnmos_cr13_1.sp deleted file mode 100644 index b8998ed9e0..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_pnmos_cr13_1.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:08:39 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net011 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net07 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 net011 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net07 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net011 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -CC0 Voutn net011 1p $[CP] -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_miller_compensated -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR13_2 Biasn Biasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_pnmos_cr13_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_pnmos_cr13_2.sp deleted file mode 100644 index b8998ed9e0..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_pnmos_cr13_2.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:08:39 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net011 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net07 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 net011 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net07 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net011 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -CC0 Voutn net011 1p $[CP] -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_miller_compensated -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR13_2 Biasn Biasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_pnmos_cr14_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_pnmos_cr14_2.sp deleted file mode 100644 index fc5d0ede9d..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_pnmos_cr14_2.sp +++ /dev/null @@ -1,69 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:08:39 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net011 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net07 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 net011 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net07 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net011 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -CC0 Voutn net011 1p $[CP] -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR14_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net010 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 Vbiasn net010 res=rK -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_miller_compensated -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR14_2 Biasn Biasp CR14_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_pnmos_cr15_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_pnmos_cr15_1.sp deleted file mode 100644 index c8becc0f2e..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_pnmos_cr15_1.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:08:39 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net011 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net07 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 net011 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net07 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net011 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -CC0 Voutn net011 1p $[CP] -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR15_1 Vbiasp -*.PININFO Vbiasp:O -RR1 Vbiasp gnd! res=rK -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_miller_compensated -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR15_1 Biasp CR15_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_pnmos_cr16_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_pnmos_cr16_1.sp deleted file mode 100644 index 231ed46c84..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_pnmos_cr16_1.sp +++ /dev/null @@ -1,67 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:08:39 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net011 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net07 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 net011 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net07 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net011 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -CC0 Voutn net011 1p $[CP] -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR16_1 Vbiasp -*.PININFO Vbiasp:O -RR0 vdd! net6 res=rK -RR1 Vbiasp gnd! res=rK -MM2 Vbiasp Vbiasp net6 vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_miller_compensated -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR16_1 Biasp CR16_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_pnmos_cr2_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_pnmos_cr2_2.sp deleted file mode 100644 index df79a9b7dc..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_pnmos_cr2_2.sp +++ /dev/null @@ -1,69 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:08:39 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net011 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net07 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 net011 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net07 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net011 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -CC0 Voutn net011 1p $[CP] -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR2_2_wilson Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -RR0 Vbiasn gnd! res=rK -MM2 Vbiasp net12 Vbiasn gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_miller_compensated -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR2_2_wilson Biasn Biasp CR2_2_wilson -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_pnmos_cr3_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_pnmos_cr3_2.sp deleted file mode 100644 index 536117d5de..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_pnmos_cr3_2.sp +++ /dev/null @@ -1,69 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:08:39 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net011 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net07 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 net011 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net07 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net011 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -CC0 Voutn net011 1p $[CP] -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR3_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 net15 gnd! res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_miller_compensated -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR3_2 Biasn Biasp CR3_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_pnmos_cr4_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_pnmos_cr4_2.sp deleted file mode 100644 index ae81d52b74..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_pnmos_cr4_2.sp +++ /dev/null @@ -1,74 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:08:39 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net011 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net07 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 net011 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net07 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net011 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -CC0 Voutn net011 1p $[CP] -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR4_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM11 net023 net024 Vbiasn gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM8 net025 net010 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM9 net024 net024 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM7 net010 net010 net025 gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net025 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 net024 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net010 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_miller_compensated -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR4_2 Biasn Biasp CR4_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_pnmos_cr5_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_pnmos_cr5_2.sp deleted file mode 100644 index 95b8fb8c3b..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_pnmos_cr5_2.sp +++ /dev/null @@ -1,71 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:08:39 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net011 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net07 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 net011 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net07 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net011 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -CC0 Voutn net011 1p $[CP] -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR5_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM5 net014 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net014 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_miller_compensated -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR5_2 Biasn Biasp CR5_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_pnmos_cr6_3.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_pnmos_cr6_3.sp deleted file mode 100644 index 17142a9c51..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_LG_pnmos_cr6_3.sp +++ /dev/null @@ -1,71 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:08:39 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net011 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net07 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 net011 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net07 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net011 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -CC0 Voutn net011 1p $[CP] -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR6_3 Vbiasn1 Vbiasn2 Vbiasp -*.PININFO Vbiasn1:O Vbiasn2:O Vbiasp:O -MM2 Vbiasp Vbiasn2 Vbiasn1 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn2 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 Vbiasn1 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM5 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn2 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutn single_ended_miller_compensated -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR6_3 Biasn1 Biasn2 Biasp CR6_3 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_nmos_l1_cr11_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_nmos_l1_cr11_1.sp deleted file mode 100644 index 94ead9f18d..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_nmos_l1_cr11_1.sp +++ /dev/null @@ -1,67 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:34 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM13 Voutp net38 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net38 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net35 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM12 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM11 net33 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net38 Vinn net33 net39 pmos_rvt w=WA l=LA nfin=nA -MM7 net35 Vinp net33 net39 pmos_rvt w=WA l=LA nfin=nA -CC2 Voutp net38 1p $[CP] -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR11_1 Vbiasn -*.PININFO Vbiasn:O -RRF vdd! Vbiasn res=rK -MM1 net9 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net9 net9 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn net9 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_miller_compensated_pmos -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR11_1 Biasn CR11_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_nmos_l1_cr12_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_nmos_l1_cr12_1.sp deleted file mode 100644 index 415a0f930b..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_nmos_l1_cr12_1.sp +++ /dev/null @@ -1,67 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:34 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM13 Voutp net38 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net38 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net35 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM12 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM11 net33 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net38 Vinn net33 net39 pmos_rvt w=WA l=LA nfin=nA -MM7 net35 Vinp net33 net39 pmos_rvt w=WA l=LA nfin=nA -CC2 Voutp net38 1p $[CP] -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR12_1 Vbiasn -*.PININFO Vbiasn:O -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 net10 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn net10 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RRF vdd! Vbiasn res=rK -RR0 vdd! net10 res=rK -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_miller_compensated_pmos -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR12_1 Biasn CR12_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_nmos_l1_cr13_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_nmos_l1_cr13_1.sp deleted file mode 100644 index 2633d6987a..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_nmos_l1_cr13_1.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:34 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM13 Voutp net38 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net38 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net35 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM12 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM11 net33 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net38 Vinn net33 net39 pmos_rvt w=WA l=LA nfin=nA -MM7 net35 Vinp net33 net39 pmos_rvt w=WA l=LA nfin=nA -CC2 Voutp net38 1p $[CP] -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_miller_compensated_pmos -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR13_2 Biasn Vbiasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_nmos_l1_cr13_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_nmos_l1_cr13_2.sp deleted file mode 100644 index 2633d6987a..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_nmos_l1_cr13_2.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:34 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM13 Voutp net38 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net38 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net35 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM12 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM11 net33 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net38 Vinn net33 net39 pmos_rvt w=WA l=LA nfin=nA -MM7 net35 Vinp net33 net39 pmos_rvt w=WA l=LA nfin=nA -CC2 Voutp net38 1p $[CP] -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_miller_compensated_pmos -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR13_2 Biasn Vbiasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_nmos_l1_cr14_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_nmos_l1_cr14_2.sp deleted file mode 100644 index ef771f5164..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_nmos_l1_cr14_2.sp +++ /dev/null @@ -1,67 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:34 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM13 Voutp net38 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net38 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net35 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM12 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM11 net33 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net38 Vinn net33 net39 pmos_rvt w=WA l=LA nfin=nA -MM7 net35 Vinp net33 net39 pmos_rvt w=WA l=LA nfin=nA -CC2 Voutp net38 1p $[CP] -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR14_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net010 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 Vbiasn net010 res=rK -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_miller_compensated_pmos -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR14_2 Biasn Vbiasp CR14_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_nmos_l1_cr1_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_nmos_l1_cr1_1.sp deleted file mode 100644 index 80cfd080e6..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_nmos_l1_cr1_1.sp +++ /dev/null @@ -1,64 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:34 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM13 Voutp net38 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net38 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net35 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM12 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM11 net33 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net38 Vinn net33 net39 pmos_rvt w=WA l=LA nfin=nA -MM7 net35 Vinp net33 net39 pmos_rvt w=WA l=LA nfin=nA -CC2 Voutp net38 1p $[CP] -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR1_1 Vbiasn -*.PININFO Vbiasn:O -RRF vdd! Vbiasn res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_miller_compensated_pmos -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR1_1 Biasn CR1_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_nmos_l1_cr2_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_nmos_l1_cr2_2.sp deleted file mode 100644 index ae6afcb173..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_nmos_l1_cr2_2.sp +++ /dev/null @@ -1,67 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:34 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM13 Voutp net38 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net38 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net35 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM12 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM11 net33 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net38 Vinn net33 net39 pmos_rvt w=WA l=LA nfin=nA -MM7 net35 Vinp net33 net39 pmos_rvt w=WA l=LA nfin=nA -CC2 Voutp net38 1p $[CP] -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR2_2_wilson Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -RR0 Vbiasn gnd! res=rK -MM2 Vbiasp net12 Vbiasn gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_miller_compensated_pmos -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR2_2_wilson Biasn Vbiasp CR2_2_wilson -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_nmos_l1_cr3_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_nmos_l1_cr3_2.sp deleted file mode 100644 index 5365f044e4..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_nmos_l1_cr3_2.sp +++ /dev/null @@ -1,67 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:34 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM13 Voutp net38 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net38 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net35 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM12 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM11 net33 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net38 Vinn net33 net39 pmos_rvt w=WA l=LA nfin=nA -MM7 net35 Vinp net33 net39 pmos_rvt w=WA l=LA nfin=nA -CC2 Voutp net38 1p $[CP] -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR3_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 net15 gnd! res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_miller_compensated_pmos -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR3_2 Biasn Vbiasp CR3_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_nmos_l1_cr4_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_nmos_l1_cr4_2.sp deleted file mode 100644 index 54f4997b49..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_nmos_l1_cr4_2.sp +++ /dev/null @@ -1,72 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:34 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM13 Voutp net38 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net38 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net35 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM12 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM11 net33 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net38 Vinn net33 net39 pmos_rvt w=WA l=LA nfin=nA -MM7 net35 Vinp net33 net39 pmos_rvt w=WA l=LA nfin=nA -CC2 Voutp net38 1p $[CP] -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR4_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM11 net023 net024 Vbiasn gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM8 net025 net010 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM9 net024 net024 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM7 net010 net010 net025 gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net025 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 net024 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net010 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_miller_compensated_pmos -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR4_2 Biasn Vbiasp CR4_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_nmos_l1_cr5_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_nmos_l1_cr5_2.sp deleted file mode 100644 index 5614d3b0cd..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_nmos_l1_cr5_2.sp +++ /dev/null @@ -1,69 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:34 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM13 Voutp net38 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net38 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net35 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM12 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM11 net33 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net38 Vinn net33 net39 pmos_rvt w=WA l=LA nfin=nA -MM7 net35 Vinp net33 net39 pmos_rvt w=WA l=LA nfin=nA -CC2 Voutp net38 1p $[CP] -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR5_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM5 net014 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net014 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_miller_compensated_pmos -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR5_2 Biasn Vbiasp CR5_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_nmos_l1_cr7_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_nmos_l1_cr7_1.sp deleted file mode 100644 index bbb53fbbf0..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_nmos_l1_cr7_1.sp +++ /dev/null @@ -1,67 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:34 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM13 Voutp net38 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net38 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net35 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM12 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM11 net33 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net38 Vinn net33 net39 pmos_rvt w=WA l=LA nfin=nA -MM7 net35 Vinp net33 net39 pmos_rvt w=WA l=LA nfin=nA -CC2 Voutp net38 1p $[CP] -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR7_1 Vbiasn -*.PININFO Vbiasn:O -RR1 Vbiasn net7 res=rK -RR0 vdd! net7 res=rK -RRF vdd! Vbiasn res=rK -MM1 net7 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_miller_compensated_pmos -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR7_1 Biasn CR7_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_nmos_l1_cr9_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_nmos_l1_cr9_1.sp deleted file mode 100644 index d1d8253ca5..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_nmos_l1_cr9_1.sp +++ /dev/null @@ -1,65 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:34 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM13 Voutp net38 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net38 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net35 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM12 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM11 net33 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net38 Vinn net33 net39 pmos_rvt w=WA l=LA nfin=nA -MM7 net35 Vinp net33 net39 pmos_rvt w=WA l=LA nfin=nA -CC2 Voutp net38 1p $[CP] -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR9_1 Vbiasn -*.PININFO Vbiasn:O -RR1 net05 gnd! res=rK -RRF vdd! Vbiasn res=rK -MM0 Vbiasn Vbiasn net05 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_miller_compensated_pmos -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR9_1 Biasn CR9_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_npmos_cr11_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_npmos_cr11_1.sp deleted file mode 100644 index 1a4c50b02e..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_npmos_cr11_1.sp +++ /dev/null @@ -1,69 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:34 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM13 Voutp net38 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net38 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net35 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM12 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM11 net33 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net38 Vinn net33 net39 pmos_rvt w=WA l=LA nfin=nA -MM7 net35 Vinp net33 net39 pmos_rvt w=WA l=LA nfin=nA -CC2 Voutp net38 1p $[CP] -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR11_1 Vbiasn -*.PININFO Vbiasn:O -RRF vdd! Vbiasn res=rK -MM1 net9 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net9 net9 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn net9 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_miller_compensated_pmos -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR11_1 Biasn CR11_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_npmos_cr12_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_npmos_cr12_1.sp deleted file mode 100644 index 21c45ed82b..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_npmos_cr12_1.sp +++ /dev/null @@ -1,69 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:34 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM13 Voutp net38 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net38 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net35 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM12 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM11 net33 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net38 Vinn net33 net39 pmos_rvt w=WA l=LA nfin=nA -MM7 net35 Vinp net33 net39 pmos_rvt w=WA l=LA nfin=nA -CC2 Voutp net38 1p $[CP] -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR12_1 Vbiasn -*.PININFO Vbiasn:O -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 net10 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn net10 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RRF vdd! Vbiasn res=rK -RR0 vdd! net10 res=rK -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_miller_compensated_pmos -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR12_1 Biasn CR12_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_npmos_cr13_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_npmos_cr13_1.sp deleted file mode 100644 index 1c661d2564..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_npmos_cr13_1.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:34 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM13 Voutp net38 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net38 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net35 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM12 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM11 net33 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net38 Vinn net33 net39 pmos_rvt w=WA l=LA nfin=nA -MM7 net35 Vinp net33 net39 pmos_rvt w=WA l=LA nfin=nA -CC2 Voutp net38 1p $[CP] -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_miller_compensated_pmos -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR13_2 Biasn Vbiasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_npmos_cr13_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_npmos_cr13_2.sp deleted file mode 100644 index 1c661d2564..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_npmos_cr13_2.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:34 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM13 Voutp net38 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net38 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net35 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM12 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM11 net33 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net38 Vinn net33 net39 pmos_rvt w=WA l=LA nfin=nA -MM7 net35 Vinp net33 net39 pmos_rvt w=WA l=LA nfin=nA -CC2 Voutp net38 1p $[CP] -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_miller_compensated_pmos -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR13_2 Biasn Vbiasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_npmos_cr14_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_npmos_cr14_2.sp deleted file mode 100644 index 5efca349b7..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_npmos_cr14_2.sp +++ /dev/null @@ -1,69 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:34 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM13 Voutp net38 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net38 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net35 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM12 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM11 net33 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net38 Vinn net33 net39 pmos_rvt w=WA l=LA nfin=nA -MM7 net35 Vinp net33 net39 pmos_rvt w=WA l=LA nfin=nA -CC2 Voutp net38 1p $[CP] -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR14_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net010 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 Vbiasn net010 res=rK -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_miller_compensated_pmos -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR14_2 Biasn Vbiasp CR14_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_npmos_cr1_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_npmos_cr1_1.sp deleted file mode 100644 index 44ae4e1c3e..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_npmos_cr1_1.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:34 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM13 Voutp net38 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net38 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net35 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM12 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM11 net33 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net38 Vinn net33 net39 pmos_rvt w=WA l=LA nfin=nA -MM7 net35 Vinp net33 net39 pmos_rvt w=WA l=LA nfin=nA -CC2 Voutp net38 1p $[CP] -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR1_1 Vbiasn -*.PININFO Vbiasn:O -RRF vdd! Vbiasn res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_miller_compensated_pmos -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR1_1 Biasn CR1_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_npmos_cr2_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_npmos_cr2_2.sp deleted file mode 100644 index 4330b9ee6c..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_npmos_cr2_2.sp +++ /dev/null @@ -1,69 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:34 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM13 Voutp net38 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net38 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net35 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM12 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM11 net33 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net38 Vinn net33 net39 pmos_rvt w=WA l=LA nfin=nA -MM7 net35 Vinp net33 net39 pmos_rvt w=WA l=LA nfin=nA -CC2 Voutp net38 1p $[CP] -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR2_2_wilson Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -RR0 Vbiasn gnd! res=rK -MM2 Vbiasp net12 Vbiasn gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_miller_compensated_pmos -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR2_2_wilson Biasn Vbiasp CR2_2_wilson -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_npmos_cr3_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_npmos_cr3_2.sp deleted file mode 100644 index 696818d5d3..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_npmos_cr3_2.sp +++ /dev/null @@ -1,69 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:34 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM13 Voutp net38 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net38 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net35 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM12 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM11 net33 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net38 Vinn net33 net39 pmos_rvt w=WA l=LA nfin=nA -MM7 net35 Vinp net33 net39 pmos_rvt w=WA l=LA nfin=nA -CC2 Voutp net38 1p $[CP] -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR3_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 net15 gnd! res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_miller_compensated_pmos -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR3_2 Biasn Vbiasp CR3_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_npmos_cr4_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_npmos_cr4_2.sp deleted file mode 100644 index 86ad08368d..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_npmos_cr4_2.sp +++ /dev/null @@ -1,74 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:34 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM13 Voutp net38 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net38 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net35 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM12 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM11 net33 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net38 Vinn net33 net39 pmos_rvt w=WA l=LA nfin=nA -MM7 net35 Vinp net33 net39 pmos_rvt w=WA l=LA nfin=nA -CC2 Voutp net38 1p $[CP] -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR4_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM11 net023 net024 Vbiasn gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM8 net025 net010 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM9 net024 net024 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM7 net010 net010 net025 gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net025 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 net024 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net010 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_miller_compensated_pmos -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR4_2 Biasn Vbiasp CR4_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_npmos_cr5_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_npmos_cr5_2.sp deleted file mode 100644 index 199f85d5df..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_npmos_cr5_2.sp +++ /dev/null @@ -1,71 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:34 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM13 Voutp net38 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net38 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net35 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM12 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM11 net33 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net38 Vinn net33 net39 pmos_rvt w=WA l=LA nfin=nA -MM7 net35 Vinp net33 net39 pmos_rvt w=WA l=LA nfin=nA -CC2 Voutp net38 1p $[CP] -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR5_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM5 net014 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net014 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_miller_compensated_pmos -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR5_2 Biasn Vbiasp CR5_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_npmos_cr7_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_npmos_cr7_1.sp deleted file mode 100644 index 33dd2aef8c..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_npmos_cr7_1.sp +++ /dev/null @@ -1,69 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:34 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM13 Voutp net38 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net38 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net35 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM12 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM11 net33 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net38 Vinn net33 net39 pmos_rvt w=WA l=LA nfin=nA -MM7 net35 Vinp net33 net39 pmos_rvt w=WA l=LA nfin=nA -CC2 Voutp net38 1p $[CP] -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR7_1 Vbiasn -*.PININFO Vbiasn:O -RR1 Vbiasn net7 res=rK -RR0 vdd! net7 res=rK -RRF vdd! Vbiasn res=rK -MM1 net7 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_miller_compensated_pmos -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR7_1 Biasn CR7_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_npmos_cr9_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_npmos_cr9_1.sp deleted file mode 100644 index f738e780d9..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_npmos_cr9_1.sp +++ /dev/null @@ -1,67 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:34 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM13 Voutp net38 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net38 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net35 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM12 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM11 net33 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net38 Vinn net33 net39 pmos_rvt w=WA l=LA nfin=nA -MM7 net35 Vinp net33 net39 pmos_rvt w=WA l=LA nfin=nA -CC2 Voutp net38 1p $[CP] -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR9_1 Vbiasn -*.PININFO Vbiasn:O -RR1 net05 gnd! res=rK -RRF vdd! Vbiasn res=rK -MM0 Vbiasn Vbiasn net05 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_miller_compensated_pmos -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR9_1 Biasn CR9_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pmos_cr11_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pmos_cr11_1.sp deleted file mode 100644 index 586cd5f02b..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pmos_cr11_1.sp +++ /dev/null @@ -1,65 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:34 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM13 Voutp net38 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net38 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net35 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM12 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM11 net33 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net38 Vinn net33 net39 pmos_rvt w=WA l=LA nfin=nA -MM7 net35 Vinp net33 net39 pmos_rvt w=WA l=LA nfin=nA -CC2 Voutp net38 1p $[CP] -.ENDS - - -.SUBCKT LG_pmos Biasn Vbiasp -*.PININFO Biasn:I Vbiasp:O -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR11_1 Vbiasn -*.PININFO Vbiasn:O -RRF vdd! Vbiasn res=rK -MM1 net9 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net9 net9 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn net9 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_miller_compensated_pmos -xiLG_pmos Biasn LG_Vbiasp LG_pmos -xibCR11_1 Biasn CR11_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pmos_cr12_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pmos_cr12_1.sp deleted file mode 100644 index 9336fa07db..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pmos_cr12_1.sp +++ /dev/null @@ -1,65 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:34 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM13 Voutp net38 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net38 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net35 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM12 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM11 net33 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net38 Vinn net33 net39 pmos_rvt w=WA l=LA nfin=nA -MM7 net35 Vinp net33 net39 pmos_rvt w=WA l=LA nfin=nA -CC2 Voutp net38 1p $[CP] -.ENDS - - -.SUBCKT LG_pmos Biasn Vbiasp -*.PININFO Biasn:I Vbiasp:O -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR12_1 Vbiasn -*.PININFO Vbiasn:O -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 net10 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn net10 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RRF vdd! Vbiasn res=rK -RR0 vdd! net10 res=rK -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_miller_compensated_pmos -xiLG_pmos Biasn LG_Vbiasp LG_pmos -xibCR12_1 Biasn CR12_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pmos_cr13_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pmos_cr13_1.sp deleted file mode 100644 index 35950563b4..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pmos_cr13_1.sp +++ /dev/null @@ -1,64 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:34 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM13 Voutp net38 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net38 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net35 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM12 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM11 net33 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net38 Vinn net33 net39 pmos_rvt w=WA l=LA nfin=nA -MM7 net35 Vinp net33 net39 pmos_rvt w=WA l=LA nfin=nA -CC2 Voutp net38 1p $[CP] -.ENDS - - -.SUBCKT LG_pmos Biasn Vbiasp -*.PININFO Biasn:I Vbiasp:O -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_miller_compensated_pmos -xiLG_pmos Biasn LG_Vbiasp LG_pmos -xibCR13_2 Biasn Vbiasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pmos_cr13_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pmos_cr13_2.sp deleted file mode 100644 index 35950563b4..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pmos_cr13_2.sp +++ /dev/null @@ -1,64 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:34 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM13 Voutp net38 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net38 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net35 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM12 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM11 net33 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net38 Vinn net33 net39 pmos_rvt w=WA l=LA nfin=nA -MM7 net35 Vinp net33 net39 pmos_rvt w=WA l=LA nfin=nA -CC2 Voutp net38 1p $[CP] -.ENDS - - -.SUBCKT LG_pmos Biasn Vbiasp -*.PININFO Biasn:I Vbiasp:O -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_miller_compensated_pmos -xiLG_pmos Biasn LG_Vbiasp LG_pmos -xibCR13_2 Biasn Vbiasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pmos_cr14_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pmos_cr14_2.sp deleted file mode 100644 index d6e43d0963..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pmos_cr14_2.sp +++ /dev/null @@ -1,65 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:34 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM13 Voutp net38 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net38 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net35 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM12 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM11 net33 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net38 Vinn net33 net39 pmos_rvt w=WA l=LA nfin=nA -MM7 net35 Vinp net33 net39 pmos_rvt w=WA l=LA nfin=nA -CC2 Voutp net38 1p $[CP] -.ENDS - - -.SUBCKT LG_pmos Biasn Vbiasp -*.PININFO Biasn:I Vbiasp:O -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR14_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net010 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 Vbiasn net010 res=rK -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_miller_compensated_pmos -xiLG_pmos Biasn LG_Vbiasp LG_pmos -xibCR14_2 Biasn Vbiasp CR14_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pmos_cr1_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pmos_cr1_1.sp deleted file mode 100644 index be98cfc023..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pmos_cr1_1.sp +++ /dev/null @@ -1,62 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:34 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM13 Voutp net38 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net38 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net35 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM12 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM11 net33 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net38 Vinn net33 net39 pmos_rvt w=WA l=LA nfin=nA -MM7 net35 Vinp net33 net39 pmos_rvt w=WA l=LA nfin=nA -CC2 Voutp net38 1p $[CP] -.ENDS - - -.SUBCKT LG_pmos Biasn Vbiasp -*.PININFO Biasn:I Vbiasp:O -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR1_1 Vbiasn -*.PININFO Vbiasn:O -RRF vdd! Vbiasn res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_miller_compensated_pmos -xiLG_pmos Biasn LG_Vbiasp LG_pmos -xibCR1_1 Biasn CR1_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pmos_cr2_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pmos_cr2_2.sp deleted file mode 100644 index a22a14259c..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pmos_cr2_2.sp +++ /dev/null @@ -1,65 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:34 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM13 Voutp net38 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net38 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net35 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM12 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM11 net33 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net38 Vinn net33 net39 pmos_rvt w=WA l=LA nfin=nA -MM7 net35 Vinp net33 net39 pmos_rvt w=WA l=LA nfin=nA -CC2 Voutp net38 1p $[CP] -.ENDS - - -.SUBCKT LG_pmos Biasn Vbiasp -*.PININFO Biasn:I Vbiasp:O -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR2_2_wilson Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -RR0 Vbiasn gnd! res=rK -MM2 Vbiasp net12 Vbiasn gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_miller_compensated_pmos -xiLG_pmos Biasn LG_Vbiasp LG_pmos -xibCR2_2_wilson Biasn Vbiasp CR2_2_wilson -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pmos_cr3_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pmos_cr3_2.sp deleted file mode 100644 index 9fd0c2be2b..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pmos_cr3_2.sp +++ /dev/null @@ -1,65 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:34 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM13 Voutp net38 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net38 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net35 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM12 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM11 net33 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net38 Vinn net33 net39 pmos_rvt w=WA l=LA nfin=nA -MM7 net35 Vinp net33 net39 pmos_rvt w=WA l=LA nfin=nA -CC2 Voutp net38 1p $[CP] -.ENDS - - -.SUBCKT LG_pmos Biasn Vbiasp -*.PININFO Biasn:I Vbiasp:O -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR3_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 net15 gnd! res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_miller_compensated_pmos -xiLG_pmos Biasn LG_Vbiasp LG_pmos -xibCR3_2 Biasn Vbiasp CR3_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pmos_cr4_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pmos_cr4_2.sp deleted file mode 100644 index 32ae75e4ff..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pmos_cr4_2.sp +++ /dev/null @@ -1,70 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:34 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM13 Voutp net38 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net38 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net35 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM12 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM11 net33 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net38 Vinn net33 net39 pmos_rvt w=WA l=LA nfin=nA -MM7 net35 Vinp net33 net39 pmos_rvt w=WA l=LA nfin=nA -CC2 Voutp net38 1p $[CP] -.ENDS - - -.SUBCKT LG_pmos Biasn Vbiasp -*.PININFO Biasn:I Vbiasp:O -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR4_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM11 net023 net024 Vbiasn gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM8 net025 net010 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM9 net024 net024 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM7 net010 net010 net025 gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net025 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 net024 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net010 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_miller_compensated_pmos -xiLG_pmos Biasn LG_Vbiasp LG_pmos -xibCR4_2 Biasn Vbiasp CR4_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pmos_cr5_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pmos_cr5_2.sp deleted file mode 100644 index a43b74e965..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pmos_cr5_2.sp +++ /dev/null @@ -1,67 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:34 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM13 Voutp net38 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net38 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net35 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM12 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM11 net33 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net38 Vinn net33 net39 pmos_rvt w=WA l=LA nfin=nA -MM7 net35 Vinp net33 net39 pmos_rvt w=WA l=LA nfin=nA -CC2 Voutp net38 1p $[CP] -.ENDS - - -.SUBCKT LG_pmos Biasn Vbiasp -*.PININFO Biasn:I Vbiasp:O -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR5_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM5 net014 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net014 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_miller_compensated_pmos -xiLG_pmos Biasn LG_Vbiasp LG_pmos -xibCR5_2 Biasn Vbiasp CR5_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pmos_cr7_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pmos_cr7_1.sp deleted file mode 100644 index 2febd91254..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pmos_cr7_1.sp +++ /dev/null @@ -1,65 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:34 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM13 Voutp net38 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net38 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net35 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM12 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM11 net33 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net38 Vinn net33 net39 pmos_rvt w=WA l=LA nfin=nA -MM7 net35 Vinp net33 net39 pmos_rvt w=WA l=LA nfin=nA -CC2 Voutp net38 1p $[CP] -.ENDS - - -.SUBCKT LG_pmos Biasn Vbiasp -*.PININFO Biasn:I Vbiasp:O -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR7_1 Vbiasn -*.PININFO Vbiasn:O -RR1 Vbiasn net7 res=rK -RR0 vdd! net7 res=rK -RRF vdd! Vbiasn res=rK -MM1 net7 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_miller_compensated_pmos -xiLG_pmos Biasn LG_Vbiasp LG_pmos -xibCR7_1 Biasn CR7_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pmos_cr9_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pmos_cr9_1.sp deleted file mode 100644 index 30fd43953f..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pmos_cr9_1.sp +++ /dev/null @@ -1,63 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:34 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM13 Voutp net38 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net38 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net35 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM12 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM11 net33 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net38 Vinn net33 net39 pmos_rvt w=WA l=LA nfin=nA -MM7 net35 Vinp net33 net39 pmos_rvt w=WA l=LA nfin=nA -CC2 Voutp net38 1p $[CP] -.ENDS - - -.SUBCKT LG_pmos Biasn Vbiasp -*.PININFO Biasn:I Vbiasp:O -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR9_1 Vbiasn -*.PININFO Vbiasn:O -RR1 net05 gnd! res=rK -RRF vdd! Vbiasn res=rK -MM0 Vbiasn Vbiasn net05 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_miller_compensated_pmos -xiLG_pmos Biasn LG_Vbiasp LG_pmos -xibCR9_1 Biasn CR9_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pmos_l1_cr13_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pmos_l1_cr13_1.sp deleted file mode 100644 index eefc905629..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pmos_l1_cr13_1.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:34 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM13 Voutp net38 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net38 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net35 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM12 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM11 net33 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net38 Vinn net33 net39 pmos_rvt w=WA l=LA nfin=nA -MM7 net35 Vinp net33 net39 pmos_rvt w=WA l=LA nfin=nA -CC2 Voutp net38 1p $[CP] -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_miller_compensated_pmos -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR13_2 Biasn Biasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pmos_l1_cr13_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pmos_l1_cr13_2.sp deleted file mode 100644 index eefc905629..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pmos_l1_cr13_2.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:34 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM13 Voutp net38 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net38 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net35 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM12 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM11 net33 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net38 Vinn net33 net39 pmos_rvt w=WA l=LA nfin=nA -MM7 net35 Vinp net33 net39 pmos_rvt w=WA l=LA nfin=nA -CC2 Voutp net38 1p $[CP] -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_miller_compensated_pmos -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR13_2 Biasn Biasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pmos_l1_cr14_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pmos_l1_cr14_2.sp deleted file mode 100644 index 003a7d0285..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pmos_l1_cr14_2.sp +++ /dev/null @@ -1,67 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:34 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM13 Voutp net38 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net38 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net35 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM12 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM11 net33 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net38 Vinn net33 net39 pmos_rvt w=WA l=LA nfin=nA -MM7 net35 Vinp net33 net39 pmos_rvt w=WA l=LA nfin=nA -CC2 Voutp net38 1p $[CP] -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR14_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net010 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 Vbiasn net010 res=rK -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_miller_compensated_pmos -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR14_2 Biasn Biasp CR14_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pmos_l1_cr15_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pmos_l1_cr15_1.sp deleted file mode 100644 index 71f4d87fdf..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pmos_l1_cr15_1.sp +++ /dev/null @@ -1,64 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:34 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM13 Voutp net38 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net38 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net35 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM12 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM11 net33 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net38 Vinn net33 net39 pmos_rvt w=WA l=LA nfin=nA -MM7 net35 Vinp net33 net39 pmos_rvt w=WA l=LA nfin=nA -CC2 Voutp net38 1p $[CP] -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR15_1 Vbiasp -*.PININFO Vbiasp:O -RR1 Vbiasp gnd! res=rK -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_miller_compensated_pmos -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR15_1 Biasp CR15_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pmos_l1_cr16_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pmos_l1_cr16_1.sp deleted file mode 100644 index af16ac3776..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pmos_l1_cr16_1.sp +++ /dev/null @@ -1,65 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:34 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM13 Voutp net38 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net38 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net35 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM12 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM11 net33 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net38 Vinn net33 net39 pmos_rvt w=WA l=LA nfin=nA -MM7 net35 Vinp net33 net39 pmos_rvt w=WA l=LA nfin=nA -CC2 Voutp net38 1p $[CP] -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR16_1 Vbiasp -*.PININFO Vbiasp:O -RR0 vdd! net6 res=rK -RR1 Vbiasp gnd! res=rK -MM2 Vbiasp Vbiasp net6 vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_miller_compensated_pmos -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR16_1 Biasp CR16_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pmos_l1_cr2_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pmos_l1_cr2_2.sp deleted file mode 100644 index e0693f8eac..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pmos_l1_cr2_2.sp +++ /dev/null @@ -1,67 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:34 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM13 Voutp net38 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net38 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net35 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM12 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM11 net33 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net38 Vinn net33 net39 pmos_rvt w=WA l=LA nfin=nA -MM7 net35 Vinp net33 net39 pmos_rvt w=WA l=LA nfin=nA -CC2 Voutp net38 1p $[CP] -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR2_2_wilson Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -RR0 Vbiasn gnd! res=rK -MM2 Vbiasp net12 Vbiasn gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_miller_compensated_pmos -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR2_2_wilson Biasn Biasp CR2_2_wilson -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pmos_l1_cr3_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pmos_l1_cr3_2.sp deleted file mode 100644 index 3c8eddffb6..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pmos_l1_cr3_2.sp +++ /dev/null @@ -1,67 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:34 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM13 Voutp net38 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net38 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net35 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM12 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM11 net33 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net38 Vinn net33 net39 pmos_rvt w=WA l=LA nfin=nA -MM7 net35 Vinp net33 net39 pmos_rvt w=WA l=LA nfin=nA -CC2 Voutp net38 1p $[CP] -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR3_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 net15 gnd! res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_miller_compensated_pmos -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR3_2 Biasn Biasp CR3_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pmos_l1_cr4_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pmos_l1_cr4_2.sp deleted file mode 100644 index 3d2c3aae4e..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pmos_l1_cr4_2.sp +++ /dev/null @@ -1,72 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:34 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM13 Voutp net38 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net38 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net35 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM12 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM11 net33 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net38 Vinn net33 net39 pmos_rvt w=WA l=LA nfin=nA -MM7 net35 Vinp net33 net39 pmos_rvt w=WA l=LA nfin=nA -CC2 Voutp net38 1p $[CP] -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR4_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM11 net023 net024 Vbiasn gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM8 net025 net010 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM9 net024 net024 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM7 net010 net010 net025 gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net025 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 net024 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net010 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_miller_compensated_pmos -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR4_2 Biasn Biasp CR4_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pmos_l1_cr5_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pmos_l1_cr5_2.sp deleted file mode 100644 index 87d273986a..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pmos_l1_cr5_2.sp +++ /dev/null @@ -1,69 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:34 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM13 Voutp net38 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net38 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net35 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM12 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM11 net33 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net38 Vinn net33 net39 pmos_rvt w=WA l=LA nfin=nA -MM7 net35 Vinp net33 net39 pmos_rvt w=WA l=LA nfin=nA -CC2 Voutp net38 1p $[CP] -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR5_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM5 net014 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net014 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_miller_compensated_pmos -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR5_2 Biasn Biasp CR5_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pmos_l1_cr6_3.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pmos_l1_cr6_3.sp deleted file mode 100644 index 3dfeb62cd8..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pmos_l1_cr6_3.sp +++ /dev/null @@ -1,69 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:34 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM13 Voutp net38 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net38 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net35 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM12 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM11 net33 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net38 Vinn net33 net39 pmos_rvt w=WA l=LA nfin=nA -MM7 net35 Vinp net33 net39 pmos_rvt w=WA l=LA nfin=nA -CC2 Voutp net38 1p $[CP] -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR6_3 Vbiasn1 Vbiasn2 Vbiasp -*.PININFO Vbiasn1:O Vbiasn2:O Vbiasp:O -MM2 Vbiasp Vbiasn2 Vbiasn1 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn2 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 Vbiasn1 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM5 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn2 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_miller_compensated_pmos -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR6_3 Biasn1 Biasn2 Biasp CR6_3 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pnmos_4_cr13_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pnmos_4_cr13_1.sp deleted file mode 100644 index 65955cbb6d..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pnmos_4_cr13_1.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:34 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM13 Voutp net38 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net38 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net35 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM12 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM11 net33 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net38 Vinn net33 net39 pmos_rvt w=WA l=LA nfin=nA -MM7 net35 Vinp net33 net39 pmos_rvt w=WA l=LA nfin=nA -CC2 Voutp net38 1p $[CP] -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_miller_compensated_pmos -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR13_2 Biasn Biasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pnmos_4_cr13_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pnmos_4_cr13_2.sp deleted file mode 100644 index 65955cbb6d..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pnmos_4_cr13_2.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:34 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM13 Voutp net38 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net38 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net35 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM12 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM11 net33 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net38 Vinn net33 net39 pmos_rvt w=WA l=LA nfin=nA -MM7 net35 Vinp net33 net39 pmos_rvt w=WA l=LA nfin=nA -CC2 Voutp net38 1p $[CP] -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_miller_compensated_pmos -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR13_2 Biasn Biasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pnmos_4_cr14_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pnmos_4_cr14_2.sp deleted file mode 100644 index fb5443bad7..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pnmos_4_cr14_2.sp +++ /dev/null @@ -1,69 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:34 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM13 Voutp net38 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net38 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net35 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM12 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM11 net33 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net38 Vinn net33 net39 pmos_rvt w=WA l=LA nfin=nA -MM7 net35 Vinp net33 net39 pmos_rvt w=WA l=LA nfin=nA -CC2 Voutp net38 1p $[CP] -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR14_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net010 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 Vbiasn net010 res=rK -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_miller_compensated_pmos -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR14_2 Biasn Biasp CR14_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pnmos_4_cr15_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pnmos_4_cr15_1.sp deleted file mode 100644 index a43e388903..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pnmos_4_cr15_1.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:34 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM13 Voutp net38 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net38 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net35 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM12 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM11 net33 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net38 Vinn net33 net39 pmos_rvt w=WA l=LA nfin=nA -MM7 net35 Vinp net33 net39 pmos_rvt w=WA l=LA nfin=nA -CC2 Voutp net38 1p $[CP] -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR15_1 Vbiasp -*.PININFO Vbiasp:O -RR1 Vbiasp gnd! res=rK -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_miller_compensated_pmos -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR15_1 Biasp CR15_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pnmos_4_cr16_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pnmos_4_cr16_1.sp deleted file mode 100644 index abdf8fa12b..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pnmos_4_cr16_1.sp +++ /dev/null @@ -1,67 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:34 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM13 Voutp net38 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net38 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net35 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM12 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM11 net33 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net38 Vinn net33 net39 pmos_rvt w=WA l=LA nfin=nA -MM7 net35 Vinp net33 net39 pmos_rvt w=WA l=LA nfin=nA -CC2 Voutp net38 1p $[CP] -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR16_1 Vbiasp -*.PININFO Vbiasp:O -RR0 vdd! net6 res=rK -RR1 Vbiasp gnd! res=rK -MM2 Vbiasp Vbiasp net6 vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_miller_compensated_pmos -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR16_1 Biasp CR16_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pnmos_4_cr2_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pnmos_4_cr2_2.sp deleted file mode 100644 index a0678ed919..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pnmos_4_cr2_2.sp +++ /dev/null @@ -1,69 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:34 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM13 Voutp net38 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net38 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net35 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM12 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM11 net33 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net38 Vinn net33 net39 pmos_rvt w=WA l=LA nfin=nA -MM7 net35 Vinp net33 net39 pmos_rvt w=WA l=LA nfin=nA -CC2 Voutp net38 1p $[CP] -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR2_2_wilson Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -RR0 Vbiasn gnd! res=rK -MM2 Vbiasp net12 Vbiasn gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_miller_compensated_pmos -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR2_2_wilson Biasn Biasp CR2_2_wilson -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pnmos_4_cr3_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pnmos_4_cr3_2.sp deleted file mode 100644 index 2271a91001..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pnmos_4_cr3_2.sp +++ /dev/null @@ -1,69 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:34 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM13 Voutp net38 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net38 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net35 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM12 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM11 net33 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net38 Vinn net33 net39 pmos_rvt w=WA l=LA nfin=nA -MM7 net35 Vinp net33 net39 pmos_rvt w=WA l=LA nfin=nA -CC2 Voutp net38 1p $[CP] -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR3_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 net15 gnd! res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_miller_compensated_pmos -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR3_2 Biasn Biasp CR3_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pnmos_4_cr4_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pnmos_4_cr4_2.sp deleted file mode 100644 index 577d8ba493..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pnmos_4_cr4_2.sp +++ /dev/null @@ -1,74 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:34 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM13 Voutp net38 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net38 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net35 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM12 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM11 net33 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net38 Vinn net33 net39 pmos_rvt w=WA l=LA nfin=nA -MM7 net35 Vinp net33 net39 pmos_rvt w=WA l=LA nfin=nA -CC2 Voutp net38 1p $[CP] -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR4_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM11 net023 net024 Vbiasn gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM8 net025 net010 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM9 net024 net024 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM7 net010 net010 net025 gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net025 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 net024 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net010 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_miller_compensated_pmos -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR4_2 Biasn Biasp CR4_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pnmos_4_cr5_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pnmos_4_cr5_2.sp deleted file mode 100644 index 600184ee78..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pnmos_4_cr5_2.sp +++ /dev/null @@ -1,71 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:34 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM13 Voutp net38 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net38 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net35 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM12 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM11 net33 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net38 Vinn net33 net39 pmos_rvt w=WA l=LA nfin=nA -MM7 net35 Vinp net33 net39 pmos_rvt w=WA l=LA nfin=nA -CC2 Voutp net38 1p $[CP] -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR5_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM5 net014 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net014 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_miller_compensated_pmos -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR5_2 Biasn Biasp CR5_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pnmos_4_cr6_3.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pnmos_4_cr6_3.sp deleted file mode 100644 index 1ccc074df6..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pnmos_4_cr6_3.sp +++ /dev/null @@ -1,71 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:34 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM13 Voutp net38 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net38 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net35 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM12 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM11 net33 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net38 Vinn net33 net39 pmos_rvt w=WA l=LA nfin=nA -MM7 net35 Vinp net33 net39 pmos_rvt w=WA l=LA nfin=nA -CC2 Voutp net38 1p $[CP] -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR6_3 Vbiasn1 Vbiasn2 Vbiasp -*.PININFO Vbiasn1:O Vbiasn2:O Vbiasp:O -MM2 Vbiasp Vbiasn2 Vbiasn1 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn2 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 Vbiasn1 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM5 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn2 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_miller_compensated_pmos -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR6_3 Biasn1 Biasn2 Biasp CR6_3 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pnmos_cr13_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pnmos_cr13_1.sp deleted file mode 100644 index 4dbba93911..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pnmos_cr13_1.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:34 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM13 Voutp net38 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net38 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net35 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM12 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM11 net33 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net38 Vinn net33 net39 pmos_rvt w=WA l=LA nfin=nA -MM7 net35 Vinp net33 net39 pmos_rvt w=WA l=LA nfin=nA -CC2 Voutp net38 1p $[CP] -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_miller_compensated_pmos -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR13_2 Biasn Biasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pnmos_cr13_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pnmos_cr13_2.sp deleted file mode 100644 index 4dbba93911..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pnmos_cr13_2.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:34 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM13 Voutp net38 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net38 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net35 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM12 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM11 net33 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net38 Vinn net33 net39 pmos_rvt w=WA l=LA nfin=nA -MM7 net35 Vinp net33 net39 pmos_rvt w=WA l=LA nfin=nA -CC2 Voutp net38 1p $[CP] -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_miller_compensated_pmos -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR13_2 Biasn Biasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pnmos_cr14_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pnmos_cr14_2.sp deleted file mode 100644 index bd852707e2..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pnmos_cr14_2.sp +++ /dev/null @@ -1,69 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:34 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM13 Voutp net38 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net38 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net35 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM12 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM11 net33 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net38 Vinn net33 net39 pmos_rvt w=WA l=LA nfin=nA -MM7 net35 Vinp net33 net39 pmos_rvt w=WA l=LA nfin=nA -CC2 Voutp net38 1p $[CP] -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR14_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net010 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 Vbiasn net010 res=rK -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_miller_compensated_pmos -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR14_2 Biasn Biasp CR14_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pnmos_cr15_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pnmos_cr15_1.sp deleted file mode 100644 index 47b75f3b35..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pnmos_cr15_1.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:34 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM13 Voutp net38 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net38 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net35 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM12 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM11 net33 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net38 Vinn net33 net39 pmos_rvt w=WA l=LA nfin=nA -MM7 net35 Vinp net33 net39 pmos_rvt w=WA l=LA nfin=nA -CC2 Voutp net38 1p $[CP] -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR15_1 Vbiasp -*.PININFO Vbiasp:O -RR1 Vbiasp gnd! res=rK -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_miller_compensated_pmos -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR15_1 Biasp CR15_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pnmos_cr16_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pnmos_cr16_1.sp deleted file mode 100644 index be015af5dd..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pnmos_cr16_1.sp +++ /dev/null @@ -1,67 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:34 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM13 Voutp net38 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net38 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net35 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM12 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM11 net33 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net38 Vinn net33 net39 pmos_rvt w=WA l=LA nfin=nA -MM7 net35 Vinp net33 net39 pmos_rvt w=WA l=LA nfin=nA -CC2 Voutp net38 1p $[CP] -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR16_1 Vbiasp -*.PININFO Vbiasp:O -RR0 vdd! net6 res=rK -RR1 Vbiasp gnd! res=rK -MM2 Vbiasp Vbiasp net6 vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_miller_compensated_pmos -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR16_1 Biasp CR16_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pnmos_cr2_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pnmos_cr2_2.sp deleted file mode 100644 index cfeb4cd046..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pnmos_cr2_2.sp +++ /dev/null @@ -1,69 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:34 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM13 Voutp net38 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net38 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net35 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM12 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM11 net33 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net38 Vinn net33 net39 pmos_rvt w=WA l=LA nfin=nA -MM7 net35 Vinp net33 net39 pmos_rvt w=WA l=LA nfin=nA -CC2 Voutp net38 1p $[CP] -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR2_2_wilson Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -RR0 Vbiasn gnd! res=rK -MM2 Vbiasp net12 Vbiasn gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_miller_compensated_pmos -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR2_2_wilson Biasn Biasp CR2_2_wilson -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pnmos_cr3_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pnmos_cr3_2.sp deleted file mode 100644 index 890bb765cc..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pnmos_cr3_2.sp +++ /dev/null @@ -1,69 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:34 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM13 Voutp net38 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net38 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net35 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM12 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM11 net33 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net38 Vinn net33 net39 pmos_rvt w=WA l=LA nfin=nA -MM7 net35 Vinp net33 net39 pmos_rvt w=WA l=LA nfin=nA -CC2 Voutp net38 1p $[CP] -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR3_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 net15 gnd! res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_miller_compensated_pmos -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR3_2 Biasn Biasp CR3_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pnmos_cr4_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pnmos_cr4_2.sp deleted file mode 100644 index 7bc976afbf..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pnmos_cr4_2.sp +++ /dev/null @@ -1,74 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:34 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM13 Voutp net38 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net38 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net35 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM12 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM11 net33 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net38 Vinn net33 net39 pmos_rvt w=WA l=LA nfin=nA -MM7 net35 Vinp net33 net39 pmos_rvt w=WA l=LA nfin=nA -CC2 Voutp net38 1p $[CP] -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR4_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM11 net023 net024 Vbiasn gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM8 net025 net010 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM9 net024 net024 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM7 net010 net010 net025 gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net025 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 net024 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net010 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_miller_compensated_pmos -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR4_2 Biasn Biasp CR4_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pnmos_cr5_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pnmos_cr5_2.sp deleted file mode 100644 index 226627e033..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pnmos_cr5_2.sp +++ /dev/null @@ -1,71 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:34 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM13 Voutp net38 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net38 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net35 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM12 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM11 net33 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net38 Vinn net33 net39 pmos_rvt w=WA l=LA nfin=nA -MM7 net35 Vinp net33 net39 pmos_rvt w=WA l=LA nfin=nA -CC2 Voutp net38 1p $[CP] -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR5_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM5 net014 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net014 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_miller_compensated_pmos -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR5_2 Biasn Biasp CR5_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pnmos_cr6_3.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pnmos_cr6_3.sp deleted file mode 100644 index 4054c2b23c..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_miller_compensated_pmos_LG_pnmos_cr6_3.sp +++ /dev/null @@ -1,71 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:34 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM13 Voutp net38 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net38 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net35 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM12 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM11 net33 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net38 Vinn net33 net39 pmos_rvt w=WA l=LA nfin=nA -MM7 net35 Vinp net33 net39 pmos_rvt w=WA l=LA nfin=nA -CC2 Voutp net38 1p $[CP] -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR6_3 Vbiasn1 Vbiasn2 Vbiasp -*.PININFO Vbiasn1:O Vbiasn2:O Vbiasp:O -MM2 Vbiasp Vbiasn2 Vbiasn1 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn2 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 Vbiasn1 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM5 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn2 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_miller_compensated_pmos -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR6_3 Biasn1 Biasn2 Biasp CR6_3 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_nmos_l1_cr11_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_nmos_l1_cr11_1.sp deleted file mode 100644 index 4bb1a35a51..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_nmos_l1_cr11_1.sp +++ /dev/null @@ -1,64 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:58 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM9 Voutp net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net12 net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp Vinn net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM6 net12 Vinp net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM5 net10 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR11_1 Vbiasn -*.PININFO Vbiasn:O -RRF vdd! Vbiasn res=rK -MM1 net9 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net9 net9 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn net9 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_pmos -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR11_1 Biasn CR11_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_nmos_l1_cr12_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_nmos_l1_cr12_1.sp deleted file mode 100644 index 7416a1d490..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_nmos_l1_cr12_1.sp +++ /dev/null @@ -1,64 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:58 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM9 Voutp net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net12 net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp Vinn net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM6 net12 Vinp net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM5 net10 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR12_1 Vbiasn -*.PININFO Vbiasn:O -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 net10 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn net10 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RRF vdd! Vbiasn res=rK -RR0 vdd! net10 res=rK -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_pmos -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR12_1 Biasn CR12_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_nmos_l1_cr13_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_nmos_l1_cr13_1.sp deleted file mode 100644 index aeeafb5e00..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_nmos_l1_cr13_1.sp +++ /dev/null @@ -1,63 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:58 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM9 Voutp net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net12 net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp Vinn net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM6 net12 Vinp net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM5 net10 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_pmos -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR13_2 Biasn Vbiasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_nmos_l1_cr13_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_nmos_l1_cr13_2.sp deleted file mode 100644 index aeeafb5e00..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_nmos_l1_cr13_2.sp +++ /dev/null @@ -1,63 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:58 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM9 Voutp net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net12 net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp Vinn net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM6 net12 Vinp net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM5 net10 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_pmos -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR13_2 Biasn Vbiasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_nmos_l1_cr14_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_nmos_l1_cr14_2.sp deleted file mode 100644 index a5c7ff4057..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_nmos_l1_cr14_2.sp +++ /dev/null @@ -1,64 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:58 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM9 Voutp net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net12 net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp Vinn net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM6 net12 Vinp net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM5 net10 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR14_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net010 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 Vbiasn net010 res=rK -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_pmos -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR14_2 Biasn Vbiasp CR14_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_nmos_l1_cr1_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_nmos_l1_cr1_1.sp deleted file mode 100644 index a153792d2c..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_nmos_l1_cr1_1.sp +++ /dev/null @@ -1,61 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:58 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM9 Voutp net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net12 net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp Vinn net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM6 net12 Vinp net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM5 net10 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR1_1 Vbiasn -*.PININFO Vbiasn:O -RRF vdd! Vbiasn res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_pmos -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR1_1 Biasn CR1_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_nmos_l1_cr2_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_nmos_l1_cr2_2.sp deleted file mode 100644 index 19caf6a693..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_nmos_l1_cr2_2.sp +++ /dev/null @@ -1,64 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:58 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM9 Voutp net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net12 net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp Vinn net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM6 net12 Vinp net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM5 net10 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR2_2_wilson Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -RR0 Vbiasn gnd! res=rK -MM2 Vbiasp net12 Vbiasn gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_pmos -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR2_2_wilson Biasn Vbiasp CR2_2_wilson -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_nmos_l1_cr3_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_nmos_l1_cr3_2.sp deleted file mode 100644 index 1d64224437..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_nmos_l1_cr3_2.sp +++ /dev/null @@ -1,64 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:58 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM9 Voutp net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net12 net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp Vinn net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM6 net12 Vinp net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM5 net10 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR3_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 net15 gnd! res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_pmos -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR3_2 Biasn Vbiasp CR3_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_nmos_l1_cr4_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_nmos_l1_cr4_2.sp deleted file mode 100644 index 2a1304ecde..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_nmos_l1_cr4_2.sp +++ /dev/null @@ -1,69 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:58 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM9 Voutp net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net12 net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp Vinn net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM6 net12 Vinp net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM5 net10 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR4_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM11 net023 net024 Vbiasn gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM8 net025 net010 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM9 net024 net024 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM7 net010 net010 net025 gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net025 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 net024 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net010 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_pmos -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR4_2 Biasn Vbiasp CR4_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_nmos_l1_cr5_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_nmos_l1_cr5_2.sp deleted file mode 100644 index 001f836e2e..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_nmos_l1_cr5_2.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:58 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM9 Voutp net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net12 net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp Vinn net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM6 net12 Vinp net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM5 net10 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR5_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM5 net014 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net014 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_pmos -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR5_2 Biasn Vbiasp CR5_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_nmos_l1_cr7_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_nmos_l1_cr7_1.sp deleted file mode 100644 index 090b5c1301..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_nmos_l1_cr7_1.sp +++ /dev/null @@ -1,64 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:58 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM9 Voutp net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net12 net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp Vinn net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM6 net12 Vinp net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM5 net10 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR7_1 Vbiasn -*.PININFO Vbiasn:O -RR1 Vbiasn net7 res=rK -RR0 vdd! net7 res=rK -RRF vdd! Vbiasn res=rK -MM1 net7 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_pmos -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR7_1 Biasn CR7_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_nmos_l1_cr9_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_nmos_l1_cr9_1.sp deleted file mode 100644 index ccccf9a14c..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_nmos_l1_cr9_1.sp +++ /dev/null @@ -1,62 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:58 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM9 Voutp net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net12 net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp Vinn net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM6 net12 Vinp net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM5 net10 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR9_1 Vbiasn -*.PININFO Vbiasn:O -RR1 net05 gnd! res=rK -RRF vdd! Vbiasn res=rK -MM0 Vbiasn Vbiasn net05 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_pmos -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR9_1 Biasn CR9_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_npmos_cr11_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_npmos_cr11_1.sp deleted file mode 100644 index 5873e217d3..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_npmos_cr11_1.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:58 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM9 Voutp net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net12 net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp Vinn net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM6 net12 Vinp net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM5 net10 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR11_1 Vbiasn -*.PININFO Vbiasn:O -RRF vdd! Vbiasn res=rK -MM1 net9 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net9 net9 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn net9 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_pmos -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR11_1 Biasn CR11_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_npmos_cr12_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_npmos_cr12_1.sp deleted file mode 100644 index 499c108fbc..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_npmos_cr12_1.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:58 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM9 Voutp net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net12 net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp Vinn net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM6 net12 Vinp net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM5 net10 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR12_1 Vbiasn -*.PININFO Vbiasn:O -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 net10 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn net10 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RRF vdd! Vbiasn res=rK -RR0 vdd! net10 res=rK -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_pmos -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR12_1 Biasn CR12_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_npmos_cr13_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_npmos_cr13_1.sp deleted file mode 100644 index de29e3439c..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_npmos_cr13_1.sp +++ /dev/null @@ -1,65 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:58 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM9 Voutp net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net12 net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp Vinn net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM6 net12 Vinp net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM5 net10 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_pmos -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR13_2 Biasn Vbiasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_npmos_cr13_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_npmos_cr13_2.sp deleted file mode 100644 index de29e3439c..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_npmos_cr13_2.sp +++ /dev/null @@ -1,65 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:58 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM9 Voutp net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net12 net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp Vinn net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM6 net12 Vinp net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM5 net10 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_pmos -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR13_2 Biasn Vbiasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_npmos_cr14_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_npmos_cr14_2.sp deleted file mode 100644 index 7e13db07af..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_npmos_cr14_2.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:58 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM9 Voutp net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net12 net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp Vinn net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM6 net12 Vinp net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM5 net10 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR14_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net010 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 Vbiasn net010 res=rK -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_pmos -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR14_2 Biasn Vbiasp CR14_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_npmos_cr1_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_npmos_cr1_1.sp deleted file mode 100644 index 8533742f32..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_npmos_cr1_1.sp +++ /dev/null @@ -1,63 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:58 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM9 Voutp net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net12 net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp Vinn net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM6 net12 Vinp net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM5 net10 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR1_1 Vbiasn -*.PININFO Vbiasn:O -RRF vdd! Vbiasn res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_pmos -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR1_1 Biasn CR1_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_npmos_cr2_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_npmos_cr2_2.sp deleted file mode 100644 index 263752b13a..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_npmos_cr2_2.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:58 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM9 Voutp net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net12 net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp Vinn net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM6 net12 Vinp net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM5 net10 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR2_2_wilson Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -RR0 Vbiasn gnd! res=rK -MM2 Vbiasp net12 Vbiasn gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_pmos -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR2_2_wilson Biasn Vbiasp CR2_2_wilson -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_npmos_cr3_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_npmos_cr3_2.sp deleted file mode 100644 index 27c2b80f29..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_npmos_cr3_2.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:58 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM9 Voutp net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net12 net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp Vinn net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM6 net12 Vinp net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM5 net10 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR3_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 net15 gnd! res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_pmos -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR3_2 Biasn Vbiasp CR3_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_npmos_cr4_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_npmos_cr4_2.sp deleted file mode 100644 index 7cbc98957b..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_npmos_cr4_2.sp +++ /dev/null @@ -1,71 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:58 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM9 Voutp net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net12 net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp Vinn net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM6 net12 Vinp net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM5 net10 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR4_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM11 net023 net024 Vbiasn gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM8 net025 net010 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM9 net024 net024 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM7 net010 net010 net025 gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net025 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 net024 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net010 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_pmos -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR4_2 Biasn Vbiasp CR4_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_npmos_cr5_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_npmos_cr5_2.sp deleted file mode 100644 index 28ad7cb256..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_npmos_cr5_2.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:58 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM9 Voutp net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net12 net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp Vinn net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM6 net12 Vinp net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM5 net10 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR5_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM5 net014 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net014 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_pmos -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR5_2 Biasn Vbiasp CR5_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_npmos_cr7_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_npmos_cr7_1.sp deleted file mode 100644 index a50b2e6ee5..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_npmos_cr7_1.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:58 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM9 Voutp net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net12 net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp Vinn net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM6 net12 Vinp net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM5 net10 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR7_1 Vbiasn -*.PININFO Vbiasn:O -RR1 Vbiasn net7 res=rK -RR0 vdd! net7 res=rK -RRF vdd! Vbiasn res=rK -MM1 net7 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_pmos -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR7_1 Biasn CR7_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_npmos_cr9_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_npmos_cr9_1.sp deleted file mode 100644 index a7e4b571d0..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_npmos_cr9_1.sp +++ /dev/null @@ -1,64 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:58 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM9 Voutp net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net12 net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp Vinn net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM6 net12 Vinp net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM5 net10 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR9_1 Vbiasn -*.PININFO Vbiasn:O -RR1 net05 gnd! res=rK -RRF vdd! Vbiasn res=rK -MM0 Vbiasn Vbiasn net05 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_pmos -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR9_1 Biasn CR9_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pmos_cr11_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pmos_cr11_1.sp deleted file mode 100644 index 624fd29d31..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pmos_cr11_1.sp +++ /dev/null @@ -1,62 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:58 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM9 Voutp net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net12 net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp Vinn net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM6 net12 Vinp net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM5 net10 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos Biasn Vbiasp -*.PININFO Biasn:I Vbiasp:O -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR11_1 Vbiasn -*.PININFO Vbiasn:O -RRF vdd! Vbiasn res=rK -MM1 net9 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net9 net9 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn net9 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_pmos -xiLG_pmos Biasn LG_Vbiasp LG_pmos -xibCR11_1 Biasn CR11_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pmos_cr12_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pmos_cr12_1.sp deleted file mode 100644 index 6e6a55fe79..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pmos_cr12_1.sp +++ /dev/null @@ -1,62 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:58 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM9 Voutp net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net12 net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp Vinn net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM6 net12 Vinp net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM5 net10 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos Biasn Vbiasp -*.PININFO Biasn:I Vbiasp:O -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR12_1 Vbiasn -*.PININFO Vbiasn:O -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 net10 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn net10 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RRF vdd! Vbiasn res=rK -RR0 vdd! net10 res=rK -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_pmos -xiLG_pmos Biasn LG_Vbiasp LG_pmos -xibCR12_1 Biasn CR12_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pmos_cr13_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pmos_cr13_1.sp deleted file mode 100644 index f05d41ba98..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pmos_cr13_1.sp +++ /dev/null @@ -1,61 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:58 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM9 Voutp net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net12 net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp Vinn net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM6 net12 Vinp net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM5 net10 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos Biasn Vbiasp -*.PININFO Biasn:I Vbiasp:O -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_pmos -xiLG_pmos Biasn LG_Vbiasp LG_pmos -xibCR13_2 Biasn Vbiasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pmos_cr13_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pmos_cr13_2.sp deleted file mode 100644 index f05d41ba98..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pmos_cr13_2.sp +++ /dev/null @@ -1,61 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:58 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM9 Voutp net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net12 net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp Vinn net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM6 net12 Vinp net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM5 net10 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos Biasn Vbiasp -*.PININFO Biasn:I Vbiasp:O -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_pmos -xiLG_pmos Biasn LG_Vbiasp LG_pmos -xibCR13_2 Biasn Vbiasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pmos_cr14_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pmos_cr14_2.sp deleted file mode 100644 index 492c3781c3..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pmos_cr14_2.sp +++ /dev/null @@ -1,62 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:58 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM9 Voutp net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net12 net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp Vinn net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM6 net12 Vinp net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM5 net10 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos Biasn Vbiasp -*.PININFO Biasn:I Vbiasp:O -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR14_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net010 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 Vbiasn net010 res=rK -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_pmos -xiLG_pmos Biasn LG_Vbiasp LG_pmos -xibCR14_2 Biasn Vbiasp CR14_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pmos_cr1_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pmos_cr1_1.sp deleted file mode 100644 index 039dfc2071..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pmos_cr1_1.sp +++ /dev/null @@ -1,59 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:58 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM9 Voutp net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net12 net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp Vinn net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM6 net12 Vinp net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM5 net10 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos Biasn Vbiasp -*.PININFO Biasn:I Vbiasp:O -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR1_1 Vbiasn -*.PININFO Vbiasn:O -RRF vdd! Vbiasn res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_pmos -xiLG_pmos Biasn LG_Vbiasp LG_pmos -xibCR1_1 Biasn CR1_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pmos_cr2_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pmos_cr2_2.sp deleted file mode 100644 index 0ed525767c..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pmos_cr2_2.sp +++ /dev/null @@ -1,62 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:58 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM9 Voutp net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net12 net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp Vinn net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM6 net12 Vinp net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM5 net10 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos Biasn Vbiasp -*.PININFO Biasn:I Vbiasp:O -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR2_2_wilson Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -RR0 Vbiasn gnd! res=rK -MM2 Vbiasp net12 Vbiasn gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_pmos -xiLG_pmos Biasn LG_Vbiasp LG_pmos -xibCR2_2_wilson Biasn Vbiasp CR2_2_wilson -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pmos_cr3_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pmos_cr3_2.sp deleted file mode 100644 index 78bcf7a6a0..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pmos_cr3_2.sp +++ /dev/null @@ -1,62 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:58 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM9 Voutp net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net12 net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp Vinn net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM6 net12 Vinp net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM5 net10 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos Biasn Vbiasp -*.PININFO Biasn:I Vbiasp:O -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR3_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 net15 gnd! res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_pmos -xiLG_pmos Biasn LG_Vbiasp LG_pmos -xibCR3_2 Biasn Vbiasp CR3_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pmos_cr4_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pmos_cr4_2.sp deleted file mode 100644 index 67270a6e6d..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pmos_cr4_2.sp +++ /dev/null @@ -1,67 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:58 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM9 Voutp net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net12 net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp Vinn net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM6 net12 Vinp net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM5 net10 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos Biasn Vbiasp -*.PININFO Biasn:I Vbiasp:O -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR4_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM11 net023 net024 Vbiasn gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM8 net025 net010 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM9 net024 net024 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM7 net010 net010 net025 gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net025 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 net024 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net010 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_pmos -xiLG_pmos Biasn LG_Vbiasp LG_pmos -xibCR4_2 Biasn Vbiasp CR4_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pmos_cr5_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pmos_cr5_2.sp deleted file mode 100644 index 25f9a278dd..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pmos_cr5_2.sp +++ /dev/null @@ -1,64 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:58 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM9 Voutp net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net12 net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp Vinn net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM6 net12 Vinp net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM5 net10 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos Biasn Vbiasp -*.PININFO Biasn:I Vbiasp:O -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR5_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM5 net014 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net014 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_pmos -xiLG_pmos Biasn LG_Vbiasp LG_pmos -xibCR5_2 Biasn Vbiasp CR5_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pmos_cr7_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pmos_cr7_1.sp deleted file mode 100644 index e30899b17e..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pmos_cr7_1.sp +++ /dev/null @@ -1,62 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:58 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM9 Voutp net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net12 net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp Vinn net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM6 net12 Vinp net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM5 net10 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos Biasn Vbiasp -*.PININFO Biasn:I Vbiasp:O -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR7_1 Vbiasn -*.PININFO Vbiasn:O -RR1 Vbiasn net7 res=rK -RR0 vdd! net7 res=rK -RRF vdd! Vbiasn res=rK -MM1 net7 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_pmos -xiLG_pmos Biasn LG_Vbiasp LG_pmos -xibCR7_1 Biasn CR7_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pmos_cr9_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pmos_cr9_1.sp deleted file mode 100644 index 486850c52c..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pmos_cr9_1.sp +++ /dev/null @@ -1,60 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:58 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM9 Voutp net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net12 net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp Vinn net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM6 net12 Vinp net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM5 net10 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos Biasn Vbiasp -*.PININFO Biasn:I Vbiasp:O -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR9_1 Vbiasn -*.PININFO Vbiasn:O -RR1 net05 gnd! res=rK -RRF vdd! Vbiasn res=rK -MM0 Vbiasn Vbiasn net05 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_pmos -xiLG_pmos Biasn LG_Vbiasp LG_pmos -xibCR9_1 Biasn CR9_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pmos_l1_cr13_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pmos_l1_cr13_1.sp deleted file mode 100644 index fc48bcf516..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pmos_l1_cr13_1.sp +++ /dev/null @@ -1,63 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:58 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM9 Voutp net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net12 net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp Vinn net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM6 net12 Vinp net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM5 net10 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_pmos -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR13_2 Biasn Biasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pmos_l1_cr13_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pmos_l1_cr13_2.sp deleted file mode 100644 index fc48bcf516..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pmos_l1_cr13_2.sp +++ /dev/null @@ -1,63 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:58 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM9 Voutp net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net12 net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp Vinn net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM6 net12 Vinp net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM5 net10 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_pmos -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR13_2 Biasn Biasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pmos_l1_cr14_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pmos_l1_cr14_2.sp deleted file mode 100644 index 081eee6ef5..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pmos_l1_cr14_2.sp +++ /dev/null @@ -1,64 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:58 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM9 Voutp net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net12 net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp Vinn net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM6 net12 Vinp net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM5 net10 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR14_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net010 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 Vbiasn net010 res=rK -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_pmos -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR14_2 Biasn Biasp CR14_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pmos_l1_cr15_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pmos_l1_cr15_1.sp deleted file mode 100644 index 4a479bf2a1..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pmos_l1_cr15_1.sp +++ /dev/null @@ -1,61 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:58 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM9 Voutp net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net12 net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp Vinn net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM6 net12 Vinp net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM5 net10 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR15_1 Vbiasp -*.PININFO Vbiasp:O -RR1 Vbiasp gnd! res=rK -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_pmos -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR15_1 Biasp CR15_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pmos_l1_cr16_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pmos_l1_cr16_1.sp deleted file mode 100644 index 6644bcbb08..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pmos_l1_cr16_1.sp +++ /dev/null @@ -1,62 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:58 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM9 Voutp net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net12 net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp Vinn net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM6 net12 Vinp net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM5 net10 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR16_1 Vbiasp -*.PININFO Vbiasp:O -RR0 vdd! net6 res=rK -RR1 Vbiasp gnd! res=rK -MM2 Vbiasp Vbiasp net6 vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_pmos -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR16_1 Biasp CR16_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pmos_l1_cr2_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pmos_l1_cr2_2.sp deleted file mode 100644 index 3a21253a5d..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pmos_l1_cr2_2.sp +++ /dev/null @@ -1,64 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:58 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM9 Voutp net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net12 net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp Vinn net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM6 net12 Vinp net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM5 net10 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR2_2_wilson Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -RR0 Vbiasn gnd! res=rK -MM2 Vbiasp net12 Vbiasn gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_pmos -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR2_2_wilson Biasn Biasp CR2_2_wilson -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pmos_l1_cr3_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pmos_l1_cr3_2.sp deleted file mode 100644 index 5b12647863..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pmos_l1_cr3_2.sp +++ /dev/null @@ -1,64 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:58 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM9 Voutp net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net12 net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp Vinn net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM6 net12 Vinp net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM5 net10 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR3_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 net15 gnd! res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_pmos -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR3_2 Biasn Biasp CR3_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pmos_l1_cr4_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pmos_l1_cr4_2.sp deleted file mode 100644 index 332b7b6f69..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pmos_l1_cr4_2.sp +++ /dev/null @@ -1,69 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:58 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM9 Voutp net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net12 net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp Vinn net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM6 net12 Vinp net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM5 net10 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR4_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM11 net023 net024 Vbiasn gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM8 net025 net010 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM9 net024 net024 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM7 net010 net010 net025 gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net025 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 net024 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net010 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_pmos -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR4_2 Biasn Biasp CR4_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pmos_l1_cr5_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pmos_l1_cr5_2.sp deleted file mode 100644 index b263a35217..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pmos_l1_cr5_2.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:58 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM9 Voutp net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net12 net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp Vinn net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM6 net12 Vinp net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM5 net10 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR5_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM5 net014 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net014 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_pmos -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR5_2 Biasn Biasp CR5_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pmos_l1_cr6_3.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pmos_l1_cr6_3.sp deleted file mode 100644 index d92d6753e5..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pmos_l1_cr6_3.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:58 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM9 Voutp net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net12 net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp Vinn net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM6 net12 Vinp net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM5 net10 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR6_3 Vbiasn1 Vbiasn2 Vbiasp -*.PININFO Vbiasn1:O Vbiasn2:O Vbiasp:O -MM2 Vbiasp Vbiasn2 Vbiasn1 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn2 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 Vbiasn1 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM5 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn2 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_pmos -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR6_3 Biasn1 Biasn2 Biasp CR6_3 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pnmos_4_cr13_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pnmos_4_cr13_1.sp deleted file mode 100644 index e64b52e517..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pnmos_4_cr13_1.sp +++ /dev/null @@ -1,65 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:58 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM9 Voutp net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net12 net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp Vinn net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM6 net12 Vinp net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM5 net10 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_pmos -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR13_2 Biasn Biasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pnmos_4_cr13_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pnmos_4_cr13_2.sp deleted file mode 100644 index e64b52e517..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pnmos_4_cr13_2.sp +++ /dev/null @@ -1,65 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:58 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM9 Voutp net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net12 net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp Vinn net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM6 net12 Vinp net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM5 net10 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_pmos -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR13_2 Biasn Biasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pnmos_4_cr14_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pnmos_4_cr14_2.sp deleted file mode 100644 index 6578677929..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pnmos_4_cr14_2.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:58 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM9 Voutp net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net12 net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp Vinn net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM6 net12 Vinp net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM5 net10 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR14_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net010 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 Vbiasn net010 res=rK -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_pmos -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR14_2 Biasn Biasp CR14_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pnmos_4_cr15_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pnmos_4_cr15_1.sp deleted file mode 100644 index f16275ea6f..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pnmos_4_cr15_1.sp +++ /dev/null @@ -1,63 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:58 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM9 Voutp net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net12 net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp Vinn net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM6 net12 Vinp net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM5 net10 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR15_1 Vbiasp -*.PININFO Vbiasp:O -RR1 Vbiasp gnd! res=rK -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_pmos -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR15_1 Biasp CR15_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pnmos_4_cr16_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pnmos_4_cr16_1.sp deleted file mode 100644 index c7e8a4e224..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pnmos_4_cr16_1.sp +++ /dev/null @@ -1,64 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:58 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM9 Voutp net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net12 net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp Vinn net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM6 net12 Vinp net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM5 net10 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR16_1 Vbiasp -*.PININFO Vbiasp:O -RR0 vdd! net6 res=rK -RR1 Vbiasp gnd! res=rK -MM2 Vbiasp Vbiasp net6 vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_pmos -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR16_1 Biasp CR16_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pnmos_4_cr2_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pnmos_4_cr2_2.sp deleted file mode 100644 index 76a1dd0bf0..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pnmos_4_cr2_2.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:58 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM9 Voutp net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net12 net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp Vinn net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM6 net12 Vinp net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM5 net10 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR2_2_wilson Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -RR0 Vbiasn gnd! res=rK -MM2 Vbiasp net12 Vbiasn gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_pmos -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR2_2_wilson Biasn Biasp CR2_2_wilson -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pnmos_4_cr3_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pnmos_4_cr3_2.sp deleted file mode 100644 index 7b4e5f1e1f..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pnmos_4_cr3_2.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:58 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM9 Voutp net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net12 net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp Vinn net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM6 net12 Vinp net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM5 net10 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR3_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 net15 gnd! res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_pmos -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR3_2 Biasn Biasp CR3_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pnmos_4_cr4_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pnmos_4_cr4_2.sp deleted file mode 100644 index f14aa792a7..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pnmos_4_cr4_2.sp +++ /dev/null @@ -1,71 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:58 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM9 Voutp net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net12 net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp Vinn net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM6 net12 Vinp net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM5 net10 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR4_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM11 net023 net024 Vbiasn gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM8 net025 net010 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM9 net024 net024 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM7 net010 net010 net025 gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net025 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 net024 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net010 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_pmos -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR4_2 Biasn Biasp CR4_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pnmos_4_cr5_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pnmos_4_cr5_2.sp deleted file mode 100644 index 3d0e41d742..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pnmos_4_cr5_2.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:58 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM9 Voutp net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net12 net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp Vinn net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM6 net12 Vinp net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM5 net10 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR5_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM5 net014 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net014 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_pmos -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR5_2 Biasn Biasp CR5_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pnmos_4_cr6_3.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pnmos_4_cr6_3.sp deleted file mode 100644 index f1b054c95f..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pnmos_4_cr6_3.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:58 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM9 Voutp net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net12 net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp Vinn net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM6 net12 Vinp net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM5 net10 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR6_3 Vbiasn1 Vbiasn2 Vbiasp -*.PININFO Vbiasn1:O Vbiasn2:O Vbiasp:O -MM2 Vbiasp Vbiasn2 Vbiasn1 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn2 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 Vbiasn1 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM5 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn2 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_pmos -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR6_3 Biasn1 Biasn2 Biasp CR6_3 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pnmos_cr13_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pnmos_cr13_1.sp deleted file mode 100644 index d138966ad4..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pnmos_cr13_1.sp +++ /dev/null @@ -1,65 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:58 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM9 Voutp net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net12 net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp Vinn net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM6 net12 Vinp net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM5 net10 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_pmos -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR13_2 Biasn Biasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pnmos_cr13_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pnmos_cr13_2.sp deleted file mode 100644 index d138966ad4..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pnmos_cr13_2.sp +++ /dev/null @@ -1,65 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:58 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM9 Voutp net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net12 net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp Vinn net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM6 net12 Vinp net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM5 net10 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_pmos -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR13_2 Biasn Biasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pnmos_cr14_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pnmos_cr14_2.sp deleted file mode 100644 index 50d16d4d95..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pnmos_cr14_2.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:58 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM9 Voutp net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net12 net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp Vinn net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM6 net12 Vinp net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM5 net10 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR14_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net010 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 Vbiasn net010 res=rK -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_pmos -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR14_2 Biasn Biasp CR14_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pnmos_cr15_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pnmos_cr15_1.sp deleted file mode 100644 index 5152ed984c..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pnmos_cr15_1.sp +++ /dev/null @@ -1,63 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:58 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM9 Voutp net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net12 net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp Vinn net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM6 net12 Vinp net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM5 net10 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR15_1 Vbiasp -*.PININFO Vbiasp:O -RR1 Vbiasp gnd! res=rK -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_pmos -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR15_1 Biasp CR15_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pnmos_cr16_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pnmos_cr16_1.sp deleted file mode 100644 index aea98a7543..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pnmos_cr16_1.sp +++ /dev/null @@ -1,64 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:58 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM9 Voutp net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net12 net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp Vinn net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM6 net12 Vinp net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM5 net10 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR16_1 Vbiasp -*.PININFO Vbiasp:O -RR0 vdd! net6 res=rK -RR1 Vbiasp gnd! res=rK -MM2 Vbiasp Vbiasp net6 vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_pmos -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR16_1 Biasp CR16_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pnmos_cr2_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pnmos_cr2_2.sp deleted file mode 100644 index ae2dc3621e..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pnmos_cr2_2.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:58 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM9 Voutp net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net12 net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp Vinn net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM6 net12 Vinp net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM5 net10 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR2_2_wilson Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -RR0 Vbiasn gnd! res=rK -MM2 Vbiasp net12 Vbiasn gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_pmos -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR2_2_wilson Biasn Biasp CR2_2_wilson -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pnmos_cr3_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pnmos_cr3_2.sp deleted file mode 100644 index 6b1d7c49eb..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pnmos_cr3_2.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:58 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM9 Voutp net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net12 net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp Vinn net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM6 net12 Vinp net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM5 net10 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR3_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 net15 gnd! res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_pmos -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR3_2 Biasn Biasp CR3_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pnmos_cr4_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pnmos_cr4_2.sp deleted file mode 100644 index c0b7e8101a..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pnmos_cr4_2.sp +++ /dev/null @@ -1,71 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:58 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM9 Voutp net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net12 net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp Vinn net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM6 net12 Vinp net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM5 net10 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR4_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM11 net023 net024 Vbiasn gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM8 net025 net010 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM9 net024 net024 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM7 net010 net010 net025 gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net025 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 net024 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net010 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_pmos -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR4_2 Biasn Biasp CR4_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pnmos_cr5_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pnmos_cr5_2.sp deleted file mode 100644 index ed4707276b..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pnmos_cr5_2.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:58 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM9 Voutp net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net12 net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp Vinn net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM6 net12 Vinp net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM5 net10 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR5_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM5 net014 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net014 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_pmos -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR5_2 Biasn Biasp CR5_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pnmos_cr6_3.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pnmos_cr6_3.sp deleted file mode 100644 index 47ca8cf9ba..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_pmos_LG_pnmos_cr6_3.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:58 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM9 Voutp net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net12 net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp Vinn net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM6 net12 Vinp net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM5 net10 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR6_3 Vbiasn1 Vbiasn2 Vbiasp -*.PININFO Vbiasn1:O Vbiasn2:O Vbiasp:O -MM2 Vbiasp Vbiasn2 Vbiasn1 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn2 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 Vbiasn1 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM5 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn2 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasp Vinn Vinp Voutp single_ended_pmos -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR6_3 Biasn1 Biasn2 Biasp CR6_3 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_telescopic_LG_load_biasp_LV_cr11_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_telescopic_LG_load_biasp_LV_cr11_1.sp deleted file mode 100644 index 99898298ab..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_telescopic_LG_load_biasp_LV_cr11_1.sp +++ /dev/null @@ -1,65 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_telescopic -* View Name: schematic -* Netlisted on: Sep 11 21:39:36 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_telescopic -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_telescopic Vbiasn Vbiasp2 Vinn Vinp Voutp -*.PININFO Vbiasn:I Vbiasp2:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net11 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net13 Vinn net11 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net11 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net13 Vbiasp2 net016 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp Vbiasp2 net014 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net014 net13 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net016 net13 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasp_LV Biasn Vbiasp2 -*.PININFO Biasn:I Vbiasp2:O -MM0 Vbiasp2 Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net8 Vbiasp2 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp2 Vbiasp2 net8 vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR11_1 Vbiasn -*.PININFO Vbiasn:O -RRF vdd! Vbiasn res=rK -MM1 net9 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net9 net9 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn net9 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp2 Vinn Vinp Voutp single_ended_telescopic -xiLG_load_biasp_LV Biasn LG_Vbiasp2 LG_load_biasp_LV -xibCR11_1 Biasn CR11_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_telescopic_LG_load_biasp_LV_cr12_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_telescopic_LG_load_biasp_LV_cr12_1.sp deleted file mode 100644 index eac04654df..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_telescopic_LG_load_biasp_LV_cr12_1.sp +++ /dev/null @@ -1,65 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_telescopic -* View Name: schematic -* Netlisted on: Sep 11 21:39:36 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_telescopic -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_telescopic Vbiasn Vbiasp2 Vinn Vinp Voutp -*.PININFO Vbiasn:I Vbiasp2:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net11 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net13 Vinn net11 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net11 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net13 Vbiasp2 net016 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp Vbiasp2 net014 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net014 net13 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net016 net13 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasp_LV Biasn Vbiasp2 -*.PININFO Biasn:I Vbiasp2:O -MM0 Vbiasp2 Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net8 Vbiasp2 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp2 Vbiasp2 net8 vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR12_1 Vbiasn -*.PININFO Vbiasn:O -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 net10 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn net10 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RRF vdd! Vbiasn res=rK -RR0 vdd! net10 res=rK -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp2 Vinn Vinp Voutp single_ended_telescopic -xiLG_load_biasp_LV Biasn LG_Vbiasp2 LG_load_biasp_LV -xibCR12_1 Biasn CR12_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_telescopic_LG_load_biasp_LV_cr13_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_telescopic_LG_load_biasp_LV_cr13_1.sp deleted file mode 100644 index 3d95d2572e..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_telescopic_LG_load_biasp_LV_cr13_1.sp +++ /dev/null @@ -1,64 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_telescopic -* View Name: schematic -* Netlisted on: Sep 11 21:39:36 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_telescopic -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_telescopic Vbiasn Vbiasp2 Vinn Vinp Voutp -*.PININFO Vbiasn:I Vbiasp2:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net11 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net13 Vinn net11 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net11 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net13 Vbiasp2 net016 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp Vbiasp2 net014 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net014 net13 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net016 net13 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasp_LV Biasn Vbiasp2 -*.PININFO Biasn:I Vbiasp2:O -MM0 Vbiasp2 Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net8 Vbiasp2 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp2 Vbiasp2 net8 vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp2 Vinn Vinp Voutp single_ended_telescopic -xiLG_load_biasp_LV Biasn LG_Vbiasp2 LG_load_biasp_LV -xibCR13_2 Biasn Vbiasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_telescopic_LG_load_biasp_LV_cr13_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_telescopic_LG_load_biasp_LV_cr13_2.sp deleted file mode 100644 index 3d95d2572e..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_telescopic_LG_load_biasp_LV_cr13_2.sp +++ /dev/null @@ -1,64 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_telescopic -* View Name: schematic -* Netlisted on: Sep 11 21:39:36 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_telescopic -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_telescopic Vbiasn Vbiasp2 Vinn Vinp Voutp -*.PININFO Vbiasn:I Vbiasp2:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net11 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net13 Vinn net11 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net11 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net13 Vbiasp2 net016 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp Vbiasp2 net014 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net014 net13 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net016 net13 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasp_LV Biasn Vbiasp2 -*.PININFO Biasn:I Vbiasp2:O -MM0 Vbiasp2 Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net8 Vbiasp2 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp2 Vbiasp2 net8 vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp2 Vinn Vinp Voutp single_ended_telescopic -xiLG_load_biasp_LV Biasn LG_Vbiasp2 LG_load_biasp_LV -xibCR13_2 Biasn Vbiasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_telescopic_LG_load_biasp_LV_cr14_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_telescopic_LG_load_biasp_LV_cr14_2.sp deleted file mode 100644 index efa7e72fb0..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_telescopic_LG_load_biasp_LV_cr14_2.sp +++ /dev/null @@ -1,65 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_telescopic -* View Name: schematic -* Netlisted on: Sep 11 21:39:36 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_telescopic -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_telescopic Vbiasn Vbiasp2 Vinn Vinp Voutp -*.PININFO Vbiasn:I Vbiasp2:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net11 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net13 Vinn net11 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net11 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net13 Vbiasp2 net016 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp Vbiasp2 net014 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net014 net13 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net016 net13 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasp_LV Biasn Vbiasp2 -*.PININFO Biasn:I Vbiasp2:O -MM0 Vbiasp2 Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net8 Vbiasp2 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp2 Vbiasp2 net8 vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR14_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net010 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 Vbiasn net010 res=rK -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp2 Vinn Vinp Voutp single_ended_telescopic -xiLG_load_biasp_LV Biasn LG_Vbiasp2 LG_load_biasp_LV -xibCR14_2 Biasn Vbiasp CR14_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_telescopic_LG_load_biasp_LV_cr1_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_telescopic_LG_load_biasp_LV_cr1_1.sp deleted file mode 100644 index f1a5af3f2d..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_telescopic_LG_load_biasp_LV_cr1_1.sp +++ /dev/null @@ -1,62 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_telescopic -* View Name: schematic -* Netlisted on: Sep 11 21:39:36 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_telescopic -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_telescopic Vbiasn Vbiasp2 Vinn Vinp Voutp -*.PININFO Vbiasn:I Vbiasp2:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net11 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net13 Vinn net11 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net11 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net13 Vbiasp2 net016 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp Vbiasp2 net014 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net014 net13 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net016 net13 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasp_LV Biasn Vbiasp2 -*.PININFO Biasn:I Vbiasp2:O -MM0 Vbiasp2 Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net8 Vbiasp2 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp2 Vbiasp2 net8 vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR1_1 Vbiasn -*.PININFO Vbiasn:O -RRF vdd! Vbiasn res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp2 Vinn Vinp Voutp single_ended_telescopic -xiLG_load_biasp_LV Biasn LG_Vbiasp2 LG_load_biasp_LV -xibCR1_1 Biasn CR1_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_telescopic_LG_load_biasp_LV_cr2_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_telescopic_LG_load_biasp_LV_cr2_2.sp deleted file mode 100644 index d2f0a9fb0d..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_telescopic_LG_load_biasp_LV_cr2_2.sp +++ /dev/null @@ -1,65 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_telescopic -* View Name: schematic -* Netlisted on: Sep 11 21:39:36 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_telescopic -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_telescopic Vbiasn Vbiasp2 Vinn Vinp Voutp -*.PININFO Vbiasn:I Vbiasp2:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net11 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net13 Vinn net11 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net11 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net13 Vbiasp2 net016 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp Vbiasp2 net014 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net014 net13 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net016 net13 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasp_LV Biasn Vbiasp2 -*.PININFO Biasn:I Vbiasp2:O -MM0 Vbiasp2 Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net8 Vbiasp2 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp2 Vbiasp2 net8 vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR2_2_wilson Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -RR0 Vbiasn gnd! res=rK -MM2 Vbiasp net12 Vbiasn gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp2 Vinn Vinp Voutp single_ended_telescopic -xiLG_load_biasp_LV Biasn LG_Vbiasp2 LG_load_biasp_LV -xibCR2_2_wilson Biasn Vbiasp CR2_2_wilson -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_telescopic_LG_load_biasp_LV_cr3_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_telescopic_LG_load_biasp_LV_cr3_2.sp deleted file mode 100644 index 8cf641d66e..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_telescopic_LG_load_biasp_LV_cr3_2.sp +++ /dev/null @@ -1,65 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_telescopic -* View Name: schematic -* Netlisted on: Sep 11 21:39:36 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_telescopic -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_telescopic Vbiasn Vbiasp2 Vinn Vinp Voutp -*.PININFO Vbiasn:I Vbiasp2:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net11 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net13 Vinn net11 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net11 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net13 Vbiasp2 net016 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp Vbiasp2 net014 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net014 net13 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net016 net13 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasp_LV Biasn Vbiasp2 -*.PININFO Biasn:I Vbiasp2:O -MM0 Vbiasp2 Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net8 Vbiasp2 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp2 Vbiasp2 net8 vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR3_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 net15 gnd! res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp2 Vinn Vinp Voutp single_ended_telescopic -xiLG_load_biasp_LV Biasn LG_Vbiasp2 LG_load_biasp_LV -xibCR3_2 Biasn Vbiasp CR3_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_telescopic_LG_load_biasp_LV_cr4_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_telescopic_LG_load_biasp_LV_cr4_2.sp deleted file mode 100644 index 9c1452d460..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_telescopic_LG_load_biasp_LV_cr4_2.sp +++ /dev/null @@ -1,70 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_telescopic -* View Name: schematic -* Netlisted on: Sep 11 21:39:36 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_telescopic -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_telescopic Vbiasn Vbiasp2 Vinn Vinp Voutp -*.PININFO Vbiasn:I Vbiasp2:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net11 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net13 Vinn net11 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net11 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net13 Vbiasp2 net016 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp Vbiasp2 net014 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net014 net13 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net016 net13 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasp_LV Biasn Vbiasp2 -*.PININFO Biasn:I Vbiasp2:O -MM0 Vbiasp2 Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net8 Vbiasp2 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp2 Vbiasp2 net8 vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR4_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM11 net023 net024 Vbiasn gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM8 net025 net010 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM9 net024 net024 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM7 net010 net010 net025 gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net025 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 net024 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net010 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp2 Vinn Vinp Voutp single_ended_telescopic -xiLG_load_biasp_LV Biasn LG_Vbiasp2 LG_load_biasp_LV -xibCR4_2 Biasn Vbiasp CR4_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_telescopic_LG_load_biasp_LV_cr5_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_telescopic_LG_load_biasp_LV_cr5_2.sp deleted file mode 100644 index 4d262c0ba7..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_telescopic_LG_load_biasp_LV_cr5_2.sp +++ /dev/null @@ -1,67 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_telescopic -* View Name: schematic -* Netlisted on: Sep 11 21:39:36 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_telescopic -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_telescopic Vbiasn Vbiasp2 Vinn Vinp Voutp -*.PININFO Vbiasn:I Vbiasp2:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net11 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net13 Vinn net11 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net11 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net13 Vbiasp2 net016 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp Vbiasp2 net014 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net014 net13 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net016 net13 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasp_LV Biasn Vbiasp2 -*.PININFO Biasn:I Vbiasp2:O -MM0 Vbiasp2 Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net8 Vbiasp2 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp2 Vbiasp2 net8 vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR5_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM5 net014 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net014 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp2 Vinn Vinp Voutp single_ended_telescopic -xiLG_load_biasp_LV Biasn LG_Vbiasp2 LG_load_biasp_LV -xibCR5_2 Biasn Vbiasp CR5_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_telescopic_LG_load_biasp_LV_cr7_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_telescopic_LG_load_biasp_LV_cr7_1.sp deleted file mode 100644 index d56b0d6d5a..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_telescopic_LG_load_biasp_LV_cr7_1.sp +++ /dev/null @@ -1,65 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_telescopic -* View Name: schematic -* Netlisted on: Sep 11 21:39:36 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_telescopic -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_telescopic Vbiasn Vbiasp2 Vinn Vinp Voutp -*.PININFO Vbiasn:I Vbiasp2:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net11 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net13 Vinn net11 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net11 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net13 Vbiasp2 net016 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp Vbiasp2 net014 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net014 net13 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net016 net13 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasp_LV Biasn Vbiasp2 -*.PININFO Biasn:I Vbiasp2:O -MM0 Vbiasp2 Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net8 Vbiasp2 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp2 Vbiasp2 net8 vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR7_1 Vbiasn -*.PININFO Vbiasn:O -RR1 Vbiasn net7 res=rK -RR0 vdd! net7 res=rK -RRF vdd! Vbiasn res=rK -MM1 net7 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp2 Vinn Vinp Voutp single_ended_telescopic -xiLG_load_biasp_LV Biasn LG_Vbiasp2 LG_load_biasp_LV -xibCR7_1 Biasn CR7_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_telescopic_LG_load_biasp_LV_cr9_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_telescopic_LG_load_biasp_LV_cr9_1.sp deleted file mode 100644 index b33bd9af00..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_telescopic_LG_load_biasp_LV_cr9_1.sp +++ /dev/null @@ -1,63 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_telescopic -* View Name: schematic -* Netlisted on: Sep 11 21:39:36 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_telescopic -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_telescopic Vbiasn Vbiasp2 Vinn Vinp Voutp -*.PININFO Vbiasn:I Vbiasp2:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net11 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net13 Vinn net11 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net11 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net13 Vbiasp2 net016 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp Vbiasp2 net014 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net014 net13 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net016 net13 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasp_LV Biasn Vbiasp2 -*.PININFO Biasn:I Vbiasp2:O -MM0 Vbiasp2 Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net8 Vbiasp2 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp2 Vbiasp2 net8 vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR9_1 Vbiasn -*.PININFO Vbiasn:O -RR1 net05 gnd! res=rK -RRF vdd! Vbiasn res=rK -MM0 Vbiasn Vbiasn net05 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp2 Vinn Vinp Voutp single_ended_telescopic -xiLG_load_biasp_LV Biasn LG_Vbiasp2 LG_load_biasp_LV -xibCR9_1 Biasn CR9_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_telescopic_LG_load_biasp_cr11_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_telescopic_LG_load_biasp_cr11_1.sp deleted file mode 100644 index 1e8f6e0c5d..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_telescopic_LG_load_biasp_cr11_1.sp +++ /dev/null @@ -1,65 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_telescopic -* View Name: schematic -* Netlisted on: Sep 11 21:39:36 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_telescopic -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_telescopic Vbiasn Vbiasp2 Vinn Vinp Voutp -*.PININFO Vbiasn:I Vbiasp2:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net11 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net13 Vinn net11 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net11 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net13 Vbiasp2 net016 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp Vbiasp2 net014 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net014 net13 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net016 net13 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasp Biasn Vbiasp1 Vbiasp2 -*.PININFO Biasn:I Vbiasp1:O Vbiasp2:O -MM0 Vbiasp2 Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp2 Vbiasp2 Vbiasp1 vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp1 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR11_1 Vbiasn -*.PININFO Vbiasn:O -RRF vdd! Vbiasn res=rK -MM1 net9 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net9 net9 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn net9 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp2 Vinn Vinp Voutp single_ended_telescopic -xiLG_load_biasp Biasn LG_Vbiasp1 LG_Vbiasp2 LG_load_biasp -xibCR11_1 Biasn CR11_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_telescopic_LG_load_biasp_cr12_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_telescopic_LG_load_biasp_cr12_1.sp deleted file mode 100644 index 981992709d..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_telescopic_LG_load_biasp_cr12_1.sp +++ /dev/null @@ -1,65 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_telescopic -* View Name: schematic -* Netlisted on: Sep 11 21:39:36 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_telescopic -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_telescopic Vbiasn Vbiasp2 Vinn Vinp Voutp -*.PININFO Vbiasn:I Vbiasp2:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net11 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net13 Vinn net11 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net11 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net13 Vbiasp2 net016 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp Vbiasp2 net014 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net014 net13 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net016 net13 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasp Biasn Vbiasp1 Vbiasp2 -*.PININFO Biasn:I Vbiasp1:O Vbiasp2:O -MM0 Vbiasp2 Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp2 Vbiasp2 Vbiasp1 vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp1 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR12_1 Vbiasn -*.PININFO Vbiasn:O -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 net10 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn net10 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RRF vdd! Vbiasn res=rK -RR0 vdd! net10 res=rK -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp2 Vinn Vinp Voutp single_ended_telescopic -xiLG_load_biasp Biasn LG_Vbiasp1 LG_Vbiasp2 LG_load_biasp -xibCR12_1 Biasn CR12_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_telescopic_LG_load_biasp_cr13_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_telescopic_LG_load_biasp_cr13_1.sp deleted file mode 100644 index 3b6f6c9fb8..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_telescopic_LG_load_biasp_cr13_1.sp +++ /dev/null @@ -1,64 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_telescopic -* View Name: schematic -* Netlisted on: Sep 11 21:39:36 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_telescopic -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_telescopic Vbiasn Vbiasp2 Vinn Vinp Voutp -*.PININFO Vbiasn:I Vbiasp2:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net11 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net13 Vinn net11 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net11 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net13 Vbiasp2 net016 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp Vbiasp2 net014 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net014 net13 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net016 net13 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasp Biasn Vbiasp1 Vbiasp2 -*.PININFO Biasn:I Vbiasp1:O Vbiasp2:O -MM0 Vbiasp2 Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp2 Vbiasp2 Vbiasp1 vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp1 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp2 Vinn Vinp Voutp single_ended_telescopic -xiLG_load_biasp Biasn LG_Vbiasp1 LG_Vbiasp2 LG_load_biasp -xibCR13_2 Biasn Vbiasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_telescopic_LG_load_biasp_cr13_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_telescopic_LG_load_biasp_cr13_2.sp deleted file mode 100644 index 3b6f6c9fb8..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_telescopic_LG_load_biasp_cr13_2.sp +++ /dev/null @@ -1,64 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_telescopic -* View Name: schematic -* Netlisted on: Sep 11 21:39:36 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_telescopic -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_telescopic Vbiasn Vbiasp2 Vinn Vinp Voutp -*.PININFO Vbiasn:I Vbiasp2:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net11 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net13 Vinn net11 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net11 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net13 Vbiasp2 net016 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp Vbiasp2 net014 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net014 net13 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net016 net13 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasp Biasn Vbiasp1 Vbiasp2 -*.PININFO Biasn:I Vbiasp1:O Vbiasp2:O -MM0 Vbiasp2 Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp2 Vbiasp2 Vbiasp1 vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp1 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp2 Vinn Vinp Voutp single_ended_telescopic -xiLG_load_biasp Biasn LG_Vbiasp1 LG_Vbiasp2 LG_load_biasp -xibCR13_2 Biasn Vbiasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_telescopic_LG_load_biasp_cr14_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_telescopic_LG_load_biasp_cr14_2.sp deleted file mode 100644 index cd638ad52f..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_telescopic_LG_load_biasp_cr14_2.sp +++ /dev/null @@ -1,65 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_telescopic -* View Name: schematic -* Netlisted on: Sep 11 21:39:36 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_telescopic -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_telescopic Vbiasn Vbiasp2 Vinn Vinp Voutp -*.PININFO Vbiasn:I Vbiasp2:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net11 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net13 Vinn net11 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net11 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net13 Vbiasp2 net016 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp Vbiasp2 net014 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net014 net13 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net016 net13 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasp Biasn Vbiasp1 Vbiasp2 -*.PININFO Biasn:I Vbiasp1:O Vbiasp2:O -MM0 Vbiasp2 Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp2 Vbiasp2 Vbiasp1 vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp1 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR14_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net010 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 Vbiasn net010 res=rK -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp2 Vinn Vinp Voutp single_ended_telescopic -xiLG_load_biasp Biasn LG_Vbiasp1 LG_Vbiasp2 LG_load_biasp -xibCR14_2 Biasn Vbiasp CR14_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_telescopic_LG_load_biasp_cr1_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_telescopic_LG_load_biasp_cr1_1.sp deleted file mode 100644 index de94a0a1e3..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_telescopic_LG_load_biasp_cr1_1.sp +++ /dev/null @@ -1,62 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_telescopic -* View Name: schematic -* Netlisted on: Sep 11 21:39:36 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_telescopic -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_telescopic Vbiasn Vbiasp2 Vinn Vinp Voutp -*.PININFO Vbiasn:I Vbiasp2:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net11 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net13 Vinn net11 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net11 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net13 Vbiasp2 net016 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp Vbiasp2 net014 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net014 net13 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net016 net13 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasp Biasn Vbiasp1 Vbiasp2 -*.PININFO Biasn:I Vbiasp1:O Vbiasp2:O -MM0 Vbiasp2 Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp2 Vbiasp2 Vbiasp1 vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp1 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR1_1 Vbiasn -*.PININFO Vbiasn:O -RRF vdd! Vbiasn res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp2 Vinn Vinp Voutp single_ended_telescopic -xiLG_load_biasp Biasn LG_Vbiasp1 LG_Vbiasp2 LG_load_biasp -xibCR1_1 Biasn CR1_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_telescopic_LG_load_biasp_cr2_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_telescopic_LG_load_biasp_cr2_2.sp deleted file mode 100644 index 3ff1cdef3b..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_telescopic_LG_load_biasp_cr2_2.sp +++ /dev/null @@ -1,65 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_telescopic -* View Name: schematic -* Netlisted on: Sep 11 21:39:36 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_telescopic -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_telescopic Vbiasn Vbiasp2 Vinn Vinp Voutp -*.PININFO Vbiasn:I Vbiasp2:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net11 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net13 Vinn net11 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net11 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net13 Vbiasp2 net016 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp Vbiasp2 net014 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net014 net13 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net016 net13 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasp Biasn Vbiasp1 Vbiasp2 -*.PININFO Biasn:I Vbiasp1:O Vbiasp2:O -MM0 Vbiasp2 Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp2 Vbiasp2 Vbiasp1 vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp1 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR2_2_wilson Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -RR0 Vbiasn gnd! res=rK -MM2 Vbiasp net12 Vbiasn gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp2 Vinn Vinp Voutp single_ended_telescopic -xiLG_load_biasp Biasn LG_Vbiasp1 LG_Vbiasp2 LG_load_biasp -xibCR2_2_wilson Biasn Vbiasp CR2_2_wilson -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_telescopic_LG_load_biasp_cr3_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_telescopic_LG_load_biasp_cr3_2.sp deleted file mode 100644 index cc21af7d23..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_telescopic_LG_load_biasp_cr3_2.sp +++ /dev/null @@ -1,65 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_telescopic -* View Name: schematic -* Netlisted on: Sep 11 21:39:36 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_telescopic -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_telescopic Vbiasn Vbiasp2 Vinn Vinp Voutp -*.PININFO Vbiasn:I Vbiasp2:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net11 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net13 Vinn net11 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net11 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net13 Vbiasp2 net016 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp Vbiasp2 net014 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net014 net13 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net016 net13 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasp Biasn Vbiasp1 Vbiasp2 -*.PININFO Biasn:I Vbiasp1:O Vbiasp2:O -MM0 Vbiasp2 Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp2 Vbiasp2 Vbiasp1 vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp1 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR3_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 net15 gnd! res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp2 Vinn Vinp Voutp single_ended_telescopic -xiLG_load_biasp Biasn LG_Vbiasp1 LG_Vbiasp2 LG_load_biasp -xibCR3_2 Biasn Vbiasp CR3_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_telescopic_LG_load_biasp_cr4_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_telescopic_LG_load_biasp_cr4_2.sp deleted file mode 100644 index 1efe53a0cd..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_telescopic_LG_load_biasp_cr4_2.sp +++ /dev/null @@ -1,70 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_telescopic -* View Name: schematic -* Netlisted on: Sep 11 21:39:36 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_telescopic -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_telescopic Vbiasn Vbiasp2 Vinn Vinp Voutp -*.PININFO Vbiasn:I Vbiasp2:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net11 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net13 Vinn net11 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net11 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net13 Vbiasp2 net016 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp Vbiasp2 net014 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net014 net13 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net016 net13 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasp Biasn Vbiasp1 Vbiasp2 -*.PININFO Biasn:I Vbiasp1:O Vbiasp2:O -MM0 Vbiasp2 Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp2 Vbiasp2 Vbiasp1 vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp1 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR4_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM11 net023 net024 Vbiasn gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM8 net025 net010 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM9 net024 net024 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM7 net010 net010 net025 gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net025 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 net024 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net010 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp2 Vinn Vinp Voutp single_ended_telescopic -xiLG_load_biasp Biasn LG_Vbiasp1 LG_Vbiasp2 LG_load_biasp -xibCR4_2 Biasn Vbiasp CR4_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_telescopic_LG_load_biasp_cr5_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_telescopic_LG_load_biasp_cr5_2.sp deleted file mode 100644 index a98668cb77..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_telescopic_LG_load_biasp_cr5_2.sp +++ /dev/null @@ -1,67 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_telescopic -* View Name: schematic -* Netlisted on: Sep 11 21:39:36 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_telescopic -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_telescopic Vbiasn Vbiasp2 Vinn Vinp Voutp -*.PININFO Vbiasn:I Vbiasp2:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net11 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net13 Vinn net11 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net11 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net13 Vbiasp2 net016 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp Vbiasp2 net014 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net014 net13 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net016 net13 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasp Biasn Vbiasp1 Vbiasp2 -*.PININFO Biasn:I Vbiasp1:O Vbiasp2:O -MM0 Vbiasp2 Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp2 Vbiasp2 Vbiasp1 vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp1 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR5_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM5 net014 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net014 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp2 Vinn Vinp Voutp single_ended_telescopic -xiLG_load_biasp Biasn LG_Vbiasp1 LG_Vbiasp2 LG_load_biasp -xibCR5_2 Biasn Vbiasp CR5_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_telescopic_LG_load_biasp_cr7_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_telescopic_LG_load_biasp_cr7_1.sp deleted file mode 100644 index 0f2368c072..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_telescopic_LG_load_biasp_cr7_1.sp +++ /dev/null @@ -1,65 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_telescopic -* View Name: schematic -* Netlisted on: Sep 11 21:39:36 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_telescopic -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_telescopic Vbiasn Vbiasp2 Vinn Vinp Voutp -*.PININFO Vbiasn:I Vbiasp2:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net11 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net13 Vinn net11 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net11 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net13 Vbiasp2 net016 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp Vbiasp2 net014 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net014 net13 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net016 net13 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasp Biasn Vbiasp1 Vbiasp2 -*.PININFO Biasn:I Vbiasp1:O Vbiasp2:O -MM0 Vbiasp2 Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp2 Vbiasp2 Vbiasp1 vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp1 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR7_1 Vbiasn -*.PININFO Vbiasn:O -RR1 Vbiasn net7 res=rK -RR0 vdd! net7 res=rK -RRF vdd! Vbiasn res=rK -MM1 net7 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp2 Vinn Vinp Voutp single_ended_telescopic -xiLG_load_biasp Biasn LG_Vbiasp1 LG_Vbiasp2 LG_load_biasp -xibCR7_1 Biasn CR7_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_telescopic_LG_load_biasp_cr9_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_telescopic_LG_load_biasp_cr9_1.sp deleted file mode 100644 index 45feecf181..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_telescopic_LG_load_biasp_cr9_1.sp +++ /dev/null @@ -1,63 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_telescopic -* View Name: schematic -* Netlisted on: Sep 11 21:39:36 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_telescopic -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_telescopic Vbiasn Vbiasp2 Vinn Vinp Voutp -*.PININFO Vbiasn:I Vbiasp2:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net11 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net13 Vinn net11 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net11 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net13 Vbiasp2 net016 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp Vbiasp2 net014 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net014 net13 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net016 net13 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasp Biasn Vbiasp1 Vbiasp2 -*.PININFO Biasn:I Vbiasp1:O Vbiasp2:O -MM0 Vbiasp2 Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp2 Vbiasp2 Vbiasp1 vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp1 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR9_1 Vbiasn -*.PININFO Vbiasn:O -RR1 net05 gnd! res=rK -RRF vdd! Vbiasn res=rK -MM0 Vbiasn Vbiasn net05 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn LG_Vbiasp2 Vinn Vinp Voutp single_ended_telescopic -xiLG_load_biasp Biasn LG_Vbiasp1 LG_Vbiasp2 LG_load_biasp -xibCR9_1 Biasn CR9_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_telescopic_pmos_LG_load_biasn_LV_cr13_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_telescopic_pmos_LG_load_biasn_LV_cr13_1.sp deleted file mode 100644 index e0009588be..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_telescopic_pmos_LG_load_biasn_LV_cr13_1.sp +++ /dev/null @@ -1,64 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_telescopic_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:39:52 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_telescopic_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_telescopic_pmos Vbiasn2 Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasn2:I Vbiasp:I Vinn:I Vinp:I Voutp:O -MM1 net14 Vbiasn2 net013 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vbiasn2 net10 gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net10 net14 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net013 net14 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM5 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 Voutp Vinn net12 net19 pmos_rvt w=WA l=LA nfin=nA -MM6 net14 Vinp net12 net19 pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasn_LV Vbiasn2 Biasp -*.PININFO Biasp:I Vbiasn2:O -MM13 net9 Vbiasn2 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM15 Vbiasn2 Vbiasn2 net9 gnd! nmos_rvt w=WA l=LA nfin=nA -MM14 Vbiasn2 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn2 LG_Vbiasp Vinn Vinp Voutp single_ended_telescopic_pmos -xiLG_load_biasn_LV Biasp LG_Vbiasn2 LG_load_biasn_LV -xibCR13_2 Biasn Biasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_telescopic_pmos_LG_load_biasn_LV_cr13_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_telescopic_pmos_LG_load_biasn_LV_cr13_2.sp deleted file mode 100644 index e0009588be..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_telescopic_pmos_LG_load_biasn_LV_cr13_2.sp +++ /dev/null @@ -1,64 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_telescopic_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:39:52 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_telescopic_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_telescopic_pmos Vbiasn2 Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasn2:I Vbiasp:I Vinn:I Vinp:I Voutp:O -MM1 net14 Vbiasn2 net013 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vbiasn2 net10 gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net10 net14 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net013 net14 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM5 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 Voutp Vinn net12 net19 pmos_rvt w=WA l=LA nfin=nA -MM6 net14 Vinp net12 net19 pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasn_LV Vbiasn2 Biasp -*.PININFO Biasp:I Vbiasn2:O -MM13 net9 Vbiasn2 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM15 Vbiasn2 Vbiasn2 net9 gnd! nmos_rvt w=WA l=LA nfin=nA -MM14 Vbiasn2 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn2 LG_Vbiasp Vinn Vinp Voutp single_ended_telescopic_pmos -xiLG_load_biasn_LV Biasp LG_Vbiasn2 LG_load_biasn_LV -xibCR13_2 Biasn Biasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_telescopic_pmos_LG_load_biasn_LV_cr14_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_telescopic_pmos_LG_load_biasn_LV_cr14_2.sp deleted file mode 100644 index 45b0f82308..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_telescopic_pmos_LG_load_biasn_LV_cr14_2.sp +++ /dev/null @@ -1,65 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_telescopic_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:39:52 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_telescopic_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_telescopic_pmos Vbiasn2 Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasn2:I Vbiasp:I Vinn:I Vinp:I Voutp:O -MM1 net14 Vbiasn2 net013 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vbiasn2 net10 gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net10 net14 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net013 net14 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM5 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 Voutp Vinn net12 net19 pmos_rvt w=WA l=LA nfin=nA -MM6 net14 Vinp net12 net19 pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasn_LV Vbiasn2 Biasp -*.PININFO Biasp:I Vbiasn2:O -MM13 net9 Vbiasn2 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM15 Vbiasn2 Vbiasn2 net9 gnd! nmos_rvt w=WA l=LA nfin=nA -MM14 Vbiasn2 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR14_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net010 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 Vbiasn net010 res=rK -.ENDS - - -xiota LG_Vbiasn2 LG_Vbiasp Vinn Vinp Voutp single_ended_telescopic_pmos -xiLG_load_biasn_LV Biasp LG_Vbiasn2 LG_load_biasn_LV -xibCR14_2 Biasn Biasp CR14_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_telescopic_pmos_LG_load_biasn_LV_cr15_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_telescopic_pmos_LG_load_biasn_LV_cr15_1.sp deleted file mode 100644 index f85d3758e0..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_telescopic_pmos_LG_load_biasn_LV_cr15_1.sp +++ /dev/null @@ -1,62 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_telescopic_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:39:52 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_telescopic_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_telescopic_pmos Vbiasn2 Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasn2:I Vbiasp:I Vinn:I Vinp:I Voutp:O -MM1 net14 Vbiasn2 net013 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vbiasn2 net10 gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net10 net14 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net013 net14 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM5 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 Voutp Vinn net12 net19 pmos_rvt w=WA l=LA nfin=nA -MM6 net14 Vinp net12 net19 pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasn_LV Vbiasn2 Biasp -*.PININFO Biasp:I Vbiasn2:O -MM13 net9 Vbiasn2 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM15 Vbiasn2 Vbiasn2 net9 gnd! nmos_rvt w=WA l=LA nfin=nA -MM14 Vbiasn2 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR15_1 Vbiasp -*.PININFO Vbiasp:O -RR1 Vbiasp gnd! res=rK -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn2 LG_Vbiasp Vinn Vinp Voutp single_ended_telescopic_pmos -xiLG_load_biasn_LV Biasp LG_Vbiasn2 LG_load_biasn_LV -xibCR15_1 Biasp CR15_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_telescopic_pmos_LG_load_biasn_LV_cr16_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_telescopic_pmos_LG_load_biasn_LV_cr16_1.sp deleted file mode 100644 index 3f231c100f..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_telescopic_pmos_LG_load_biasn_LV_cr16_1.sp +++ /dev/null @@ -1,63 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_telescopic_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:39:52 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_telescopic_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_telescopic_pmos Vbiasn2 Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasn2:I Vbiasp:I Vinn:I Vinp:I Voutp:O -MM1 net14 Vbiasn2 net013 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vbiasn2 net10 gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net10 net14 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net013 net14 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM5 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 Voutp Vinn net12 net19 pmos_rvt w=WA l=LA nfin=nA -MM6 net14 Vinp net12 net19 pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasn_LV Vbiasn2 Biasp -*.PININFO Biasp:I Vbiasn2:O -MM13 net9 Vbiasn2 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM15 Vbiasn2 Vbiasn2 net9 gnd! nmos_rvt w=WA l=LA nfin=nA -MM14 Vbiasn2 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR16_1 Vbiasp -*.PININFO Vbiasp:O -RR0 vdd! net6 res=rK -RR1 Vbiasp gnd! res=rK -MM2 Vbiasp Vbiasp net6 vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn2 LG_Vbiasp Vinn Vinp Voutp single_ended_telescopic_pmos -xiLG_load_biasn_LV Biasp LG_Vbiasn2 LG_load_biasn_LV -xibCR16_1 Biasp CR16_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_telescopic_pmos_LG_load_biasn_LV_cr2_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_telescopic_pmos_LG_load_biasn_LV_cr2_2.sp deleted file mode 100644 index 5ecea72b97..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_telescopic_pmos_LG_load_biasn_LV_cr2_2.sp +++ /dev/null @@ -1,65 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_telescopic_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:39:52 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_telescopic_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_telescopic_pmos Vbiasn2 Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasn2:I Vbiasp:I Vinn:I Vinp:I Voutp:O -MM1 net14 Vbiasn2 net013 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vbiasn2 net10 gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net10 net14 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net013 net14 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM5 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 Voutp Vinn net12 net19 pmos_rvt w=WA l=LA nfin=nA -MM6 net14 Vinp net12 net19 pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasn_LV Vbiasn2 Biasp -*.PININFO Biasp:I Vbiasn2:O -MM13 net9 Vbiasn2 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM15 Vbiasn2 Vbiasn2 net9 gnd! nmos_rvt w=WA l=LA nfin=nA -MM14 Vbiasn2 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR2_2_wilson Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -RR0 Vbiasn gnd! res=rK -MM2 Vbiasp net12 Vbiasn gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn2 LG_Vbiasp Vinn Vinp Voutp single_ended_telescopic_pmos -xiLG_load_biasn_LV Biasp LG_Vbiasn2 LG_load_biasn_LV -xibCR2_2_wilson Biasn Biasp CR2_2_wilson -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_telescopic_pmos_LG_load_biasn_LV_cr3_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_telescopic_pmos_LG_load_biasn_LV_cr3_2.sp deleted file mode 100644 index 2b99b04411..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_telescopic_pmos_LG_load_biasn_LV_cr3_2.sp +++ /dev/null @@ -1,65 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_telescopic_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:39:52 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_telescopic_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_telescopic_pmos Vbiasn2 Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasn2:I Vbiasp:I Vinn:I Vinp:I Voutp:O -MM1 net14 Vbiasn2 net013 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vbiasn2 net10 gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net10 net14 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net013 net14 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM5 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 Voutp Vinn net12 net19 pmos_rvt w=WA l=LA nfin=nA -MM6 net14 Vinp net12 net19 pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasn_LV Vbiasn2 Biasp -*.PININFO Biasp:I Vbiasn2:O -MM13 net9 Vbiasn2 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM15 Vbiasn2 Vbiasn2 net9 gnd! nmos_rvt w=WA l=LA nfin=nA -MM14 Vbiasn2 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR3_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 net15 gnd! res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn2 LG_Vbiasp Vinn Vinp Voutp single_ended_telescopic_pmos -xiLG_load_biasn_LV Biasp LG_Vbiasn2 LG_load_biasn_LV -xibCR3_2 Biasn Biasp CR3_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_telescopic_pmos_LG_load_biasn_LV_cr4_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_telescopic_pmos_LG_load_biasn_LV_cr4_2.sp deleted file mode 100644 index 399cd12288..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_telescopic_pmos_LG_load_biasn_LV_cr4_2.sp +++ /dev/null @@ -1,70 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_telescopic_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:39:52 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_telescopic_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_telescopic_pmos Vbiasn2 Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasn2:I Vbiasp:I Vinn:I Vinp:I Voutp:O -MM1 net14 Vbiasn2 net013 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vbiasn2 net10 gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net10 net14 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net013 net14 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM5 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 Voutp Vinn net12 net19 pmos_rvt w=WA l=LA nfin=nA -MM6 net14 Vinp net12 net19 pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasn_LV Vbiasn2 Biasp -*.PININFO Biasp:I Vbiasn2:O -MM13 net9 Vbiasn2 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM15 Vbiasn2 Vbiasn2 net9 gnd! nmos_rvt w=WA l=LA nfin=nA -MM14 Vbiasn2 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR4_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM11 net023 net024 Vbiasn gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM8 net025 net010 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM9 net024 net024 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM7 net010 net010 net025 gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net025 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 net024 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net010 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn2 LG_Vbiasp Vinn Vinp Voutp single_ended_telescopic_pmos -xiLG_load_biasn_LV Biasp LG_Vbiasn2 LG_load_biasn_LV -xibCR4_2 Biasn Biasp CR4_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_telescopic_pmos_LG_load_biasn_LV_cr5_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_telescopic_pmos_LG_load_biasn_LV_cr5_2.sp deleted file mode 100644 index ed63d7e22f..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_telescopic_pmos_LG_load_biasn_LV_cr5_2.sp +++ /dev/null @@ -1,67 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_telescopic_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:39:52 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_telescopic_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_telescopic_pmos Vbiasn2 Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasn2:I Vbiasp:I Vinn:I Vinp:I Voutp:O -MM1 net14 Vbiasn2 net013 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vbiasn2 net10 gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net10 net14 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net013 net14 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM5 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 Voutp Vinn net12 net19 pmos_rvt w=WA l=LA nfin=nA -MM6 net14 Vinp net12 net19 pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasn_LV Vbiasn2 Biasp -*.PININFO Biasp:I Vbiasn2:O -MM13 net9 Vbiasn2 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM15 Vbiasn2 Vbiasn2 net9 gnd! nmos_rvt w=WA l=LA nfin=nA -MM14 Vbiasn2 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR5_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM5 net014 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net014 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn2 LG_Vbiasp Vinn Vinp Voutp single_ended_telescopic_pmos -xiLG_load_biasn_LV Biasp LG_Vbiasn2 LG_load_biasn_LV -xibCR5_2 Biasn Biasp CR5_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_telescopic_pmos_LG_load_biasn_LV_cr6_3.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_telescopic_pmos_LG_load_biasn_LV_cr6_3.sp deleted file mode 100644 index 18dbf82502..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_telescopic_pmos_LG_load_biasn_LV_cr6_3.sp +++ /dev/null @@ -1,67 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_telescopic_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:39:52 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_telescopic_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_telescopic_pmos Vbiasn2 Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasn2:I Vbiasp:I Vinn:I Vinp:I Voutp:O -MM1 net14 Vbiasn2 net013 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vbiasn2 net10 gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net10 net14 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net013 net14 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM5 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 Voutp Vinn net12 net19 pmos_rvt w=WA l=LA nfin=nA -MM6 net14 Vinp net12 net19 pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_load_biasn_LV Vbiasn2 Biasp -*.PININFO Biasp:I Vbiasn2:O -MM13 net9 Vbiasn2 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM15 Vbiasn2 Vbiasn2 net9 gnd! nmos_rvt w=WA l=LA nfin=nA -MM14 Vbiasn2 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR6_3 Vbiasn1 Vbiasn2 Vbiasp -*.PININFO Vbiasn1:O Vbiasn2:O Vbiasp:O -MM2 Vbiasp Vbiasn2 Vbiasn1 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn2 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 Vbiasn1 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM5 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn2 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn2 LG_Vbiasp Vinn Vinp Voutp single_ended_telescopic_pmos -xiLG_load_biasn_LV Biasp LG_Vbiasn2 LG_load_biasn_LV -xibCR6_3 Biasn1 Biasn2 Biasp CR6_3 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_nmos_cr13_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_nmos_cr13_1.sp deleted file mode 100644 index 7a587a889a..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_nmos_cr13_1.sp +++ /dev/null @@ -1,65 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_two_stage -* View Name: schematic -* Netlisted on: Sep 11 21:10:37 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_two_stage -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_two_stage Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM1 net16 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 net9 net12 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net16 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net16 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos Biasp Vbiasn -*.PININFO Biasp:I Vbiasn:O -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_two_stage -xiLG_nmos Biasp LG_Vbiasn LG_nmos -xibCR13_2 Biasn Biasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_nmos_cr13_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_nmos_cr13_2.sp deleted file mode 100644 index 7a587a889a..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_nmos_cr13_2.sp +++ /dev/null @@ -1,65 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_two_stage -* View Name: schematic -* Netlisted on: Sep 11 21:10:37 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_two_stage -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_two_stage Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM1 net16 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 net9 net12 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net16 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net16 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos Biasp Vbiasn -*.PININFO Biasp:I Vbiasn:O -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_two_stage -xiLG_nmos Biasp LG_Vbiasn LG_nmos -xibCR13_2 Biasn Biasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_nmos_cr14_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_nmos_cr14_2.sp deleted file mode 100644 index 4469940a3a..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_nmos_cr14_2.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_two_stage -* View Name: schematic -* Netlisted on: Sep 11 21:10:37 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_two_stage -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_two_stage Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM1 net16 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 net9 net12 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net16 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net16 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos Biasp Vbiasn -*.PININFO Biasp:I Vbiasn:O -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR14_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net010 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 Vbiasn net010 res=rK -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_two_stage -xiLG_nmos Biasp LG_Vbiasn LG_nmos -xibCR14_2 Biasn Biasp CR14_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_nmos_cr15_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_nmos_cr15_1.sp deleted file mode 100644 index 0c9562d2f8..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_nmos_cr15_1.sp +++ /dev/null @@ -1,63 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_two_stage -* View Name: schematic -* Netlisted on: Sep 11 21:10:37 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_two_stage -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_two_stage Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM1 net16 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 net9 net12 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net16 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net16 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos Biasp Vbiasn -*.PININFO Biasp:I Vbiasn:O -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR15_1 Vbiasp -*.PININFO Vbiasp:O -RR1 Vbiasp gnd! res=rK -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_two_stage -xiLG_nmos Biasp LG_Vbiasn LG_nmos -xibCR15_1 Biasp CR15_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_nmos_cr16_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_nmos_cr16_1.sp deleted file mode 100644 index 7088b16abc..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_nmos_cr16_1.sp +++ /dev/null @@ -1,64 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_two_stage -* View Name: schematic -* Netlisted on: Sep 11 21:10:37 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_two_stage -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_two_stage Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM1 net16 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 net9 net12 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net16 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net16 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos Biasp Vbiasn -*.PININFO Biasp:I Vbiasn:O -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR16_1 Vbiasp -*.PININFO Vbiasp:O -RR0 vdd! net6 res=rK -RR1 Vbiasp gnd! res=rK -MM2 Vbiasp Vbiasp net6 vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_two_stage -xiLG_nmos Biasp LG_Vbiasn LG_nmos -xibCR16_1 Biasp CR16_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_nmos_cr2_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_nmos_cr2_2.sp deleted file mode 100644 index 17ba1c6c94..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_nmos_cr2_2.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_two_stage -* View Name: schematic -* Netlisted on: Sep 11 21:10:37 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_two_stage -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_two_stage Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM1 net16 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 net9 net12 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net16 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net16 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos Biasp Vbiasn -*.PININFO Biasp:I Vbiasn:O -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR2_2_wilson Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -RR0 Vbiasn gnd! res=rK -MM2 Vbiasp net12 Vbiasn gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_two_stage -xiLG_nmos Biasp LG_Vbiasn LG_nmos -xibCR2_2_wilson Biasn Biasp CR2_2_wilson -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_nmos_cr3_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_nmos_cr3_2.sp deleted file mode 100644 index b9c42ab9c8..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_nmos_cr3_2.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_two_stage -* View Name: schematic -* Netlisted on: Sep 11 21:10:37 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_two_stage -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_two_stage Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM1 net16 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 net9 net12 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net16 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net16 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos Biasp Vbiasn -*.PININFO Biasp:I Vbiasn:O -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR3_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 net15 gnd! res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_two_stage -xiLG_nmos Biasp LG_Vbiasn LG_nmos -xibCR3_2 Biasn Biasp CR3_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_nmos_cr4_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_nmos_cr4_2.sp deleted file mode 100644 index b26debcabc..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_nmos_cr4_2.sp +++ /dev/null @@ -1,71 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_two_stage -* View Name: schematic -* Netlisted on: Sep 11 21:10:37 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_two_stage -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_two_stage Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM1 net16 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 net9 net12 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net16 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net16 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos Biasp Vbiasn -*.PININFO Biasp:I Vbiasn:O -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR4_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM11 net023 net024 Vbiasn gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM8 net025 net010 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM9 net024 net024 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM7 net010 net010 net025 gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net025 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 net024 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net010 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_two_stage -xiLG_nmos Biasp LG_Vbiasn LG_nmos -xibCR4_2 Biasn Biasp CR4_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_nmos_cr5_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_nmos_cr5_2.sp deleted file mode 100644 index 62b24bae4b..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_nmos_cr5_2.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_two_stage -* View Name: schematic -* Netlisted on: Sep 11 21:10:37 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_two_stage -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_two_stage Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM1 net16 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 net9 net12 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net16 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net16 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos Biasp Vbiasn -*.PININFO Biasp:I Vbiasn:O -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR5_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM5 net014 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net014 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_two_stage -xiLG_nmos Biasp LG_Vbiasn LG_nmos -xibCR5_2 Biasn Biasp CR5_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_nmos_cr6_3.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_nmos_cr6_3.sp deleted file mode 100644 index fd6a239fc7..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_nmos_cr6_3.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_two_stage -* View Name: schematic -* Netlisted on: Sep 11 21:10:37 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_two_stage -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_two_stage Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM1 net16 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 net9 net12 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net16 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net16 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos Biasp Vbiasn -*.PININFO Biasp:I Vbiasn:O -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR6_3 Vbiasn1 Vbiasn2 Vbiasp -*.PININFO Vbiasn1:O Vbiasn2:O Vbiasp:O -MM2 Vbiasp Vbiasn2 Vbiasn1 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn2 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 Vbiasn1 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM5 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn2 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_two_stage -xiLG_nmos Biasp LG_Vbiasn LG_nmos -xibCR6_3 Biasn1 Biasn2 Biasp CR6_3 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_nmos_l1_cr11_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_nmos_l1_cr11_1.sp deleted file mode 100644 index f729ca3706..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_nmos_l1_cr11_1.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_two_stage -* View Name: schematic -* Netlisted on: Sep 11 21:10:37 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_two_stage -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_two_stage Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM1 net16 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 net9 net12 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net16 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net16 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR11_1 Vbiasn -*.PININFO Vbiasn:O -RRF vdd! Vbiasn res=rK -MM1 net9 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net9 net9 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn net9 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_two_stage -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR11_1 Biasn CR11_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_nmos_l1_cr12_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_nmos_l1_cr12_1.sp deleted file mode 100644 index ee92dd9553..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_nmos_l1_cr12_1.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_two_stage -* View Name: schematic -* Netlisted on: Sep 11 21:10:37 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_two_stage -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_two_stage Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM1 net16 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 net9 net12 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net16 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net16 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR12_1 Vbiasn -*.PININFO Vbiasn:O -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 net10 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn net10 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RRF vdd! Vbiasn res=rK -RR0 vdd! net10 res=rK -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_two_stage -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR12_1 Biasn CR12_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_nmos_l1_cr13_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_nmos_l1_cr13_1.sp deleted file mode 100644 index a7d3541ac7..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_nmos_l1_cr13_1.sp +++ /dev/null @@ -1,67 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_two_stage -* View Name: schematic -* Netlisted on: Sep 11 21:10:37 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_two_stage -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_two_stage Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM1 net16 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 net9 net12 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net16 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net16 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_two_stage -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR13_2 Biasn Vbiasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_nmos_l1_cr13_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_nmos_l1_cr13_2.sp deleted file mode 100644 index a7d3541ac7..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_nmos_l1_cr13_2.sp +++ /dev/null @@ -1,67 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_two_stage -* View Name: schematic -* Netlisted on: Sep 11 21:10:37 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_two_stage -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_two_stage Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM1 net16 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 net9 net12 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net16 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net16 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_two_stage -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR13_2 Biasn Vbiasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_nmos_l1_cr14_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_nmos_l1_cr14_2.sp deleted file mode 100644 index 362b50b421..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_nmos_l1_cr14_2.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_two_stage -* View Name: schematic -* Netlisted on: Sep 11 21:10:37 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_two_stage -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_two_stage Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM1 net16 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 net9 net12 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net16 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net16 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR14_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net010 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 Vbiasn net010 res=rK -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_two_stage -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR14_2 Biasn Vbiasp CR14_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_nmos_l1_cr1_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_nmos_l1_cr1_1.sp deleted file mode 100644 index ae0562b907..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_nmos_l1_cr1_1.sp +++ /dev/null @@ -1,65 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_two_stage -* View Name: schematic -* Netlisted on: Sep 11 21:10:37 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_two_stage -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_two_stage Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM1 net16 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 net9 net12 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net16 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net16 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR1_1 Vbiasn -*.PININFO Vbiasn:O -RRF vdd! Vbiasn res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_two_stage -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR1_1 Biasn CR1_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_nmos_l1_cr2_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_nmos_l1_cr2_2.sp deleted file mode 100644 index 1eb757757c..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_nmos_l1_cr2_2.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_two_stage -* View Name: schematic -* Netlisted on: Sep 11 21:10:37 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_two_stage -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_two_stage Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM1 net16 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 net9 net12 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net16 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net16 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR2_2_wilson Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -RR0 Vbiasn gnd! res=rK -MM2 Vbiasp net12 Vbiasn gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_two_stage -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR2_2_wilson Biasn Vbiasp CR2_2_wilson -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_nmos_l1_cr3_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_nmos_l1_cr3_2.sp deleted file mode 100644 index c940261b90..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_nmos_l1_cr3_2.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_two_stage -* View Name: schematic -* Netlisted on: Sep 11 21:10:37 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_two_stage -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_two_stage Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM1 net16 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 net9 net12 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net16 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net16 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR3_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 net15 gnd! res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_two_stage -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR3_2 Biasn Vbiasp CR3_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_nmos_l1_cr4_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_nmos_l1_cr4_2.sp deleted file mode 100644 index dc9841ad98..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_nmos_l1_cr4_2.sp +++ /dev/null @@ -1,73 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_two_stage -* View Name: schematic -* Netlisted on: Sep 11 21:10:37 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_two_stage -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_two_stage Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM1 net16 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 net9 net12 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net16 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net16 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR4_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM11 net023 net024 Vbiasn gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM8 net025 net010 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM9 net024 net024 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM7 net010 net010 net025 gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net025 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 net024 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net010 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_two_stage -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR4_2 Biasn Vbiasp CR4_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_nmos_l1_cr5_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_nmos_l1_cr5_2.sp deleted file mode 100644 index e6842576c6..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_nmos_l1_cr5_2.sp +++ /dev/null @@ -1,70 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_two_stage -* View Name: schematic -* Netlisted on: Sep 11 21:10:37 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_two_stage -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_two_stage Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM1 net16 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 net9 net12 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net16 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net16 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR5_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM5 net014 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net014 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_two_stage -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR5_2 Biasn Vbiasp CR5_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_nmos_l1_cr7_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_nmos_l1_cr7_1.sp deleted file mode 100644 index aee3b4962e..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_nmos_l1_cr7_1.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_two_stage -* View Name: schematic -* Netlisted on: Sep 11 21:10:37 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_two_stage -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_two_stage Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM1 net16 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 net9 net12 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net16 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net16 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR7_1 Vbiasn -*.PININFO Vbiasn:O -RR1 Vbiasn net7 res=rK -RR0 vdd! net7 res=rK -RRF vdd! Vbiasn res=rK -MM1 net7 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_two_stage -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR7_1 Biasn CR7_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_nmos_l1_cr9_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_nmos_l1_cr9_1.sp deleted file mode 100644 index 7b5b52ca77..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_nmos_l1_cr9_1.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_two_stage -* View Name: schematic -* Netlisted on: Sep 11 21:10:37 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_two_stage -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_two_stage Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM1 net16 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 net9 net12 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net16 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net16 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR9_1 Vbiasn -*.PININFO Vbiasn:O -RR1 net05 gnd! res=rK -RRF vdd! Vbiasn res=rK -MM0 Vbiasn Vbiasn net05 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_two_stage -xiLG_nmos_l1 Biasn LG_Vbiasn LG_Vbiasp LG_nmos_l1 -xibCR9_1 Biasn CR9_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_npmos_cr11_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_npmos_cr11_1.sp deleted file mode 100644 index 708abf2902..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_npmos_cr11_1.sp +++ /dev/null @@ -1,70 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_two_stage -* View Name: schematic -* Netlisted on: Sep 11 21:10:37 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_two_stage -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_two_stage Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM1 net16 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 net9 net12 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net16 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net16 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR11_1 Vbiasn -*.PININFO Vbiasn:O -RRF vdd! Vbiasn res=rK -MM1 net9 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net9 net9 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn net9 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_two_stage -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR11_1 Biasn CR11_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_npmos_cr12_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_npmos_cr12_1.sp deleted file mode 100644 index eb73ba47e4..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_npmos_cr12_1.sp +++ /dev/null @@ -1,70 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_two_stage -* View Name: schematic -* Netlisted on: Sep 11 21:10:37 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_two_stage -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_two_stage Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM1 net16 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 net9 net12 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net16 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net16 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR12_1 Vbiasn -*.PININFO Vbiasn:O -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 net10 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn net10 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RRF vdd! Vbiasn res=rK -RR0 vdd! net10 res=rK -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_two_stage -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR12_1 Biasn CR12_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_npmos_cr13_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_npmos_cr13_1.sp deleted file mode 100644 index 67c2ebedb2..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_npmos_cr13_1.sp +++ /dev/null @@ -1,69 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_two_stage -* View Name: schematic -* Netlisted on: Sep 11 21:10:37 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_two_stage -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_two_stage Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM1 net16 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 net9 net12 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net16 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net16 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_two_stage -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR13_2 Biasn Vbiasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_npmos_cr13_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_npmos_cr13_2.sp deleted file mode 100644 index 67c2ebedb2..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_npmos_cr13_2.sp +++ /dev/null @@ -1,69 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_two_stage -* View Name: schematic -* Netlisted on: Sep 11 21:10:37 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_two_stage -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_two_stage Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM1 net16 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 net9 net12 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net16 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net16 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_two_stage -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR13_2 Biasn Vbiasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_npmos_cr14_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_npmos_cr14_2.sp deleted file mode 100644 index 0c36450254..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_npmos_cr14_2.sp +++ /dev/null @@ -1,70 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_two_stage -* View Name: schematic -* Netlisted on: Sep 11 21:10:37 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_two_stage -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_two_stage Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM1 net16 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 net9 net12 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net16 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net16 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR14_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net010 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 Vbiasn net010 res=rK -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_two_stage -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR14_2 Biasn Vbiasp CR14_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_npmos_cr1_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_npmos_cr1_1.sp deleted file mode 100644 index 7b5bf5d929..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_npmos_cr1_1.sp +++ /dev/null @@ -1,67 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_two_stage -* View Name: schematic -* Netlisted on: Sep 11 21:10:37 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_two_stage -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_two_stage Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM1 net16 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 net9 net12 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net16 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net16 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR1_1 Vbiasn -*.PININFO Vbiasn:O -RRF vdd! Vbiasn res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_two_stage -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR1_1 Biasn CR1_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_npmos_cr2_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_npmos_cr2_2.sp deleted file mode 100644 index a1f18dd6ac..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_npmos_cr2_2.sp +++ /dev/null @@ -1,70 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_two_stage -* View Name: schematic -* Netlisted on: Sep 11 21:10:37 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_two_stage -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_two_stage Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM1 net16 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 net9 net12 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net16 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net16 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR2_2_wilson Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -RR0 Vbiasn gnd! res=rK -MM2 Vbiasp net12 Vbiasn gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_two_stage -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR2_2_wilson Biasn Vbiasp CR2_2_wilson -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_npmos_cr3_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_npmos_cr3_2.sp deleted file mode 100644 index 2f1636a243..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_npmos_cr3_2.sp +++ /dev/null @@ -1,70 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_two_stage -* View Name: schematic -* Netlisted on: Sep 11 21:10:37 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_two_stage -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_two_stage Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM1 net16 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 net9 net12 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net16 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net16 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR3_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 net15 gnd! res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_two_stage -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR3_2 Biasn Vbiasp CR3_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_npmos_cr4_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_npmos_cr4_2.sp deleted file mode 100644 index 0083d17e43..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_npmos_cr4_2.sp +++ /dev/null @@ -1,75 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_two_stage -* View Name: schematic -* Netlisted on: Sep 11 21:10:37 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_two_stage -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_two_stage Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM1 net16 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 net9 net12 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net16 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net16 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR4_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM11 net023 net024 Vbiasn gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM8 net025 net010 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM9 net024 net024 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM7 net010 net010 net025 gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net025 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 net024 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net010 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_two_stage -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR4_2 Biasn Vbiasp CR4_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_npmos_cr5_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_npmos_cr5_2.sp deleted file mode 100644 index 7644bb3704..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_npmos_cr5_2.sp +++ /dev/null @@ -1,72 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_two_stage -* View Name: schematic -* Netlisted on: Sep 11 21:10:37 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_two_stage -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_two_stage Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM1 net16 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 net9 net12 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net16 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net16 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR5_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM5 net014 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net014 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_two_stage -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR5_2 Biasn Vbiasp CR5_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_npmos_cr7_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_npmos_cr7_1.sp deleted file mode 100644 index 86bacedf64..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_npmos_cr7_1.sp +++ /dev/null @@ -1,70 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_two_stage -* View Name: schematic -* Netlisted on: Sep 11 21:10:37 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_two_stage -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_two_stage Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM1 net16 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 net9 net12 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net16 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net16 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR7_1 Vbiasn -*.PININFO Vbiasn:O -RR1 Vbiasn net7 res=rK -RR0 vdd! net7 res=rK -RRF vdd! Vbiasn res=rK -MM1 net7 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_two_stage -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR7_1 Biasn CR7_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_npmos_cr9_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_npmos_cr9_1.sp deleted file mode 100644 index 58e70f5c3b..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_npmos_cr9_1.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_two_stage -* View Name: schematic -* Netlisted on: Sep 11 21:10:37 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_two_stage -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_two_stage Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM1 net16 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 net9 net12 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net16 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net16 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR9_1 Vbiasn -*.PININFO Vbiasn:O -RR1 net05 gnd! res=rK -RRF vdd! Vbiasn res=rK -MM0 Vbiasn Vbiasn net05 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_two_stage -xiLG_npmos Biasn LG_Vbiasn LG_Vbiasp LG_npmos -xibCR9_1 Biasn CR9_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_pmos_l1_cr13_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_pmos_l1_cr13_1.sp deleted file mode 100644 index 07bdf9cef1..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_pmos_l1_cr13_1.sp +++ /dev/null @@ -1,67 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_two_stage -* View Name: schematic -* Netlisted on: Sep 11 21:10:37 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_two_stage -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_two_stage Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM1 net16 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 net9 net12 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net16 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net16 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_two_stage -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR13_2 Biasn Biasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_pmos_l1_cr13_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_pmos_l1_cr13_2.sp deleted file mode 100644 index 07bdf9cef1..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_pmos_l1_cr13_2.sp +++ /dev/null @@ -1,67 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_two_stage -* View Name: schematic -* Netlisted on: Sep 11 21:10:37 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_two_stage -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_two_stage Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM1 net16 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 net9 net12 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net16 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net16 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_two_stage -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR13_2 Biasn Biasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_pmos_l1_cr14_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_pmos_l1_cr14_2.sp deleted file mode 100644 index c2ebece888..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_pmos_l1_cr14_2.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_two_stage -* View Name: schematic -* Netlisted on: Sep 11 21:10:37 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_two_stage -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_two_stage Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM1 net16 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 net9 net12 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net16 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net16 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR14_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net010 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 Vbiasn net010 res=rK -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_two_stage -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR14_2 Biasn Biasp CR14_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_pmos_l1_cr15_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_pmos_l1_cr15_1.sp deleted file mode 100644 index 11204d5b50..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_pmos_l1_cr15_1.sp +++ /dev/null @@ -1,65 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_two_stage -* View Name: schematic -* Netlisted on: Sep 11 21:10:37 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_two_stage -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_two_stage Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM1 net16 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 net9 net12 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net16 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net16 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR15_1 Vbiasp -*.PININFO Vbiasp:O -RR1 Vbiasp gnd! res=rK -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_two_stage -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR15_1 Biasp CR15_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_pmos_l1_cr16_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_pmos_l1_cr16_1.sp deleted file mode 100644 index 7d042ff7bc..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_pmos_l1_cr16_1.sp +++ /dev/null @@ -1,66 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_two_stage -* View Name: schematic -* Netlisted on: Sep 11 21:10:37 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_two_stage -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_two_stage Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM1 net16 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 net9 net12 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net16 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net16 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR16_1 Vbiasp -*.PININFO Vbiasp:O -RR0 vdd! net6 res=rK -RR1 Vbiasp gnd! res=rK -MM2 Vbiasp Vbiasp net6 vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_two_stage -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR16_1 Biasp CR16_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_pmos_l1_cr2_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_pmos_l1_cr2_2.sp deleted file mode 100644 index 0bc219f747..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_pmos_l1_cr2_2.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_two_stage -* View Name: schematic -* Netlisted on: Sep 11 21:10:37 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_two_stage -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_two_stage Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM1 net16 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 net9 net12 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net16 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net16 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR2_2_wilson Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -RR0 Vbiasn gnd! res=rK -MM2 Vbiasp net12 Vbiasn gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_two_stage -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR2_2_wilson Biasn Biasp CR2_2_wilson -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_pmos_l1_cr3_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_pmos_l1_cr3_2.sp deleted file mode 100644 index 102ab44456..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_pmos_l1_cr3_2.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_two_stage -* View Name: schematic -* Netlisted on: Sep 11 21:10:37 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_two_stage -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_two_stage Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM1 net16 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 net9 net12 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net16 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net16 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR3_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 net15 gnd! res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_two_stage -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR3_2 Biasn Biasp CR3_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_pmos_l1_cr4_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_pmos_l1_cr4_2.sp deleted file mode 100644 index f544854ddd..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_pmos_l1_cr4_2.sp +++ /dev/null @@ -1,73 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_two_stage -* View Name: schematic -* Netlisted on: Sep 11 21:10:37 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_two_stage -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_two_stage Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM1 net16 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 net9 net12 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net16 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net16 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR4_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM11 net023 net024 Vbiasn gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM8 net025 net010 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM9 net024 net024 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM7 net010 net010 net025 gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net025 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 net024 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net010 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_two_stage -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR4_2 Biasn Biasp CR4_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_pmos_l1_cr5_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_pmos_l1_cr5_2.sp deleted file mode 100644 index 692bbbcaf3..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_pmos_l1_cr5_2.sp +++ /dev/null @@ -1,70 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_two_stage -* View Name: schematic -* Netlisted on: Sep 11 21:10:37 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_two_stage -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_two_stage Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM1 net16 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 net9 net12 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net16 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net16 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR5_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM5 net014 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net014 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_two_stage -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR5_2 Biasn Biasp CR5_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_pmos_l1_cr6_3.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_pmos_l1_cr6_3.sp deleted file mode 100644 index 08044b397a..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_pmos_l1_cr6_3.sp +++ /dev/null @@ -1,70 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_two_stage -* View Name: schematic -* Netlisted on: Sep 11 21:10:37 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_two_stage -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_two_stage Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM1 net16 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 net9 net12 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net16 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net16 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR6_3 Vbiasn1 Vbiasn2 Vbiasp -*.PININFO Vbiasn1:O Vbiasn2:O Vbiasp:O -MM2 Vbiasp Vbiasn2 Vbiasn1 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn2 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 Vbiasn1 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM5 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn2 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_two_stage -xiLG_pmos_l1 Biasp LG_Vbiasn LG_Vbiasp LG_pmos_l1 -xibCR6_3 Biasn1 Biasn2 Biasp CR6_3 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_pnmos_4_cr13_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_pnmos_4_cr13_1.sp deleted file mode 100644 index 326cf4a06c..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_pnmos_4_cr13_1.sp +++ /dev/null @@ -1,69 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_two_stage -* View Name: schematic -* Netlisted on: Sep 11 21:10:37 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_two_stage -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_two_stage Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM1 net16 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 net9 net12 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net16 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net16 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_two_stage -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR13_2 Biasn Biasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_pnmos_4_cr13_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_pnmos_4_cr13_2.sp deleted file mode 100644 index 326cf4a06c..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_pnmos_4_cr13_2.sp +++ /dev/null @@ -1,69 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_two_stage -* View Name: schematic -* Netlisted on: Sep 11 21:10:37 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_two_stage -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_two_stage Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM1 net16 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 net9 net12 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net16 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net16 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_two_stage -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR13_2 Biasn Biasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_pnmos_4_cr14_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_pnmos_4_cr14_2.sp deleted file mode 100644 index e19d7f0d41..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_pnmos_4_cr14_2.sp +++ /dev/null @@ -1,70 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_two_stage -* View Name: schematic -* Netlisted on: Sep 11 21:10:37 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_two_stage -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_two_stage Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM1 net16 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 net9 net12 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net16 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net16 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR14_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net010 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 Vbiasn net010 res=rK -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_two_stage -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR14_2 Biasn Biasp CR14_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_pnmos_4_cr15_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_pnmos_4_cr15_1.sp deleted file mode 100644 index dc5ea1f2c9..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_pnmos_4_cr15_1.sp +++ /dev/null @@ -1,67 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_two_stage -* View Name: schematic -* Netlisted on: Sep 11 21:10:37 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_two_stage -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_two_stage Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM1 net16 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 net9 net12 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net16 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net16 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR15_1 Vbiasp -*.PININFO Vbiasp:O -RR1 Vbiasp gnd! res=rK -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_two_stage -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR15_1 Biasp CR15_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_pnmos_4_cr16_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_pnmos_4_cr16_1.sp deleted file mode 100644 index a490a79cf7..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_pnmos_4_cr16_1.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_two_stage -* View Name: schematic -* Netlisted on: Sep 11 21:10:37 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_two_stage -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_two_stage Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM1 net16 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 net9 net12 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net16 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net16 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR16_1 Vbiasp -*.PININFO Vbiasp:O -RR0 vdd! net6 res=rK -RR1 Vbiasp gnd! res=rK -MM2 Vbiasp Vbiasp net6 vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_two_stage -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR16_1 Biasp CR16_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_pnmos_4_cr2_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_pnmos_4_cr2_2.sp deleted file mode 100644 index 837815893e..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_pnmos_4_cr2_2.sp +++ /dev/null @@ -1,70 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_two_stage -* View Name: schematic -* Netlisted on: Sep 11 21:10:37 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_two_stage -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_two_stage Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM1 net16 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 net9 net12 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net16 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net16 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR2_2_wilson Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -RR0 Vbiasn gnd! res=rK -MM2 Vbiasp net12 Vbiasn gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_two_stage -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR2_2_wilson Biasn Biasp CR2_2_wilson -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_pnmos_4_cr3_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_pnmos_4_cr3_2.sp deleted file mode 100644 index fe3aefeeb2..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_pnmos_4_cr3_2.sp +++ /dev/null @@ -1,70 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_two_stage -* View Name: schematic -* Netlisted on: Sep 11 21:10:37 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_two_stage -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_two_stage Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM1 net16 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 net9 net12 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net16 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net16 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR3_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 net15 gnd! res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_two_stage -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR3_2 Biasn Biasp CR3_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_pnmos_4_cr4_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_pnmos_4_cr4_2.sp deleted file mode 100644 index e52e668268..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_pnmos_4_cr4_2.sp +++ /dev/null @@ -1,75 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_two_stage -* View Name: schematic -* Netlisted on: Sep 11 21:10:37 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_two_stage -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_two_stage Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM1 net16 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 net9 net12 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net16 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net16 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR4_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM11 net023 net024 Vbiasn gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM8 net025 net010 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM9 net024 net024 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM7 net010 net010 net025 gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net025 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 net024 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net010 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_two_stage -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR4_2 Biasn Biasp CR4_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_pnmos_4_cr5_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_pnmos_4_cr5_2.sp deleted file mode 100644 index 4681848f8a..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_pnmos_4_cr5_2.sp +++ /dev/null @@ -1,72 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_two_stage -* View Name: schematic -* Netlisted on: Sep 11 21:10:37 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_two_stage -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_two_stage Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM1 net16 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 net9 net12 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net16 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net16 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR5_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM5 net014 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net014 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_two_stage -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR5_2 Biasn Biasp CR5_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_pnmos_4_cr6_3.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_pnmos_4_cr6_3.sp deleted file mode 100644 index 6467d18663..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_pnmos_4_cr6_3.sp +++ /dev/null @@ -1,72 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_two_stage -* View Name: schematic -* Netlisted on: Sep 11 21:10:37 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_two_stage -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_two_stage Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM1 net16 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 net9 net12 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net16 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net16 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR6_3 Vbiasn1 Vbiasn2 Vbiasp -*.PININFO Vbiasn1:O Vbiasn2:O Vbiasp:O -MM2 Vbiasp Vbiasn2 Vbiasn1 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn2 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 Vbiasn1 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM5 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn2 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_two_stage -xiLG_pnmos_4 Biasp LG_Vbiasn LG_Vbiasp LG_pnmos_4 -xibCR6_3 Biasn1 Biasn2 Biasp CR6_3 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_pnmos_cr13_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_pnmos_cr13_1.sp deleted file mode 100644 index 445b53b80b..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_pnmos_cr13_1.sp +++ /dev/null @@ -1,69 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_two_stage -* View Name: schematic -* Netlisted on: Sep 11 21:10:37 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_two_stage -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_two_stage Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM1 net16 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 net9 net12 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net16 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net16 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_two_stage -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR13_2 Biasn Biasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_pnmos_cr13_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_pnmos_cr13_2.sp deleted file mode 100644 index 445b53b80b..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_pnmos_cr13_2.sp +++ /dev/null @@ -1,69 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_two_stage -* View Name: schematic -* Netlisted on: Sep 11 21:10:37 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_two_stage -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_two_stage Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM1 net16 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 net9 net12 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net16 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net16 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_two_stage -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR13_2 Biasn Biasp CR13_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_pnmos_cr14_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_pnmos_cr14_2.sp deleted file mode 100644 index 219e250c91..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_pnmos_cr14_2.sp +++ /dev/null @@ -1,70 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_two_stage -* View Name: schematic -* Netlisted on: Sep 11 21:10:37 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_two_stage -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_two_stage Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM1 net16 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 net9 net12 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net16 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net16 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR14_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net010 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 Vbiasn net010 res=rK -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_two_stage -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR14_2 Biasn Biasp CR14_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_pnmos_cr15_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_pnmos_cr15_1.sp deleted file mode 100644 index 50ad74bb28..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_pnmos_cr15_1.sp +++ /dev/null @@ -1,67 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_two_stage -* View Name: schematic -* Netlisted on: Sep 11 21:10:37 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_two_stage -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_two_stage Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM1 net16 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 net9 net12 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net16 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net16 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR15_1 Vbiasp -*.PININFO Vbiasp:O -RR1 Vbiasp gnd! res=rK -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_two_stage -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR15_1 Biasp CR15_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_pnmos_cr16_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_pnmos_cr16_1.sp deleted file mode 100644 index ecc4e7bc1f..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_pnmos_cr16_1.sp +++ /dev/null @@ -1,68 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_two_stage -* View Name: schematic -* Netlisted on: Sep 11 21:10:37 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_two_stage -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_two_stage Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM1 net16 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 net9 net12 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net16 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net16 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR16_1 Vbiasp -*.PININFO Vbiasp:O -RR0 vdd! net6 res=rK -RR1 Vbiasp gnd! res=rK -MM2 Vbiasp Vbiasp net6 vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_two_stage -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR16_1 Biasp CR16_1 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_pnmos_cr2_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_pnmos_cr2_2.sp deleted file mode 100644 index e40a22ee7e..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_pnmos_cr2_2.sp +++ /dev/null @@ -1,70 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_two_stage -* View Name: schematic -* Netlisted on: Sep 11 21:10:37 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_two_stage -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_two_stage Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM1 net16 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 net9 net12 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net16 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net16 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR2_2_wilson Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -RR0 Vbiasn gnd! res=rK -MM2 Vbiasp net12 Vbiasn gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_two_stage -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR2_2_wilson Biasn Biasp CR2_2_wilson -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_pnmos_cr3_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_pnmos_cr3_2.sp deleted file mode 100644 index 25e01e66fd..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_pnmos_cr3_2.sp +++ /dev/null @@ -1,70 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_two_stage -* View Name: schematic -* Netlisted on: Sep 11 21:10:37 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_two_stage -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_two_stage Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM1 net16 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 net9 net12 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net16 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net16 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR3_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 net15 gnd! res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_two_stage -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR3_2 Biasn Biasp CR3_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_pnmos_cr4_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_pnmos_cr4_2.sp deleted file mode 100644 index f20d213939..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_pnmos_cr4_2.sp +++ /dev/null @@ -1,75 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_two_stage -* View Name: schematic -* Netlisted on: Sep 11 21:10:37 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_two_stage -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_two_stage Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM1 net16 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 net9 net12 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net16 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net16 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR4_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM11 net023 net024 Vbiasn gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM8 net025 net010 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM9 net024 net024 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM7 net010 net010 net025 gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net025 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 net024 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net010 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_two_stage -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR4_2 Biasn Biasp CR4_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_pnmos_cr5_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_pnmos_cr5_2.sp deleted file mode 100644 index d660a68b3b..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_pnmos_cr5_2.sp +++ /dev/null @@ -1,72 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_two_stage -* View Name: schematic -* Netlisted on: Sep 11 21:10:37 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_two_stage -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_two_stage Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM1 net16 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 net9 net12 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net16 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net16 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR5_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM5 net014 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net014 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_two_stage -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR5_2 Biasn Biasp CR5_2 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_pnmos_cr6_3.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_pnmos_cr6_3.sp deleted file mode 100644 index c09b35eee5..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/full_OTA/single_ended_OTA/single_ended_two_stage_LG_pnmos_cr6_3.sp +++ /dev/null @@ -1,72 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_two_stage -* View Name: schematic -* Netlisted on: Sep 11 21:10:37 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_two_stage -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_two_stage Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM1 net16 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 net9 net12 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net16 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net16 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - -.SUBCKT CR6_3 Vbiasn1 Vbiasn2 Vbiasp -*.PININFO Vbiasn1:O Vbiasn2:O Vbiasp:O -MM2 Vbiasp Vbiasn2 Vbiasn1 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn2 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 Vbiasn1 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM5 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn2 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - - -xiota LG_Vbiasn Vinn Vinp Voutp single_ended_two_stage -xiLG_pnmos Biasp LG_Vbiasn LG_Vbiasp LG_pnmos -xibCR6_3 Biasn1 Biasn2 Biasp CR6_3 -.END \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/OTA/.stimulusFile.auCdl b/DesignDatabase/Testcases/OTA/OTA_topologies/generator/OTA/.stimulusFile.auCdl deleted file mode 100644 index e69de29bb2..0000000000 diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/OTA/Fully_differential_cascode_current_mirror b/DesignDatabase/Testcases/OTA/OTA_topologies/generator/OTA/Fully_differential_cascode_current_mirror deleted file mode 100644 index 78095322c1..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/OTA/Fully_differential_cascode_current_mirror +++ /dev/null @@ -1,53 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: Fully_differential_cascode_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:02:16 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: Fully_differential_cascode_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT Fully_differential_cascode_current_mirror Vbiasn Vbiasn1 Vbiasn2 -+ Vbiasp1 Vbiasp2 Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vbiasn1:I Vbiasn2:I Vbiasp1:I Vbiasp2:I Vinn:I Vinp:I -*.PININFO Voutn:O Voutp:O -MM3 net22 Vinp net9 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net31 Vinn net9 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net9 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM14 Voutp Vbiasn2 net34 gnd! nmos_rvt w=WA l=LA nfin=nA -MM13 Voutn Vbiasn2 net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net34 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 net21 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 net32 Vbiasp2 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net23 Vbiasp2 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM6 net33 Vbiasp2 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 net20 Vbiasp2 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM12 net31 Vbiasp1 net32 vdd! pmos_rvt w=WA l=LA nfin=nA -MM11 net22 Vbiasp1 net23 vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Voutp Vbiasp1 net33 vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 Voutn Vbiasp1 net20 vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/OTA/Fully_differential_cascode_current_mirror_pmos b/DesignDatabase/Testcases/OTA/OTA_topologies/generator/OTA/Fully_differential_cascode_current_mirror_pmos deleted file mode 100644 index 1b71242b1b..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/OTA/Fully_differential_cascode_current_mirror_pmos +++ /dev/null @@ -1,53 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: Fully_differential_cascode_current_mirror_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:02:31 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: Fully_differential_cascode_current_mirror_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT Fully_differential_cascode_current_mirror_pmos Vbiasn1 Vbiasn2 Vbiasp -+ Vbiasp1 Vbiasp2 Vinn Vinp Voutn Voutp -*.PININFO Vbiasn1:I Vbiasn2:I Vbiasp:I Vbiasp1:I Vbiasp2:I Vinn:I Vinp:I -*.PININFO Voutn:O Voutp:O -MM1 Voutp Vbiasn2 net37 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutn Vbiasn2 net29 gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net35 Vbiasn2 net34 gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net31 Vbiasn2 net30 gnd! nmos_rvt w=WA l=LA nfin=nA -MM12 net37 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM11 net29 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 net34 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net30 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM14 net36 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM13 net28 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Voutp Vbiasp2 net36 vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutn Vbiasp2 net28 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 net17 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net35 Vinn net17 net32 pmos_rvt w=WA l=LA nfin=nA -MM6 net31 Vinp net17 net32 pmos_rvt w=WA l=LA nfin=nA -.ENDS - diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/OTA/Fully_differential_current_mirror b/DesignDatabase/Testcases/OTA/OTA_topologies/generator/OTA/Fully_differential_current_mirror deleted file mode 100644 index 88c33d683e..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/OTA/Fully_differential_current_mirror +++ /dev/null @@ -1,45 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: Fully_differential_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:01:53 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: Fully_differential_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT Fully_differential_current_mirror Vbiasn Vbiasn1 Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vbiasn1:I Vinn:I Vinp:I Voutn:O Voutp:O -MM3 net23 Vinp net19 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net15 Vinn net19 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net19 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Voutp Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutn Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutp net15 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net23 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net23 net23 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net15 net15 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/OTA/Fully_differential_current_mirror_pmos b/DesignDatabase/Testcases/OTA/OTA_topologies/generator/OTA/Fully_differential_current_mirror_pmos deleted file mode 100644 index 0d080b1067..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/OTA/Fully_differential_current_mirror_pmos +++ /dev/null @@ -1,46 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: Fully_differential_current_mirror_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:02:54 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: Fully_differential_current_mirror_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT Fully_differential_current_mirror_pmos Vbiasp Vbiasp1 Vinn Vinp Voutn -+ Voutp -*.PININFO Vbiasp:I Vbiasp1:I Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutp net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net13 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutn net19 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net19 net19 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutp Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutn Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 net17 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net13 Vinn net17 net24 pmos_rvt w=WA l=LA nfin=nA -MM6 net19 Vinp net17 net24 pmos_rvt w=WA l=LA nfin=nA -.ENDS - diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/OTA/Fully_differential_folded_cascode b/DesignDatabase/Testcases/OTA/OTA_topologies/generator/OTA/Fully_differential_folded_cascode deleted file mode 100644 index 8faa70fefa..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/OTA/Fully_differential_folded_cascode +++ /dev/null @@ -1,49 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: Fully_differential_folded_cascode -* View Name: schematic -* Netlisted on: Sep 11 21:03:06 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: Fully_differential_folded_cascode -* View Name: schematic -************************************************************************ - -.SUBCKT Fully_differential_folded_cascode Vbiasn Vbiasn1 Vbiasn2 Vbiasp1 -+ Vbiasp2 Vinn Vinp Voutn -*.PININFO Vbiasn:I Vbiasn1:I Vbiasn2:I Vbiasp1:I Vbiasp2:I Vinn:I Vinp:I -*.PININFO Voutn:O -MM6 net26 Vbiasp2 net23 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn Vbiasp2 net24 vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net23 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net24 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM8 net26 Vbiasn2 net27 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutn Vbiasn2 net25 gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net24 Vinp net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net23 Vinn net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 net27 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net25 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net13 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/OTA/Fully_differential_folded_cascode_pmos b/DesignDatabase/Testcases/OTA/OTA_topologies/generator/OTA/Fully_differential_folded_cascode_pmos deleted file mode 100644 index b822fc3c36..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/OTA/Fully_differential_folded_cascode_pmos +++ /dev/null @@ -1,49 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: Fully_differential_folded_cascode_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:03:18 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: Fully_differential_folded_cascode_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT Fully_differential_folded_cascode_pmos Vbiasn1 Vbiasn2 Vbiasp Vbiasp1 -+ Vbiasp2 Vinn Vinp Voutn Voutp -*.PININFO Vbiasn1:I Vbiasn2:I Vbiasp:I Vbiasp1:I Vbiasp2:I Vinn:I Vinp:I -*.PININFO Voutn:O Voutp:O -MM8 Voutn Vbiasn2 net23 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp Vbiasn2 net22 gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 net23 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net22 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net26 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net24 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net22 Vinn net12 net27 pmos_rvt w=WA l=LA nfin=nA -MM3 net23 Vinp net12 net27 pmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vbiasp2 net26 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp Vbiasp2 net24 vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/OTA/Fully_differential_miller_compensated_pmos b/DesignDatabase/Testcases/OTA/OTA_topologies/generator/OTA/Fully_differential_miller_compensated_pmos deleted file mode 100644 index e667df5bc9..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/OTA/Fully_differential_miller_compensated_pmos +++ /dev/null @@ -1,48 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: Fully_differential_miller_compensated_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:03:30 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: Fully_differential_miller_compensated_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT Fully_differential_miller_compensated_pmos Vbiasn1 Vbiasp Vinn Vinp -+ Voutn Voutp -*.PININFO Vbiasn1:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn net21 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM13 Voutp net25 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net25 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net21 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM12 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM11 net17 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net25 Vinn net17 net28 pmos_rvt w=WA l=LA nfin=nA -MM7 net21 Vinp net17 net28 pmos_rvt w=WA l=LA nfin=nA -CC0 Voutn net21 1p $[CP] -CC2 Voutp net25 1p $[CP] -.ENDS - diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/OTA/Fully_differential_telescopic b/DesignDatabase/Testcases/OTA/OTA_topologies/generator/OTA/Fully_differential_telescopic deleted file mode 100644 index 0295543017..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/OTA/Fully_differential_telescopic +++ /dev/null @@ -1,44 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: Fully_differential_telescopic -* View Name: schematic -* Netlisted on: Sep 11 21:03:54 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: Fully_differential_telescopic -* View Name: schematic -************************************************************************ - -.SUBCKT Fully_differential_telescopic Vbiasn Vbiasp1 Vbiasp2 Vinn Vinp Voutn -+ Voutp -*.PININFO Vbiasn:I Vbiasp1:I Vbiasp2:I Vinn:I Vinp:I Voutn:O Voutp:O -MM5 Voutp Vbiasp2 net18 net18 pmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vbiasp2 net13 net13 pmos_rvt w=WA l=LA nfin=nA -MM1 net18 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net13 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Voutp Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutn Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/OTA/Fully_differential_telescopic_pmos b/DesignDatabase/Testcases/OTA/OTA_topologies/generator/OTA/Fully_differential_telescopic_pmos deleted file mode 100644 index f4dd49ee6b..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/OTA/Fully_differential_telescopic_pmos +++ /dev/null @@ -1,44 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: Fully_differential_telescopic_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:04:07 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: Fully_differential_telescopic_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT Fully_differential_telescopic_pmos Vbiasn1 Vbiasn2 Vbiasp Vinn Vinp -+ Voutn Voutp -*.PININFO Vbiasn1:I Vbiasn2:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM0 Voutp Vbiasn2 net12 net12 nmos_rvt w=WA l=LA nfin=nA -MM1 Voutn Vbiasn2 net17 net17 nmos_rvt w=WA l=LA nfin=nA -MM8 net17 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net12 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM5 net14 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 Voutp Vinn net14 net18 pmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vinp net14 net18 pmos_rvt w=WA l=LA nfin=nA -.ENDS - diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/OTA/fully_differential b/DesignDatabase/Testcases/OTA/OTA_topologies/generator/OTA/fully_differential deleted file mode 100644 index 7f240ed090..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/OTA/fully_differential +++ /dev/null @@ -1,41 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential -* View Name: schematic -* Netlisted on: Sep 11 21:04:32 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/OTA/fully_differential_cascode b/DesignDatabase/Testcases/OTA/OTA_topologies/generator/OTA/fully_differential_cascode deleted file mode 100644 index 0d7dbf6315..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/OTA/fully_differential_cascode +++ /dev/null @@ -1,43 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_cascode -* View Name: schematic -* Netlisted on: Sep 11 21:04:46 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_cascode -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_cascode Vbiasn Vbiasp1 Vbiasp2 Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vbiasp1:I Vbiasp2:I Vinn:I Vinp:I Voutn:O Voutp:O -MM3 Voutn Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutp Vbiasp2 net22 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn Vbiasp2 net21 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net21 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net22 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/OTA/fully_differential_cascode_pmos b/DesignDatabase/Testcases/OTA/OTA_topologies/generator/OTA/fully_differential_cascode_pmos deleted file mode 100644 index f14a5d9cc6..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/OTA/fully_differential_cascode_pmos +++ /dev/null @@ -1,44 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_cascode_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:05:09 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_cascode_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_cascode_pmos Vbiasn1 Vbiasn2 Vbiasp Vinn Vinp -+ Voutp1 Voutp2 -*.PININFO Vbiasp:I Vinn:I Vinp:I Vbiasn1:O Vbiasn2:O Voutp1:O Voutp2:O -MM1 Voutp2 Vbiasn2 net17 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp1 Vbiasn2 net18 gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net18 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net17 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM5 net13 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 Voutp1 Vinn net13 net20 pmos_rvt w=WA l=LA nfin=nA -MM6 Voutp2 Vinp net13 net20 pmos_rvt w=WA l=LA nfin=nA -.ENDS - diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/OTA/fully_differential_gain_boosting b/DesignDatabase/Testcases/OTA/OTA_topologies/generator/OTA/fully_differential_gain_boosting deleted file mode 100644 index dfb1de55a1..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/OTA/fully_differential_gain_boosting +++ /dev/null @@ -1,62 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_gain_boosting -* View Name: schematic -* Netlisted on: Sep 11 21:05:36 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential Vinn Vinp Voutn Voutp -*.PININFO Vinn:I Vinp:I Voutn:O Voutp:O -MM1 Voutn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net14 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Voutn Vinp net14 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vinn net14 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_gain_boosting -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_gain_boosting Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Vbiasp:O Voutn:O Voutp:O -MM8 Voutn net22 net23 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp net19 net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net23 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net21 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn net24 net25 vdd pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net20 net12 vdd pmos_rvt w=WA l=LA nfin=nA -MM1 net25 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -XI3 net12 net25 net24 net20 / fully_differential -XI1 net23 net21 net19 net22 / fully_differential -.ENDS - diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/OTA/fully_differential_miller_compensated b/DesignDatabase/Testcases/OTA/OTA_topologies/generator/OTA/fully_differential_miller_compensated deleted file mode 100644 index 6d5ea7dafe..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/OTA/fully_differential_miller_compensated +++ /dev/null @@ -1,48 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:05:48 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_miller_compensated Vbiasn Vbiasp Vinn Vinp Voutn -+ Voutp -*.PININFO Vbiasn:I Vbiasp:I Vinn:I Vinp:I Voutn:O Voutp:O -MM7 Voutp net15 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net22 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net22 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM8 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net22 Vinp net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net15 Vinn net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net21 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -CC1 Voutp net15 1p $[CP] -CC0 Voutn net22 1p $[CP] -.ENDS - diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/OTA/fully_differential_pmos b/DesignDatabase/Testcases/OTA/OTA_topologies/generator/OTA/fully_differential_pmos deleted file mode 100644 index 1762c9c9a3..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/OTA/fully_differential_pmos +++ /dev/null @@ -1,41 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: fully_differential_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:06:01 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: fully_differential_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT fully_differential_pmos Vbiasn Vbiasp Vinn Vinp Voutn Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Vbiasn:O Voutn:O Voutp:O -MM7 Voutp Vinn net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM6 Voutn Vinp net12 net16 pmos_rvt w=WA l=LA nfin=nA -MM5 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 Voutp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/OTA/single_ended b/DesignDatabase/Testcases/OTA/OTA_topologies/generator/OTA/single_ended deleted file mode 100644 index 5f2c763bfc..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/OTA/single_ended +++ /dev/null @@ -1,41 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended -* View Name: schematic -* Netlisted on: Sep 11 21:06:14 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/OTA/single_ended_cascode b/DesignDatabase/Testcases/OTA/OTA_topologies/generator/OTA/single_ended_cascode deleted file mode 100644 index a5503617e4..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/OTA/single_ended_cascode +++ /dev/null @@ -1,47 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_cascode -* View Name: schematic -* Netlisted on: Sep 11 21:06:28 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_cascode -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_cascode Vbiasn1 Vbiasn2 Vbiasp1 Vbiasp2 Vinn Vinp Voutn -*.PININFO Vbiasn1:I Vbiasn2:I Vbiasp1:I Vbiasp2:I Vinn:I Vinp:I Voutn:O -MM10 net27 net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net21 net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net12 Vbiasn2 net27 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutn Vbiasn2 net21 gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net32 Vinp net10 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net26 Vinn net10 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net10 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net12 Vbiasp2 net26 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn Vbiasp2 net32 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net32 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net26 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/OTA/single_ended_cascode_current_mirror b/DesignDatabase/Testcases/OTA/OTA_topologies/generator/OTA/single_ended_cascode_current_mirror deleted file mode 100644 index c91b116108..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/OTA/single_ended_cascode_current_mirror +++ /dev/null @@ -1,52 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_cascode_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:41:11 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_cascode_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_cascode_current_mirror Vbiasn Vbiasn2 Vbiasp2 Vinn Vinp -+ Voutn -*.PININFO Vbiasn:I Vbiasn2:I Vbiasp2:I Vinn:I Vinp:I Voutn:O -MM12 net12 Vbiasp2 net37 vdd! pmos_rvt w=WA l=LA nfin=nA -MM11 net23 Vbiasp2 net36 vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net10 Vbiasp2 net35 vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 Voutn Vbiasp2 net34 vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net37 net12 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net36 net23 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM6 net35 net12 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 net34 net23 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM14 net10 Vbiasn2 net33 gnd! nmos_rvt w=WA l=LA nfin=nA -MM13 Voutn Vbiasn2 net31 gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net23 Vinp net17 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vinn net17 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net17 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net33 net10 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 net31 net10 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/OTA/single_ended_cascode_current_mirror_pmos b/DesignDatabase/Testcases/OTA/OTA_topologies/generator/OTA/single_ended_cascode_current_mirror_pmos deleted file mode 100644 index 25fea950a6..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/OTA/single_ended_cascode_current_mirror_pmos +++ /dev/null @@ -1,52 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_cascode_current_mirror_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:41:22 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_cascode_current_mirror_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_cascode_current_mirror_pmos Vbiasn2 Vbiasp Vbiasp2 Vinn -+ Vinp Voutp -*.PININFO Vbiasn2:I Vbiasp:I Vbiasp2:I Vinn:I Vinp:I Voutp:O -MM14 net025 net012 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM13 net024 net012 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Voutp Vbiasp2 net025 vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net012 Vbiasp2 net024 vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net11 Vinn net14 net27 pmos_rvt w=WA l=LA nfin=nA -MM6 net16 Vinp net14 net27 pmos_rvt w=WA l=LA nfin=nA -MM5 net14 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM12 net29 net11 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM11 net32 net16 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 net33 net11 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net26 net16 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Voutp Vbiasn2 net29 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net012 Vbiasn2 net32 gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net11 Vbiasn2 net33 gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net16 Vbiasn2 net26 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/OTA/single_ended_cascode_pmos b/DesignDatabase/Testcases/OTA/OTA_topologies/generator/OTA/single_ended_cascode_pmos deleted file mode 100644 index 7c5a2629f9..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/OTA/single_ended_cascode_pmos +++ /dev/null @@ -1,48 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_cascode_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:07:21 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_cascode_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_cascode_pmos Vbiasn1 Vbiasn2 Vbiasp1 Vbiasp2 Vinn Vinp -+ Voutp -*.PININFO Vbiasp1:I Vbiasp2:I Vinn:I Vinp:I Vbiasn1:O Vbiasn2:O Voutp:O -MM4 net28 Vinn net12 net22 pmos_rvt w=WA l=LA nfin=nA -MM3 net29 Vinp net12 net22 pmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM6 net16 Vbiasp2 net25 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp Vbiasp2 net24 vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net25 net16 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net24 net16 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net29 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net28 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net16 Vbiasn2 net29 gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp Vbiasn2 net28 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/OTA/single_ended_current_mirror b/DesignDatabase/Testcases/OTA/OTA_topologies/generator/OTA/single_ended_current_mirror deleted file mode 100644 index c443b4922b..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/OTA/single_ended_current_mirror +++ /dev/null @@ -1,45 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:07:33 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM8 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutn net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net20 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net9 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net11 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/OTA/single_ended_current_mirror_pmos b/DesignDatabase/Testcases/OTA/OTA_topologies/generator/OTA/single_ended_current_mirror_pmos deleted file mode 100644 index b73a740694..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/OTA/single_ended_current_mirror_pmos +++ /dev/null @@ -1,45 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:07:49 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_current_mirror_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_current_mirror_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM3 Voutp net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net17 net17 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 Vinn net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vinp net13 net22 pmos_rvt w=WA l=LA nfin=nA -MM5 net13 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net17 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/OTA/single_ended_low_voltage_cascode_current_mirror b/DesignDatabase/Testcases/OTA/OTA_topologies/generator/OTA/single_ended_low_voltage_cascode_current_mirror deleted file mode 100644 index 74a87b46b9..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/OTA/single_ended_low_voltage_cascode_current_mirror +++ /dev/null @@ -1,43 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -* Netlisted on: Sep 11 21:08:07 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_current_mirror -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_current_mirror Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net11 Vinn net13 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net13 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net11 net18 net19 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net18 net20 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net20 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net19 net11 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/OTA/single_ended_low_voltage_cascode_pmos b/DesignDatabase/Testcases/OTA/OTA_topologies/generator/OTA/single_ended_low_voltage_cascode_pmos deleted file mode 100644 index c6dd7df37c..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/OTA/single_ended_low_voltage_cascode_pmos +++ /dev/null @@ -1,43 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:08:22 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_low_voltage_cascode_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_low_voltage_cascode_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM7 Voutp Vinn net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM6 net13 Vinp net11 net18 pmos_rvt w=WA l=LA nfin=nA -MM5 net11 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Voutp net17 net20 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net13 net17 net19 gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net20 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net19 net13 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/OTA/single_ended_miller_compensated b/DesignDatabase/Testcases/OTA/OTA_topologies/generator/OTA/single_ended_miller_compensated deleted file mode 100644 index 5ec09a2749..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/OTA/single_ended_miller_compensated +++ /dev/null @@ -1,44 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated -* View Name: schematic -* Netlisted on: Sep 11 21:08:39 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated Vbiasn Vinn Vinp Voutn -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutn:O -MM6 Voutn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net011 Vinp net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net07 Vinn net16 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net16 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 net011 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net07 net07 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutn net011 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -CC0 Voutn net011 1p $[CP] -.ENDS - diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/OTA/single_ended_miller_compensated_pmos b/DesignDatabase/Testcases/OTA/OTA_topologies/generator/OTA/single_ended_miller_compensated_pmos deleted file mode 100644 index b700ae509b..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/OTA/single_ended_miller_compensated_pmos +++ /dev/null @@ -1,44 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:34 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_miller_compensated_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_miller_compensated_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM13 Voutp net38 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net38 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net35 net35 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM12 Voutp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM11 net33 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net38 Vinn net33 net39 pmos_rvt w=WA l=LA nfin=nA -MM7 net35 Vinp net33 net39 pmos_rvt w=WA l=LA nfin=nA -CC2 Voutp net38 1p $[CP] -.ENDS - diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/OTA/single_ended_pmos b/DesignDatabase/Testcases/OTA/OTA_topologies/generator/OTA/single_ended_pmos deleted file mode 100644 index 997df31d95..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/OTA/single_ended_pmos +++ /dev/null @@ -1,41 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:09:58 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_pmos Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasp:I Vinn:I Vinp:I Voutp:O -MM9 Voutp net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net12 net12 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM7 Voutp Vinn net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM6 net12 Vinp net10 net14 pmos_rvt w=WA l=LA nfin=nA -MM5 net10 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/OTA/single_ended_telescopic b/DesignDatabase/Testcases/OTA/OTA_topologies/generator/OTA/single_ended_telescopic deleted file mode 100644 index 76b999a4fc..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/OTA/single_ended_telescopic +++ /dev/null @@ -1,43 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_telescopic -* View Name: schematic -* Netlisted on: Sep 11 21:39:36 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_telescopic -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_telescopic Vbiasn Vbiasp2 Vinn Vinp Voutp -*.PININFO Vbiasn:I Vbiasp2:I Vinn:I Vinp:I Voutp:O -MM3 Voutp Vinp net11 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net13 Vinn net11 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net11 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net13 Vbiasp2 net016 vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp Vbiasp2 net014 vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net014 net13 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net016 net13 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/OTA/single_ended_telescopic_pmos b/DesignDatabase/Testcases/OTA/OTA_topologies/generator/OTA/single_ended_telescopic_pmos deleted file mode 100644 index b77d06bc5e..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/OTA/single_ended_telescopic_pmos +++ /dev/null @@ -1,43 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_telescopic_pmos -* View Name: schematic -* Netlisted on: Sep 11 21:39:52 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_telescopic_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_telescopic_pmos Vbiasn2 Vbiasp Vinn Vinp Voutp -*.PININFO Vbiasn2:I Vbiasp:I Vinn:I Vinp:I Voutp:O -MM1 net14 Vbiasn2 net013 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Voutp Vbiasn2 net10 gnd! nmos_rvt w=WA l=LA nfin=nA -MM9 net10 net14 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net013 net14 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM5 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 Voutp Vinn net12 net19 pmos_rvt w=WA l=LA nfin=nA -MM6 net14 Vinp net12 net19 pmos_rvt w=WA l=LA nfin=nA -.ENDS - diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/OTA/single_ended_two_stage b/DesignDatabase/Testcases/OTA/OTA_topologies/generator/OTA/single_ended_two_stage deleted file mode 100644 index f9bcb58b1b..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/OTA/single_ended_two_stage +++ /dev/null @@ -1,45 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_class -* Top Cell Name: single_ended_two_stage -* View Name: schematic -* Netlisted on: Sep 11 21:10:37 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_class -* Cell Name: single_ended_two_stage -* View Name: schematic -************************************************************************ - -.SUBCKT single_ended_two_stage Vbiasn Vinn Vinp Voutp -*.PININFO Vbiasn:I Vinn:I Vinp:I Voutp:O -MM1 net16 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 net12 net20 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM9 net9 net12 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM5 Voutp net16 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM7 net9 net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net16 Vinp net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vinn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 Voutp net9 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/README.md b/DesignDatabase/Testcases/OTA/OTA_topologies/generator/README.md deleted file mode 100644 index 19d0d5eba8..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/README.md +++ /dev/null @@ -1,8 +0,0 @@ -# OTA subcircuit topologies -This directory contains subcircuit topologies used to generate OTA with bias circuits. - -## Directory structure -- *bias*: contains different low frequency analog bias topologies which provide voltage reference to local generators (15 circuits) -- *local_generation*: contains various local current/voltage biasing used for OTA circuits -- *OTA*: contains OTA signal path topologies -- *merge_OTA.py*: utilizes *bias, local_generation, OTA* subcircuits to generate full OTA circuits with proper biasing diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/bias/cr11_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/generator/bias/cr11_1.sp deleted file mode 100644 index f039d80669..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/bias/cr11_1.sp +++ /dev/null @@ -1,41 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: biasing_circuits -* Top Cell Name: CR11_1 -* View Name: schematic -* Netlisted on: Apr 4 17:14:35 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: biasing_circuits -* Cell Name: CR11_1 -* View Name: schematic -************************************************************************ - -.SUBCKT CR11_1 Vbiasn -*.PININFO Vbiasn:O -RRF vdd! Vbiasn res=rK -MM1 net9 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net9 net9 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn net9 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/bias/cr12_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/generator/bias/cr12_1.sp deleted file mode 100644 index ec9f00f531..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/bias/cr12_1.sp +++ /dev/null @@ -1,41 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: biasing_circuits -* Top Cell Name: CR12_1 -* View Name: schematic -* Netlisted on: Apr 4 17:15:12 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: biasing_circuits -* Cell Name: CR12_1 -* View Name: schematic -************************************************************************ - -.SUBCKT CR12_1 Vbiasn -*.PININFO Vbiasn:O -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 net10 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn net10 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RRF vdd! Vbiasn res=rK -RR0 vdd! net10 res=rK -.ENDS - diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/bias/cr13_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/generator/bias/cr13_1.sp deleted file mode 100644 index 3ff7c45443..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/bias/cr13_1.sp +++ /dev/null @@ -1,40 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: biasing_circuits -* Top Cell Name: CR13_2 -* View Name: schematic -* Netlisted on: Apr 4 17:15:36 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: biasing_circuits -* Cell Name: CR13_2 -* View Name: schematic -************************************************************************ - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/bias/cr13_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/generator/bias/cr13_2.sp deleted file mode 100644 index 6a7252eca9..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/bias/cr13_2.sp +++ /dev/null @@ -1,40 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: biasing_circuits -* Top Cell Name: CR13_2 -* View Name: schematic -* Netlisted on: Oct 23 15:01:25 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: biasing_circuits -* Cell Name: CR13_2 -* View Name: schematic -************************************************************************ - -.SUBCKT CR13_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/bias/cr14_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/generator/bias/cr14_2.sp deleted file mode 100644 index 9983865e23..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/bias/cr14_2.sp +++ /dev/null @@ -1,41 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: biasing_circuits -* Top Cell Name: CR14_2 -* View Name: schematic -* Netlisted on: Apr 4 17:15:59 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: biasing_circuits -* Cell Name: CR14_2 -* View Name: schematic -************************************************************************ - -.SUBCKT CR14_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM2 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net010 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 Vbiasn net010 res=rK -.ENDS - diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/bias/cr15_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/generator/bias/cr15_1.sp deleted file mode 100644 index e176e9f9ba..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/bias/cr15_1.sp +++ /dev/null @@ -1,38 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: biasing_circuits -* Top Cell Name: CR15_1 -* View Name: schematic -* Netlisted on: Apr 4 13:53:10 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: biasing_circuits -* Cell Name: CR15_1 -* View Name: schematic -************************************************************************ - -.SUBCKT CR15_1 Vbiasp -*.PININFO Vbiasp:O -RR1 Vbiasp gnd! res=rK -MM2 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/bias/cr16_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/generator/bias/cr16_1.sp deleted file mode 100644 index 5ffc7e05da..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/bias/cr16_1.sp +++ /dev/null @@ -1,39 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: biasing_circuits -* Top Cell Name: CR16_1 -* View Name: schematic -* Netlisted on: Apr 4 13:53:44 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: biasing_circuits -* Cell Name: CR16_1 -* View Name: schematic -************************************************************************ - -.SUBCKT CR16_1 Vbiasp -*.PININFO Vbiasp:O -RR0 vdd! net6 res=rK -RR1 Vbiasp gnd! res=rK -MM2 Vbiasp Vbiasp net6 vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/bias/cr1_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/generator/bias/cr1_1.sp deleted file mode 100644 index cf49adb527..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/bias/cr1_1.sp +++ /dev/null @@ -1,38 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: biasing_circuits -* Top Cell Name: CR1_1 -* View Name: schematic -* Netlisted on: Mar 31 15:07:06 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: biasing_circuits -* Cell Name: CR1_1 -* View Name: schematic -************************************************************************ - -.SUBCKT CR1_1 Vbiasn -*.PININFO Vbiasn:O -RRF vdd! Vbiasn res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/bias/cr2_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/generator/bias/cr2_2.sp deleted file mode 100644 index ba7d95dfd0..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/bias/cr2_2.sp +++ /dev/null @@ -1,41 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: biasing_circuits -* Top Cell Name: CR2_2_wilson -* View Name: schematic -* Netlisted on: Mar 31 15:08:05 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: biasing_circuits -* Cell Name: CR2_2_wilson -* View Name: schematic -************************************************************************ - -.SUBCKT CR2_2_wilson Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -RR0 Vbiasn gnd! res=rK -MM2 Vbiasp net12 Vbiasn gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 net12 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 net12 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/bias/cr3_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/generator/bias/cr3_2.sp deleted file mode 100644 index 7328c6cbfa..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/bias/cr3_2.sp +++ /dev/null @@ -1,41 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: biasing_circuits -* Top Cell Name: CR3_2 -* View Name: schematic -* Netlisted on: Mar 31 15:08:54 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: biasing_circuits -* Cell Name: CR3_2 -* View Name: schematic -************************************************************************ - -.SUBCKT CR3_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -RR0 net15 gnd! res=rK -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/bias/cr4_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/generator/bias/cr4_2.sp deleted file mode 100644 index 53bf2cbfaf..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/bias/cr4_2.sp +++ /dev/null @@ -1,46 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: biasing_circuits -* Top Cell Name: CR4_2 -* View Name: schematic -* Netlisted on: Apr 4 17:17:18 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: biasing_circuits -* Cell Name: CR4_2 -* View Name: schematic -************************************************************************ - -.SUBCKT CR4_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM11 net023 net024 Vbiasn gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM8 net025 net010 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM9 net024 net024 net023 gnd! nmos_rvt w=27.0n l=LA nfin=nA -MM7 net010 net010 net025 gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net025 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 net024 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM4 net010 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/bias/cr5_2.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/generator/bias/cr5_2.sp deleted file mode 100644 index 1612f2a910..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/bias/cr5_2.sp +++ /dev/null @@ -1,43 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: biasing_circuits -* Top Cell Name: CR5_2 -* View Name: schematic -* Netlisted on: Apr 4 17:13:49 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: biasing_circuits -* Cell Name: CR5_2 -* View Name: schematic -************************************************************************ - -.SUBCKT CR5_2 Vbiasn Vbiasp -*.PININFO Vbiasn:O Vbiasp:O -MM5 net014 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 net15 net014 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasp Vbiasn net15 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM6 net014 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/bias/cr6_3.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/generator/bias/cr6_3.sp deleted file mode 100644 index 4e8daf5bde..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/bias/cr6_3.sp +++ /dev/null @@ -1,43 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: biasing_circuits -* Top Cell Name: CR6_3 -* View Name: schematic -* Netlisted on: Apr 4 21:22:32 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: biasing_circuits -* Cell Name: CR6_3 -* View Name: schematic -************************************************************************ - -.SUBCKT CR6_3 Vbiasn1 Vbiasn2 Vbiasp -*.PININFO Vbiasn1:O Vbiasn2:O Vbiasp:O -MM2 Vbiasp Vbiasn2 Vbiasn1 gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn2 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM4 Vbiasn1 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM5 net15 net15 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn2 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM6 net15 Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/bias/cr7_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/generator/bias/cr7_1.sp deleted file mode 100644 index 1970b4ef8b..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/bias/cr7_1.sp +++ /dev/null @@ -1,41 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: biasing_circuits -* Top Cell Name: CR7_1 -* View Name: schematic -* Netlisted on: Apr 4 17:16:44 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: biasing_circuits -* Cell Name: CR7_1 -* View Name: schematic -************************************************************************ - -.SUBCKT CR7_1 Vbiasn -*.PININFO Vbiasn:O -RR1 Vbiasn net7 res=rK -RR0 vdd! net7 res=rK -RRF vdd! Vbiasn res=rK -MM1 net7 Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/bias/cr9_1.sp b/DesignDatabase/Testcases/OTA/OTA_topologies/generator/bias/cr9_1.sp deleted file mode 100644 index a0de1cb0a9..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/bias/cr9_1.sp +++ /dev/null @@ -1,39 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: biasing_circuits -* Top Cell Name: CR9_1 -* View Name: schematic -* Netlisted on: Apr 4 13:52:46 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: biasing_circuits -* Cell Name: CR9_1 -* View Name: schematic -************************************************************************ - -.SUBCKT CR9_1 Vbiasn -*.PININFO Vbiasn:O -RR1 net05 gnd! res=rK -RRF vdd! Vbiasn res=rK -MM0 Vbiasn Vbiasn net05 gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/local_generation/LG_load_biasn b/DesignDatabase/Testcases/OTA/OTA_topologies/generator/local_generation/LG_load_biasn deleted file mode 100644 index b84410674e..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/local_generation/LG_load_biasn +++ /dev/null @@ -1,39 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_LG -* Top Cell Name: LG_load_biasn -* View Name: schematic -* Netlisted on: Sep 13 00:30:40 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_LG -* Cell Name: LG_load_biasn -* View Name: schematic -************************************************************************ - -.SUBCKT LG_load_biasn Vbiasn1 Vbiasn2 Biasp -*.PININFO Biasp:I Vbiasn1:O Vbiasn2:O -MM15 Vbiasn2 Vbiasn2 Vbiasn1 gnd! nmos_rvt w=WA l=LA nfin=nA -MM13 Vbiasn1 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM14 Vbiasn2 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/local_generation/LG_load_biasn_LV b/DesignDatabase/Testcases/OTA/OTA_topologies/generator/local_generation/LG_load_biasn_LV deleted file mode 100644 index 91fb3830e2..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/local_generation/LG_load_biasn_LV +++ /dev/null @@ -1,39 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_LG -* Top Cell Name: LG_load_biasn_LV -* View Name: schematic -* Netlisted on: Sep 13 00:31:05 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_LG -* Cell Name: LG_load_biasn_LV -* View Name: schematic -************************************************************************ - -.SUBCKT LG_load_biasn_LV Vbiasn2 Biasp -*.PININFO Biasp:I Vbiasn2:O -MM13 net9 Vbiasn2 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM15 Vbiasn2 Vbiasn2 net9 gnd! nmos_rvt w=WA l=LA nfin=nA -MM14 Vbiasn2 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/local_generation/LG_load_biasn_S1 b/DesignDatabase/Testcases/OTA/OTA_topologies/generator/local_generation/LG_load_biasn_S1 deleted file mode 100644 index 492859c4c3..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/local_generation/LG_load_biasn_S1 +++ /dev/null @@ -1,38 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_LG -* Top Cell Name: LG_load_biasn_S1 -* View Name: schematic -* Netlisted on: Sep 13 00:31:22 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_LG -* Cell Name: LG_load_biasn_S1 -* View Name: schematic -************************************************************************ - -.SUBCKT LG_load_biasn_S1 Vbiasn1 Biasp -*.PININFO Biasp:I Vbiasn1:O -MM8 Vbiasn1 Vbiasn1 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn1 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/local_generation/LG_load_biasp b/DesignDatabase/Testcases/OTA/OTA_topologies/generator/local_generation/LG_load_biasp deleted file mode 100644 index 221c895703..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/local_generation/LG_load_biasp +++ /dev/null @@ -1,39 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_LG -* Top Cell Name: LG_load_biasp -* View Name: schematic -* Netlisted on: Sep 13 00:31:35 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_LG -* Cell Name: LG_load_biasp -* View Name: schematic -************************************************************************ - -.SUBCKT LG_load_biasp Biasn Vbiasp1 Vbiasp2 -*.PININFO Biasn:I Vbiasp1:O Vbiasp2:O -MM0 Vbiasp2 Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp2 Vbiasp2 Vbiasp1 vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp1 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/local_generation/LG_load_biasp_LV b/DesignDatabase/Testcases/OTA/OTA_topologies/generator/local_generation/LG_load_biasp_LV deleted file mode 100644 index 97c887f7c9..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/local_generation/LG_load_biasp_LV +++ /dev/null @@ -1,39 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_LG -* Top Cell Name: LG_load_biasp_LV -* View Name: schematic -* Netlisted on: Sep 13 00:31:47 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_LG -* Cell Name: LG_load_biasp_LV -* View Name: schematic -************************************************************************ - -.SUBCKT LG_load_biasp_LV Biasn Vbiasp2 -*.PININFO Biasn:I Vbiasp2:O -MM0 Vbiasp2 Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 net8 Vbiasp2 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasp2 Vbiasp2 net8 vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/local_generation/LG_load_biasp_S1 b/DesignDatabase/Testcases/OTA/OTA_topologies/generator/local_generation/LG_load_biasp_S1 deleted file mode 100644 index a641bc7f81..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/local_generation/LG_load_biasp_S1 +++ /dev/null @@ -1,38 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_LG -* Top Cell Name: LG_load_biasp_S1 -* View Name: schematic -* Netlisted on: Sep 13 00:31:58 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_LG -* Cell Name: LG_load_biasp_S1 -* View Name: schematic -************************************************************************ - -.SUBCKT LG_load_biasp_S1 Biasn Vbiasp1 -*.PININFO Biasn:I Vbiasp1:O -MM3 Vbiasp1 Vbiasp1 vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp1 Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -.ENDS - diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/local_generation/LG_nmos b/DesignDatabase/Testcases/OTA/OTA_topologies/generator/local_generation/LG_nmos deleted file mode 100644 index 6835cf4044..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/local_generation/LG_nmos +++ /dev/null @@ -1,38 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_LG -* Top Cell Name: LG_nmos -* View Name: schematic -* Netlisted on: Sep 13 00:32:17 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_LG -* Cell Name: LG_nmos -* View Name: schematic -************************************************************************ - -.SUBCKT LG_nmos Biasp Vbiasn -*.PININFO Biasp:I Vbiasn:O -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/local_generation/LG_nmos_l1 b/DesignDatabase/Testcases/OTA/OTA_topologies/generator/local_generation/LG_nmos_l1 deleted file mode 100644 index 19b63e9fea..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/local_generation/LG_nmos_l1 +++ /dev/null @@ -1,40 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_LG -* Top Cell Name: LG_nmos_l1 -* View Name: schematic -* Netlisted on: Sep 13 00:32:31 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_LG -* Cell Name: LG_nmos_l1 -* View Name: schematic -************************************************************************ - -.SUBCKT LG_nmos_l1 Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/local_generation/LG_npmos b/DesignDatabase/Testcases/OTA/OTA_topologies/generator/local_generation/LG_npmos deleted file mode 100644 index 52e1b3d54b..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/local_generation/LG_npmos +++ /dev/null @@ -1,42 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_LG -* Top Cell Name: LG_npmos -* View Name: schematic -* Netlisted on: Sep 13 00:32:50 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_LG -* Cell Name: LG_npmos -* View Name: schematic -************************************************************************ - -.SUBCKT LG_npmos Biasn Vbiasn Vbiasp -*.PININFO Biasn:I Vbiasn:O Vbiasp:O -MM4 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM10 neta Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM1 Vbiasn neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM0 neta neta vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/local_generation/LG_pmos b/DesignDatabase/Testcases/OTA/OTA_topologies/generator/local_generation/LG_pmos deleted file mode 100644 index 52d47f060c..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/local_generation/LG_pmos +++ /dev/null @@ -1,38 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_LG -* Top Cell Name: LG_pmos -* View Name: schematic -* Netlisted on: Sep 13 00:33:02 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_LG -* Cell Name: LG_pmos -* View Name: schematic -************************************************************************ - -.SUBCKT LG_pmos Biasn Vbiasp -*.PININFO Biasn:I Vbiasp:O -MM10 Vbiasp Biasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/local_generation/LG_pmos_l1 b/DesignDatabase/Testcases/OTA/OTA_topologies/generator/local_generation/LG_pmos_l1 deleted file mode 100644 index 35581c64ef..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/local_generation/LG_pmos_l1 +++ /dev/null @@ -1,40 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_LG -* Top Cell Name: LG_pmos_l1 -* View Name: schematic -* Netlisted on: Sep 13 00:33:15 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL gnd! -+ vdd! - -*.PIN gnd! -*+ vdd! - -************************************************************************ -* Library Name: OTA_LG -* Cell Name: LG_pmos_l1 -* View Name: schematic -************************************************************************ - -.SUBCKT LG_pmos_l1 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM0 Vbiasp Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 Vbiasn Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/local_generation/LG_pnmos b/DesignDatabase/Testcases/OTA/OTA_topologies/generator/local_generation/LG_pnmos deleted file mode 100644 index e9b984e9a6..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/local_generation/LG_pnmos +++ /dev/null @@ -1,42 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_LG -* Top Cell Name: LG_pnmos -* View Name: schematic -* Netlisted on: Sep 13 00:33:35 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_LG -* Cell Name: LG_pnmos -* View Name: schematic -************************************************************************ - -.SUBCKT LG_pnmos Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/local_generation/LG_pnmos_4 b/DesignDatabase/Testcases/OTA/OTA_topologies/generator/local_generation/LG_pnmos_4 deleted file mode 100644 index 4d4eb3978e..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/local_generation/LG_pnmos_4 +++ /dev/null @@ -1,42 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: OTA_LG -* Top Cell Name: LG_pnmos_4 -* View Name: schematic -* Netlisted on: Sep 13 00:33:48 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM - -*.GLOBAL vdd! -+ gnd! - -*.PIN vdd! -*+ gnd! - -************************************************************************ -* Library Name: OTA_LG -* Cell Name: LG_pnmos_4 -* View Name: schematic -************************************************************************ - -.SUBCKT LG_pnmos_4 Biasp Vbiasn Vbiasp -*.PININFO Biasp:I Vbiasn:O Vbiasp:O -MM1 Vbiasn Vbiasn gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM0 Vbiasp net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM8 net6 net6 gnd! gnd! nmos_rvt w=WA l=LA nfin=nA -MM2 Vbiasn Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM3 Vbiasp Vbiasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -MM10 net6 Biasp vdd! vdd! pmos_rvt w=WA l=LA nfin=nA -.ENDS - diff --git a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/merge_OTA.py b/DesignDatabase/Testcases/OTA/OTA_topologies/generator/merge_OTA.py deleted file mode 100644 index ede0acba90..0000000000 --- a/DesignDatabase/Testcases/OTA/OTA_topologies/generator/merge_OTA.py +++ /dev/null @@ -1,186 +0,0 @@ -#!/usr/bin/env python3 -# -*- coding: utf-8 -*- -""" -Created on Tue Oct 22 21:06:36 2019 - -@author: kunal001 -""" - -import os -import logging - -if not os.path.exists("./LOG"): - os.mkdir("./LOG") -elif os.path.exists("./LOG/read_netlist.log"): - os.rename("./LOG/read_netlist.log", "./LOG/read_netlist.log1") - -logging.basicConfig(filename='./LOG/read_netlist.log', level=logging.DEBUG) - -OTA_DIR = "OTA" -BIAS_DIR = "BIAS" -LG_DIR = "Local_generation" - -OTA_NETLIST = os.listdir(OTA_DIR) -LG_NETLIST = os.listdir(LG_DIR) -BIAS_NETLIST = os.listdir(BIAS_DIR) - - -class create_OTA_connection: - - def __init__(self,line): - self.line =line - self.bias_ports =[] - self.LG_connect_pins =[] - self.insts = [] - self.LG_input = None - self.ota_inst() - def ota_inst(self): - words=line.split() - for idx, port in enumerate(words): - if 'bias' in port: - words[idx]="LG_"+port - self.bias_ports.append("LG_"+port) - self.insts.append( "\nxiota "+ " ".join(words[2:]) + \ - " "+ words[1]) - def LG_pins(self,lg_pins,lg_type): - - if "LG_Vbiasn2" in self.bias_ports: - if "Vbiasn2" not in lg_pins: - logging.error("Vbiasn2 not in lg_pins:%s,%s",self.insts[0],lg_type) - return 0 - elif "LG_Vbiasp2" in self.bias_ports: - if "Vbiasp2" not in lg_pins: - logging.error("Vbiasp2 not in lg_pins:%s,%s",self.insts[0],lg_type) - return 0 - elif "LG_Vbiasn2" not in self.bias_ports: - if "Vbiasn2" in lg_pins: - logging.error("Vbiasn2 in lg_pins:%s,%s",self.insts[0],lg_type) - return 0 - elif "LG_Vbiasp2" not in self.bias_ports: - if "Vbiasp2" in lg_pins: - logging.error("Vbiasp2 in lg_pins:%s,%s",self.insts[0],lg_type) - return 0 - if "LG_Vbiasn1" not in self.bias_ports: - if "Vbiasn1" in lg_pins: - logging.error("Vbiasn1 in lg_pins:%s,%s",self.insts[0],lg_type) - return 0 - elif "LG_Vbiasp1" not in self.bias_ports: - if "Vbiasp1" in lg_pins: - logging.error("Vbiasp1 in lg_pins:%s,%s",self.insts[0],lg_type) - return 0 - words=lg_pins.split()[1:] - added = 0 - for idx, port in enumerate(words): - if 'bias' in port and port.endswith('O'): - check_port = "LG_"+port.replace(':O','') - words[idx] = check_port - if check_port in self.bias_ports: - self.LG_connect_pins.append(check_port) - added = 1 - elif port.endswith(':I') and 'ias' in port: - self.LG_input = port.replace(':I','') - words[idx]= self.LG_input - else: - words[idx] = port.replace(':I','').replace(':O','') - - if added ==1: - self.insts.append("\nxi"+lg_type+" " +" ".join(words) +" "+lg_type) - return 1 - else: - return 0 - - def BIAS_pins(self,bias_line): - words=bias_line.split() - for idx, port in enumerate(words): - port = port.replace("Vbias","Bias") - words[idx] = port - if self.LG_input ==port: - self.insts.append("\nxib"+words[1]+" "+ \ - " ".join(words[2:])+ " "+words[1]) - return 1 - - return 0 - -def read_LG_bias(file, connect): - BIAS_lines=[] - found=0 - if 'LG' in file: - FLAG =0 - with open(file, "r") as file: - name ="" - for line in file: - if ".SUBCKT" in line: - name = line.split()[1] - FLAG=1 - elif ".PININFO" in line: - found = connect.LG_pins(line,name) - elif ".ENDS" in line: - FLAG=0 - BIAS_lines.append(line) - if FLAG==1: - BIAS_lines.append(line) - if found: - return BIAS_lines - else: - return None - -def read_bias(file, connect): - BIAS_lines=[] - found=0 - if file.endswith('.sp'): - FLAG =0 - with open(file, "r") as file: - for line in file: - if ".SUBCKT" in line: - found=connect.BIAS_pins(line) - FLAG=1 - elif ".ENDS" in line: - FLAG=0 - BIAS_lines.append(line) - if FLAG==1: - BIAS_lines.append(line) - if found: - return BIAS_lines - else: - return None - -for ON in OTA_NETLIST: - if "_" in ON: - with open(OTA_DIR+"/"+ON, "r") as file: - OTA_lines = [] - for line in file: - if ".SUBCKT" in line: - connect = create_OTA_connection(line) - OTA_lines.append(line) - - for LN in LG_NETLIST: - for BN in BIAS_NETLIST: - LG_lines =[] - BG_lines =[] - connect.insts=[connect.insts[0]] - check_lg = read_LG_bias(LG_DIR+"/"+LN, connect) - if check_lg: - check_bias = read_bias(BIAS_DIR+"/"+BN, connect) - if check_bias: - print("Creating combination of: " +ON + ", " +LN + ", "+ BN) - fo= open("FULL_OTA/"+ON+"_"+LN+"_"+BN,"w") - LG_lines = LG_lines+check_lg - BG_lines = BG_lines + check_bias - for line in OTA_lines: - fo.write(line) - fo.write("\n") - for line in LG_lines: - fo.write(line) - fo.write("\n") - for line in BG_lines: - fo.write(line) - fo.write("\n") - - for connect_line in connect.insts: - fo.write(connect_line) - - fo.write("\n.END") - fo.close - - - diff --git a/DesignDatabase/Testcases/OTA/README.md b/DesignDatabase/Testcases/OTA/README.md deleted file mode 100644 index b024328b28..0000000000 --- a/DesignDatabase/Testcases/OTA/README.md +++ /dev/null @@ -1,4 +0,0 @@ -This folder contains the OTA circuits that have been tried on the tool - - -ota_2018_12_06 : Contains the files ( netlist (verilog), constraints, LEF) for a telescopic OTA with bias transistors sized on ASAP 7nm \ No newline at end of file diff --git a/DesignDatabase/Testcases/OTA/ota_2018_12_06/Circuit Description/Switched_capacitor_filter_ota.pdf b/DesignDatabase/Testcases/OTA/ota_2018_12_06/Circuit Description/Switched_capacitor_filter_ota.pdf deleted file mode 100644 index e1151dbcae..0000000000 Binary files a/DesignDatabase/Testcases/OTA/ota_2018_12_06/Circuit Description/Switched_capacitor_filter_ota.pdf and /dev/null differ diff --git a/DesignDatabase/Testcases/OTA/ota_2018_12_06/Constraints/ota.const b/DesignDatabase/Testcases/OTA/ota_2018_12_06/Constraints/ota.const deleted file mode 100644 index 5413a4ea39..0000000000 --- a/DesignDatabase/Testcases/OTA/ota_2018_12_06/Constraints/ota.const +++ /dev/null @@ -1,25 +0,0 @@ -SymmNet( {Vinp,L1_MM1_MM0/G1,Vinp} , {Vinn,L1_MM1_MM0/G2,Vinn}) -SymmNet( {net10,L1_MM1_MM0/D1,L1_MM10_MM2/S1} , {net11,L1_MM1_MM0/D2,L1_MM10_MM2/S2}) -SymmNet( {Voutn,L1_MM10_MM2/D1,L1_MM7_MM6/D1,Voutn} , {Voutp,L1_MM10_MM2/D2,L1_MM7_MM6/D2,Voutp}) -SymmNet( {net13,L1_MM7_MM6/S1,L1_MM8_MM9/D1}, {net12,L1_MM7_MM6/S2,L1_MM8_MM9/D2}) -CritNet(net6, mid) -CritNet(Vbiasn, mid) -CritNet(Vbiasp1, mid) -CritNet(Vbiasp2, mid) -CritNet(net10, min) -CritNet(net11, min) -CritNet(Voutn, min) -CritNet(Voutp, min) -CritNet(net13, min) -CritNet(net12, min) -MatchBlock(L0_MM16,L0_MM11) -MatchBlock(L0_MM11,L1_MM8_MM9) -MatchBlock(L0_MM14,L1_MM8_MM9) -MatchBlock(L0_MM131,L1_MM7_MM6) -MatchBlock(L0_MM132,L1_MM7_MM6) -MatchBlock(L0_MM17,L1_MM10_MM2) -MatchBlock(L0_MM18,L1_MM10_MM2) -MatchBlock(L0_MM12,L1_MM1_MM0) -MatchBlock(L0_MM15,L1_MM1_MM0) -MatchBlock(L0_MM12,L1_MM4_MM3) -MatchBlock(L0_MM15,L1_MM4_MM3) diff --git a/DesignDatabase/Testcases/OTA/ota_2018_12_06/LEF/ota.lef b/DesignDatabase/Testcases/OTA/ota_2018_12_06/LEF/ota.lef deleted file mode 100644 index a786c53298..0000000000 --- a/DesignDatabase/Testcases/OTA/ota_2018_12_06/LEF/ota.lef +++ /dev/null @@ -1,602 +0,0 @@ -VERSION 5.7 ; -BUSBITCHARS "[]" ; -DIVIDERCHAR "/" ; - -MACRO CMC_NMOS_25_1x10 - ORIGIN 0 0 ; - FOREIGN CMC_NMOS_25_1x10 0 0 ; - SIZE 2.16 BY 0.402 ; - PIN S2 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.256 0.32 2.012 0.338 ; - END - END S2 - PIN VSS - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER M2 ; - RECT 0 0 2.16 0.018 ; - END - END VSS - PIN VDD - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 0.384 2.16 0.402 ; - END - END VDD - PIN G - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER M2 ; - RECT 0.094 0.064 2.066 0.082 ; - END - END G - PIN D1 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.148 0.128 1.904 0.146 ; - END - END D1 - PIN D2 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.364 0.192 2.12 0.21 ; - END - END D2 - PIN S1 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.04 0.256 1.796 0.274 ; - END - END S1 - OBS - LAYER M1 ; - RECT 0 0 2.16 0.402 ; - END -END CMC_NMOS_25_1x10 - -MACRO CMC_PMOS_10_1x4 - ORIGIN 0 0 ; - FOREIGN CMC_PMOS_10_1x4 0 0 ; - SIZE 0.864 BY 0.402 ; - PIN S - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.04 0.32 0.716 0.338 ; - END - END S - PIN VDD - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER M2 ; - RECT 0 0.384 0.864 0.402 ; - END - END VDD - PIN VSS - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER M2 ; - RECT 0 0 0.864 0.018 ; - END - END VSS - PIN G - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.094 0.064 0.77 0.082 ; - END - END G - PIN D1 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.148 0.128 0.824 0.146 ; - END - END D1 - PIN D2 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.364 0.192 0.608 0.21 ; - END - END D2 - OBS - LAYER M1 ; - RECT 0 0 0.864 0.402 ; - END -END CMC_PMOS_10_1x4 - -MACRO CMC_PMOS_15_1x6 - ORIGIN 0 0 ; - FOREIGN CMC_PMOS_15_1x6 0 0 ; - SIZE 1.296 BY 0.402 ; - PIN S2 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.256 0.32 1.148 0.338 ; - END - END S2 - PIN VDD - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER M2 ; - RECT 0 0.384 1.296 0.402 ; - END - END VDD - PIN VSS - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER M2 ; - RECT 0 0 1.296 0.018 ; - END - END VSS - PIN G - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.094 0.064 1.202 0.082 ; - END - END G - PIN D1 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.148 0.128 1.04 0.146 ; - END - END D1 - PIN D2 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.364 0.192 1.256 0.21 ; - END - END D2 - PIN S1 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.04 0.256 0.932 0.274 ; - END - END S1 - OBS - LAYER M1 ; - RECT 0 0 1.296 0.402 ; - END -END CMC_PMOS_15_1x6 - -MACRO DP_NMOS_75_3x10 - ORIGIN 0 0 ; - FOREIGN DP_NMOS_75_3x10 0 0 ; - SIZE 2.16 BY 1.298 ; - PIN S - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.04 1.152 2.012 1.17 ; - END - PORT - LAYER M2 ; - RECT 0.148 0.576 2.12 0.594 ; - END - PORT - LAYER M2 ; - RECT 0.04 0.256 2.012 0.274 ; - END - END S - PIN VSS - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER M2 ; - RECT 0 0.896 2.16 0.914 ; - END - PORT - LAYER M2 ; - RECT 0 0.832 2.16 0.85 ; - END - PORT - LAYER M2 ; - RECT 0 0 2.16 0.018 ; - END - END VSS - PIN VDD - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER M2 ; - RECT 0 1.28 2.16 1.298 ; - END - PORT - LAYER M2 ; - RECT 0 0.448 2.16 0.466 ; - END - PORT - LAYER M2 ; - RECT 0 0.384 2.16 0.402 ; - END - END VDD - PIN D1 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.148 1.024 1.904 1.042 ; - END - PORT - LAYER M2 ; - RECT 0.256 0.704 2.012 0.722 ; - END - PORT - LAYER M2 ; - RECT 0.148 0.128 1.904 0.146 ; - END - END D1 - PIN D2 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.364 1.088 2.12 1.106 ; - END - PORT - LAYER M2 ; - RECT 0.04 0.64 1.796 0.658 ; - END - PORT - LAYER M2 ; - RECT 0.364 0.192 2.12 0.21 ; - END - END D2 - PIN G1 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.094 0.96 1.85 0.978 ; - END - PORT - LAYER M2 ; - RECT 0.31 0.768 2.066 0.786 ; - END - PORT - LAYER M2 ; - RECT 0.094 0.064 1.85 0.082 ; - END - END G1 - PIN G2 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.31 1.216 2.066 1.234 ; - END - PORT - LAYER M2 ; - RECT 0.094 0.512 1.85 0.53 ; - END - PORT - LAYER M2 ; - RECT 0.31 0.32 2.066 0.338 ; - END - END G2 - OBS - LAYER M1 ; - RECT 0 0 2.16 0.402 ; - RECT 0 0.402 2.16 0.85 ; - RECT 0 0.85 2.16 1.298 ; - END -END DP_NMOS_75_3x10 - -MACRO DiodeConnected_NMOS_5_1x1 - ORIGIN 0 0 ; - FOREIGN DiodeConnected_NMOS_5_1x1 0 0 ; - SIZE 0.216 BY 0.402 ; - PIN VSS - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER M2 ; - RECT 0 0 0.216 0.018 ; - END - END VSS - PIN D - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.094 0.064 0.176 0.082 ; - END - END D - PIN S - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 0.128 0.068 0.146 ; - END - END S - PIN VDD - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER M2 ; - RECT 0 0.384 0.216 0.402 ; - END - END VDD -END DiodeConnected_NMOS_5_1x1 - -MACRO DiodeConnected_PMOS_10_1x2 - ORIGIN 0 0 ; - FOREIGN DiodeConnected_PMOS_10_1x2 0 0 ; - SIZE 0.432 BY 0.402 ; - PIN VSS - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER M2 ; - RECT 0 0 0.432 0.018 ; - END - END VSS - PIN D - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.094 0.064 0.392 0.082 ; - END - END D - PIN S - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 0.128 0.284 0.146 ; - END - END S - PIN VDD - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER M2 ; - RECT 0 0.384 0.432 0.402 ; - END - END VDD -END DiodeConnected_PMOS_10_1x2 - -END LIBRARY -VERSION 5.7 ; -BUSBITCHARS "[]" ; -DIVIDERCHAR "/" ; - -VIA M2_M1_0 - VIARULE M2_M1 ; - CUTSIZE 0.018 0.018 ; - LAYERS M1 V1 M2 ; - CUTSPACING 0.018 0.018 ; - ENCLOSURE 0 0.005 0.005 0 ; - ROWCOL 1 1 ; -END M2_M1_0 - -VIA M2_M1_1 - VIARULE M2_M1 ; - CUTSIZE 0.018 0.018 ; - LAYERS M1 V1 M2 ; - CUTSPACING 0.018 0.018 ; - ENCLOSURE 0 0.005 0.005 0 ; - ROWCOL 1 1 ; -END M2_M1_1 - -MACRO DiodeConnected_PMOS_20_1x4 - ORIGIN 0 0 ; - FOREIGN DiodeConnected_PMOS_20_1x4 0 0 ; - SIZE 0.864 BY 0.402 ; - PIN VSS - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER M2 ; - RECT 0 0 0.864 0.018 ; - END - END VSS - PIN D - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.094 0.064 0.824 0.082 ; - END - END D - PIN S - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 0.128 0.716 0.146 ; - END - END S - PIN VDD - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER M2 ; - RECT 0 0.384 0.864 0.402 ; - END - END VDD -END DiodeConnected_PMOS_20_1x4 - -MACRO SCM_NMOS_50_1x12 - ORIGIN 0 0 ; - FOREIGN SCM_NMOS_50_1x12 0 0 ; - SIZE 2.592 BY 0.402 ; - PIN D1 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 1.228 0.192 1.472 0.21 ; - END - PORT - LAYER M2 ; - RECT 1.444 0.192 1.472 0.21 ; - END - END D1 - PIN VSS - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER M2 ; - RECT 0 0 2.592 0.018 ; - END - END VSS - PIN S - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.04 0.256 2.444 0.274 ; - END - END S - PIN VDD - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER M2 ; - RECT 0 0.384 2.592 0.402 ; - END - END VDD - PIN D2 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.148 0.128 2.552 0.146 ; - END - END D2 - OBS - LAYER M1 ; - RECT 0 0 2.592 0.402 ; - END -END SCM_NMOS_50_1x12 - -MACRO Switch_NMOS_10_1x1 - ORIGIN 0 0 ; - FOREIGN Switch_NMOS_10_1x1 0 0 ; - SIZE 0.432 BY 0.402 ; - PIN S - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.04 0.064 0.284 0.082 ; - END - END S - PIN VSS - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER M2 ; - RECT 0 0 0.432 0.018 ; - END - END VSS - PIN D - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.148 0.192 0.392 0.21 ; - END - END D - PIN G - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.094 0.128 0.338 0.146 ; - END - END G - PIN VDD - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER M2 ; - RECT 0 0.384 0.432 0.402 ; - END - END VDD -END Switch_NMOS_10_1x1 - -MACRO Switch_PMOS_10_1x1 - ORIGIN 0 0 ; - FOREIGN Switch_PMOS_10_1x1 0 0 ; - SIZE 0.432 BY 0.402 ; - PIN S - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.04 0.192 0.284 0.21 ; - END - END S - PIN VSS - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER M2 ; - RECT 0 0 0.432 0.018 ; - END - END VSS - PIN D - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.148 0.064 0.392 0.082 ; - END - END D - PIN G - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.094 0.128 0.338 0.146 ; - END - END G - PIN VDD - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER M2 ; - RECT 0 0.384 0.432 0.402 ; - END - END VDD -END Switch_PMOS_10_1x1 - -END LIBRARY diff --git a/DesignDatabase/Testcases/OTA/ota_2018_12_06/README.md b/DesignDatabase/Testcases/OTA/ota_2018_12_06/README.md deleted file mode 100644 index 8c7cb9dc1d..0000000000 --- a/DesignDatabase/Testcases/OTA/ota_2018_12_06/README.md +++ /dev/null @@ -1,17 +0,0 @@ -# INPUT for PnR tool -sc_block.v : block level netlist for switched capacitor -   This netlist contains two modules which need to be placed and routed hierarchicaly. -      1.switched_capacitor_filter : top level module , corresponding constraint are there in switched_capacitor_filter.const -      2.cascode_current_mirror_ota : sub module , corresponding constraint are there in cascode_current_mirror_ota.const - -sc.lef : lef file with block dimensions and pin locations - -# BLOCKS used (defined in lef, used in netlist) -1.CMC_NMOS_25_1 : common centroid transistors with gate connection -2.CMC_PMOS_10_1 : common centroid transistors with gate connection -3.CMC_PMOS_15_1 : common centroid transistors with gate connection -4.DP_NMOS_70_1 : Differential pair -5.SCM_NMOS_50 : current mirror -6.Cap_xxf: capacitance -7.Switch_NMOS_10 : transistor building block with 10 fins -8.Switch_PMOS_10 : transistor building block with 10 fins diff --git a/DesignDatabase/Testcases/OTA/ota_2018_12_06/Verilog Netlist/ota.v b/DesignDatabase/Testcases/OTA/ota_2018_12_06/Verilog Netlist/ota.v deleted file mode 100644 index 765d71686d..0000000000 --- a/DesignDatabase/Testcases/OTA/ota_2018_12_06/Verilog Netlist/ota.v +++ /dev/null @@ -1,46 +0,0 @@ -// Verilog HDL and netlist files of -// "pcell switched_capacitor_filter schematic" - -// Netlisted models - -// Library - pcell, Cell - cascode_current_mirror_ota, View - schematic -// LAST TIME SAVED: Aug 30 07:09:12 2018 -// NETLIST TIME: Nov 13 07:44:10 2018 - - -module cascode_current_mirror_ota ( Voutn, Voutp, Vinn, Vinp, Id ); - -//output Voutn, Voutp; - -//input Vbiasn, Vbiasp1, Vbiasp2, Vinn, Vinp; - -SCM_NMOS_50_1x12 L1_MM4_MM3 ( .D1(Id), .D2(net6), .S(GND) ); -CMC_NMOS_25_1x10 L1_MM10_MM2 ( .D1(Voutn), .D2(Voutp), .G(net_vbiasn), .S1(net10), .S2(net11) ); -CMC_PMOS_15_1x6 L1_MM7_MM6 ( .D1(Voutn), .D2(Voutp), .G(net_vbiasp), .S1(net13), .S2(net12) ); -CMC_PMOS_10_1x4 L1_MM8_MM9 ( .D1(net13), .D2(net12), .G(net_vbiasp1), .S(VDD) ); -DP_NMOS_75_3x10 L1_MM1_MM0 ( .D1(net10), .D2(net11), .G1(Vinp), .G2(Vinn), .S(net6) ); -//bias transistors -DiodeConnected_NMOS_5_1x1 L0_MM17 ( .D(net_vbiasn), .S(net6) ); - -DiodeConnected_PMOS_10_1x2 L0_MM11 ( .D(net_vbiasp1), .S(VDD) ); - -//DiodeConnected_PMOS_20_1x4 L0_MM13 ( .D(net_vbiasp), .S(net1_vbiasp) ); -DiodeConnected_PMOS_10_1x2 L0_MM131 ( .D(net_vbiasp), .S(net1_vbiasp) ); -DiodeConnected_PMOS_10_1x2 L0_MM132 ( .D(net_vbiasp), .S(net1_vbiasp) ); -DiodeConnected_PMOS_20_1x4 L0_MM14 ( .D(net1_vbiasp), .S(VDD) ); - -Switch_NMOS_10_1x1 L0_MM12 ( .D(net_vbiasp1), .G(Id), .S(GND) ); -Switch_NMOS_10_1x1 L0_MM15 ( .D(net_vbiasp), .G(Id), .S(GND) ); -Switch_PMOS_10_1x1 L0_MM16 ( .D(net_vbiasn), .G(net_vbiasp), .S(VDD) ); - -//dummy transistors -DiodeConnected_NMOS_5_1x1 L0_MM18 ( .D(GND), .S(GND) ); - - -//idc I3 ( .PLUS(cds_globals.vdd_), .MINUS(net1)); - -endmodule - -// End HDL models - -`endcelldefine diff --git a/DesignDatabase/Testcases/README.md b/DesignDatabase/Testcases/README.md deleted file mode 100644 index 7a7a63672e..0000000000 --- a/DesignDatabase/Testcases/README.md +++ /dev/null @@ -1,12 +0,0 @@ -This folder contains circuits that have been tried on the tool - - -Equalizer : Contains the different testcases based on the EQUALIZER design/circuit - -OTA : Contains the different testcases based on the OTA design/circuit - -Switched Capacitor Filter : Contains the different testcases based on the SWITCHED CAPACITOR FILTER design/circuit - -USC : Contains the different testcases provided by the University of Southern California - -UVA : Contains the different testcases provided by the University of Virginia diff --git a/DesignDatabase/Testcases/Switched Capacitor Filter/README.md b/DesignDatabase/Testcases/Switched Capacitor Filter/README.md deleted file mode 100644 index 7e4e76b54a..0000000000 --- a/DesignDatabase/Testcases/Switched Capacitor Filter/README.md +++ /dev/null @@ -1,17 +0,0 @@ -This folder contains the different versions of switched capacitor filter circuits (and some associated circuits) that have been tried on the tool - -The versions are named chronologically (YYYY_MM_DD) and are described below - -switched_capacitor_filter_2018_10_09 : Contains the files (eg. modified netlist (bookshelf format), constraints) of a preliminary first order SC Filter structure that hasn't been sized - -switched_capacitor_filter_2018_11_01 : Contains the files (eg. modified netlist (verilog), constraints) of a preliminary first order SC Filter structure that hasn't been sized - -switched_capacitor_filter_2018_11_10 : Contains the files (eg. modified netlist (verilog), constraints, LEF) of a preliminary first order SC Filter structure that hasn't been sized - -switched_capacitor_filter_2018_11_20 : Contains the files (eg. modified netlist (verilog), constraints, LEF) of a preliminary first order SC Filter structure that hasn't been sized - -switched_capacitor_filter_2018_12_06 : Contains the files (eg. modified netlist (verilog), constraints, LEF) of a preliminary first order SC Filter structure that has been sized - -switched_capacitor_filter_2018_12_10 : Contains the files (eg. modified netlist (verilog), constraints, LEF) of a preliminary first order SC Filter structure that has been sized and has additional hierarchy introduced - -common_centroid_capacitor_array_2019_01_31 : Contains the files (eg. modified netlist (verilog), constraints, LEF) of the capacitor array in the filter circuit that needs to be placed in common centroid configuration \ No newline at end of file diff --git a/DesignDatabase/Testcases/Switched Capacitor Filter/common_centroid_capacitor_array_2019_01_31/Constraints/switched_capacitor_combination.const b/DesignDatabase/Testcases/Switched Capacitor Filter/common_centroid_capacitor_array_2019_01_31/Constraints/switched_capacitor_combination.const deleted file mode 100644 index a261c82fb7..0000000000 --- a/DesignDatabase/Testcases/Switched Capacitor Filter/common_centroid_capacitor_array_2019_01_31/Constraints/switched_capacitor_combination.const +++ /dev/null @@ -1,3 +0,0 @@ - -{CC0}, {6}, {Cap_10f_1x1} -{CC4, CC3}, {6, 3}, {Cap_10f_1x1} diff --git a/DesignDatabase/Testcases/Switched Capacitor Filter/common_centroid_capacitor_array_2019_01_31/LEF/common_centroid.lef b/DesignDatabase/Testcases/Switched Capacitor Filter/common_centroid_capacitor_array_2019_01_31/LEF/common_centroid.lef deleted file mode 100644 index 93ccfb752a..0000000000 --- a/DesignDatabase/Testcases/Switched Capacitor Filter/common_centroid_capacitor_array_2019_01_31/LEF/common_centroid.lef +++ /dev/null @@ -1,111 +0,0 @@ -VERSION 5.7 ; -BUSBITCHARS "[]" ; -DIVIDERCHAR "/" ; - -MACRO Cap_10f_1x1 - ORIGIN 0 0 ; - FOREIGN Cap_10f_1x1 0 0 ; - SIZE 2.214 BY 2.214 ; - PIN PLUS - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 2.196 2.214 2.214 ; - END - END PLUS - PIN MINUS - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 0 2.214 0.018 ; - END - END MINUS - OBS - LAYER M1 ; - RECT 0 0 2.214 2.214 ; - END - OBS - LAYER M2 ; - RECT 0.018 0.018 2.196 2.196 ; - END - OBS - LAYER M3 ; - RECT 0 0 2.214 2.214 ; - END -END Cap_10f_1x1 - -MACRO Switch_NMOS_10_1x1 - ORIGIN 0 0 ; - FOREIGN Switch_NMOS_10_1x1 0 0 ; - SIZE 0.432 BY 0.402 ; - PIN S - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.04 0.064 0.284 0.082 ; - END - END S - PIN VSS - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER M2 ; - RECT 0 0 0.432 0.018 ; - END - END VSS - PIN D - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.148 0.192 0.392 0.21 ; - END - END D - PIN G - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.094 0.128 0.338 0.146 ; - END - END G - PIN VDD - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER M2 ; - RECT 0 0.384 0.432 0.402 ; - END - END VDD - -END Switch_NMOS_10_1x1 - - -END LIBRARY -VERSION 5.7 ; -BUSBITCHARS "[]" ; -DIVIDERCHAR "/" ; - -VIA M2_M1_0 - VIARULE M2_M1 ; - CUTSIZE 0.018 0.018 ; - LAYERS M1 V1 M2 ; - CUTSPACING 0.018 0.018 ; - ENCLOSURE 0 0.005 0.005 0 ; - ROWCOL 1 1 ; -END M2_M1_0 - -VIA M2_M1_1 - VIARULE M2_M1 ; - CUTSIZE 0.018 0.018 ; - LAYERS M1 V1 M2 ; - CUTSPACING 0.018 0.018 ; - ENCLOSURE 0 0.005 0.005 0 ; - ROWCOL 1 1 ; -END M2_M1_1 - - -END LIBRARY diff --git a/DesignDatabase/Testcases/Switched Capacitor Filter/common_centroid_capacitor_array_2019_01_31/Verilog Netlist/common_centroid.v b/DesignDatabase/Testcases/Switched Capacitor Filter/common_centroid_capacitor_array_2019_01_31/Verilog Netlist/common_centroid.v deleted file mode 100644 index 3eea553906..0000000000 --- a/DesignDatabase/Testcases/Switched Capacitor Filter/common_centroid_capacitor_array_2019_01_31/Verilog Netlist/common_centroid.v +++ /dev/null @@ -1,107 +0,0 @@ -// Verilog HDL and netlist files of -// "pcell switched_capacitor_filter schematic" - -// Netlisted models - -// Library - pcell, Cell - cascode_current_mirror_ota, View - schematic -// LAST TIME SAVED: Aug 30 07:09:12 2018 -// NETLIST TIME: Nov 13 07:44:10 2018 -`timescale 1ns / 1ns -// Library - pcell, Cell - switched_capacitor_filter, View - -//schematic -// LAST TIME SAVED: Aug 30 07:08:50 2018 -// NETLIST TIME: Nov 13 07:44:10 2018 -`timescale 1ns / 1ns - -module switched_capacitor_combination ( Vout, Vin_ota, Vin, phi2, phi1, agnd ); - -output Vout, Vin_ota; - -input Vin, phi2, phi1, agnd; - -specify - specparam CDS_LIBNAME = "pcell"; - specparam CDS_CELLNAME = "switched_capacitor_combination"; - specparam CDS_VIEWNAME = "schematic"; -endspecify - -Switch_NMOS_10_1x1 L0_MM0 ( .S(net3), .G(phi1), .D(Vin)); -Switch_NMOS_10_1x1 L0_MM10 ( .S(net3), .G(phi2), .D(agnd)); -Cap_60f CC4 ( .PLUS(net6), .MINUS(net3)); -Switch_NMOS_10_1x1 L0_MM9 ( .S(net6), .G(phi2), .D(agnd)); -Cap_30f CC3 ( .PLUS(net6), .MINUS(net12)); -Switch_NMOS_10_1x1 L0_MM11 ( .S(net12), .G(phi1), .D(agnd)); -Switch_NMOS_10_1x1 L0_MM8 ( .S(Vout), .G(phi2), .D(net12)); -Switch_NMOS_10_1x1 L0_MM1 ( .S(Vin_ota), .G(phi1), .D(net6)); -Cap_60f CC0 ( .PLUS(Vin_ota), .MINUS(Vout)); - -endmodule - -module common_centroid ( Voutn, Voutp, Vinp, Vinn, Id, agnd, clk ); - - -specify - specparam CDS_LIBNAME = "pcell"; - specparam CDS_CELLNAME = "switched_capacitor_filter"; - specparam CDS_VIEWNAME = "schematic"; -endspecify - -//vdc V5 ( .PLUS(cds_globals.vdd_), .MINUS(cds_globals.gnd_)); -//vdc V4 ( .PLUS(Vinp), .MINUS(cds_globals.gnd_)); -//vdc V3 ( .PLUS(Vinn), .MINUS(cds_globals.gnd_)); -//vdc V2 ( .PLUS(Vbiasp2), .MINUS(cds_globals.gnd_)); -//vdc V1 ( .PLUS(Vbiasp1), .MINUS(cds_globals.gnd_)); -//vdc V0 ( .PLUS(Vbiasn), .MINUS(cds_globals.gnd_)); -//cascode_current_mirror_ota I0 ( .Voutn(Voutn), .Voutp(Voutp), .Vbiasn(Vbiasn), .Vbiasp1(Vbiasp1), .Vbiasp2(Vbiasp2), .Vinn(Vinn_ota), .Vinp(Vinp_ota)); -//telescopic_ota I0 ( .Voutn(Voutn), .Voutp(Voutp), .Vinn(Vinn), .Vinp(Vinp), .Id(Id), .Vg(Vg)); -switched_capacitor_combination I1 ( .Vout(Voutp), .Vin_ota(Vinn_ota), .Vin(Vinp), .phi2(phi2), .phi1(phi1), .agnd(agnd)); -switched_capacitor_combination I2 ( .Vout(Voutn), .Vin_ota(Vinp_ota), .Vin(Vinn), .phi2(phi2), .phi1(phi1), .agnd(agnd)); -//common_mode_feedback I3 ( .Vg(Vg), .Va(Voutp), .Vb(Voutn), .phi1(phi1), .phi2(phi2), .Vbias_in(Id), .Vcm_in(agnd)); -//non_overlapping_clock_generator I4 ( .digital_vdd(cds_globals.vdd_), .digital_vss(cds_globals.gnd_), .clk(clk), .phi1(phi1), .phi2(phi2)); -//Cap_30f_1x3 CC5 ( .PLUS(Vinn_ota), .MINUS(Vinn)); -//Cap_30f_1x3 CC7 ( .PLUS(Vinp_ota), .MINUS(Vinp)); -//Cap_60f_2x3 CC8 ( .PLUS(Voutp), .MINUS(cds_globals.gnd_)); -//Cap_60f_2x3 CC9 ( .PLUS(Voutn), .MINUS(cds_globals.gnd_)); - - - -//Cap_60f_2x3 CC7 ( .PLUS(net7), .MINUS(Vinp)); -//Cap_60f_2x3 CC6 ( .PLUS(net5), .MINUS(net4)); -//Cap_60f_2x3 CC5 ( .PLUS(net23), .MINUS(Vinn)); -//Cap_60f_2x3 CC4 ( .PLUS(net6), .MINUS(net3)); -//Cap_32f_1x1 CC3 ( .PLUS(net6), .MINUS(net12)); -//Cap_32f_1x1 CC2 ( .PLUS(net7), .MINUS(Voutn)); -//Cap_32f_1x1 CC1 ( .PLUS(net5), .MINUS(net11)); -//Cap_32f_1x1 CC0 ( .PLUS(net23), .MINUS(Voutp)); -//Switch_NMOS_10_1x1 L0_MM11 ( .S(net12), .G(phi1), .D(cds_globals.gnd_)); -//Switch_NMOS_10_1x1 L0_MM10 ( .S(net3), .G(phi2), .D(cds_globals.gnd_)); -//Switch_NMOS_10_1x1 L0_MM9 ( .S(net6), .G(phi2), .D(cds_globals.gnd_)); -//Switch_NMOS_10_1x1 L0_MM8 ( .S(Voutp), .G(phi2), .D(net12)); -//Switch_NMOS_10_1x1 L0_MM7 ( .S(net11), .G(phi2), .D(Voutn)); -//Switch_NMOS_10_1x1 L0_MM6 ( .S(cds_globals.gnd_), .G(phi1), .D(net11)); -//Switch_NMOS_10_1x1 L0_MM5 ( .S(cds_globals.gnd_), .G(phi2), .D(net5)); -//Switch_NMOS_10_1x1 L0_MM4 ( .S(cds_globals.gnd_), .G(phi2), .D(net4)); -//Switch_NMOS_10_1x1 L0_MM3 ( .S(net5), .G(phi1), .D(net7)); -//Switch_NMOS_10_1x1 L0_MM2 ( .S(Vinn), .G(phi1), .D(net4)); -//Switch_NMOS_10_1x1 L0_MM1 ( .S(net23), .G(phi1), .D(net6)); -//Switch_NMOS_10_1x1 L0_MM0 ( .S(net3), .G(phi1), .D(Vinp)); -//vpulse V7 ( .PLUS(phi2), .MINUS(cds_globals.gnd_)); -//vpulse V6 ( .PLUS(phi1), .MINUS(cds_globals.gnd_)); - -endmodule - - -// End HDL models -// Global nets module - -`celldefine -module cds_globals; - - -supply0 gnd_; - -supply1 vdd_; - - -endmodule -`endcelldefine diff --git a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_10_09/Bookshelf_format_files/sc.blocks b/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_10_09/Bookshelf_format_files/sc.blocks deleted file mode 100644 index e556b21c5e..0000000000 --- a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_10_09/Bookshelf_format_files/sc.blocks +++ /dev/null @@ -1,138 +0,0 @@ -#UMN blocks 1.0 -# Created : August 31 19:15:43 -# User : madhu028@umn.edu -# Platform : Linux - -NumSoftRectangularBlocks : 1 -NumHardRectilinearBlocks : 16 -NumTerminals : 12 - -L0_MM0 hardrectilinear 4 (0, 0) (0, 414) (324, 414) (324, 0) -L0_MM1 hardrectilinear 4 (0, 0) (0, 414) (324, 414) (324, 0) -L0_MM2 hardrectilinear 4 (0, 0) (0, 414) (324, 414) (324, 0) -L0_MM3 hardrectilinear 4 (0, 0) (0, 414) (324, 414) (324, 0) -L0_MM4 hardrectilinear 4 (0, 0) (0, 414) (324, 414) (324, 0) -L0_MM5 hardrectilinear 4 (0, 0) (0, 414) (324, 414) (324, 0) -L0_MM6 hardrectilinear 4 (0, 0) (0, 414) (324, 414) (324, 0) -L0_MM7 hardrectilinear 4 (0, 0) (0, 414) (324, 414) (324, 0) -L0_MM8 hardrectilinear 4 (0, 0) (0, 414) (324, 414) (324, 0) -L0_MM9 hardrectilinear 4 (0, 0) (0, 414) (324, 414) (324, 0) -L0_MM10 hardrectilinear 4 (0, 0) (0, 414) (324, 414) (324, 0) -L0_MM11 hardrectilinear 4 (0, 0) (0, 414) (324, 414) (324, 0) - -L1_CC5_CC7 hardrectilinear 4 (0, 0) (0, 452) (346, 452) (346, 0) -L1_CC4_CC6 hardrectilinear 4 (0, 0) (0, 452) (638, 452) (638, 0) -L1_CC1_CC3 hardrectilinear 4 (0, 0) (0, 452) (638, 452) (638, 0) -L1_CC0_CC2 hardrectilinear 4 (0, 0) (0, 452) (638, 452) (638, 0) - -I0 softrectilinear ota - -BLOCK I0 : 10 -gnd! -vdd! -Vinp -Vinn -Vbiasn -Vbiasp1 -Vbiasp2 -Voutp -Voutn -Id - -BLOCK L0_MM0 : 3 -G M1 (110,280) (110,414) (146,414) (146,280) -D M1 (90,0) (90,118) (126,118) (126,0) -S M1 (198,0) (198,118) (234,118) (234,0) - -BLOCK L0_MM1 : 3 -G M1 (110,280) (110,414) (146,414) (146,280) -D M1 (90,0) (90,118) (126,118) (126,0) -S M1 (198,0) (198,118) (234,118) (234,0) - -BLOCK L0_MM2 : 3 -G M1 (110,280) (110,414) (146,414) (146,280) -D M1 (90,0) (90,118) (126,118) (126,0) -S M1 (198,0) (198,118) (234,118) (234,0) - -BLOCK L0_MM3 : 3 -G M1 (110,280) (110,414) (146,414) (146,280) -D M1 (90,0) (90,118) (126,118) (126,0) -S M1 (198,0) (198,118) (234,118) (234,0) - -BLOCK L0_MM4 : 3 -G M1 (110,280) (110,414) (146,414) (146,280) -D M1 (90,0) (90,118) (126,118) (126,0) -S M1 (198,0) (198,118) (234,118) (234,0) - -BLOCK L0_MM5 : 3 -G M1 (110,280) (110,414) (146,414) (146,280) -D M1 (90,0) (90,118) (126,118) (126,0) -S M1 (198,0) (198,118) (234,118) (234,0) - -BLOCK L0_MM6 : 3 -G M1 (110,280) (110,414) (146,414) (146,280) -D M1 (90,0) (90,118) (126,118) (126,0) -S M1 (198,0) (198,118) (234,118) (234,0) - -BLOCK L0_MM7 : 3 -G M1 (110,280) (110,414) (146,414) (146,280) -D M1 (90,0) (90,118) (126,118) (126,0) -S M1 (198,0) (198,118) (234,118) (234,0) - -BLOCK L0_MM8 : 3 -G M1 (110,280) (110,414) (146,414) (146,280) -D M1 (90,0) (90,118) (126,118) (126,0) -S M1 (198,0) (198,118) (234,118) (234,0) - -BLOCK L0_MM9 : 3 -G M1 (110,280) (110,414) (146,414) (146,280) -D M1 (90,0) (90,118) (126,118) (126,0) -S M1 (198,0) (198,118) (234,118) (234,0) - -BLOCK L0_MM10 : 3 -G M1 (110,280) (110,414) (146,414) (146,280) -D M1 (90,0) (90,118) (126,118) (126,0) -S M1 (198,0) (198,118) (234,118) (234,0) - -BLOCK L0_MM11 : 3 -G M1 (110,280) (110,414) (146,414) (146,280) -D M1 (90,0) (90,118) (126,118) (126,0) -S M1 (198,0) (198,118) (234,118) (234,0) - -BLOCK L1_CC5_CC7 : 4 -CP1 M1 (10,226) (10,426) (46,426) (46,226) -CP2 M1 (300,226) (300,426) (336,426) (336,226) -CN1 M1 (82,0) (82,128) (118,128) (118,0) -CN2 M1 (228,0) (228,128) (264,128) (264,0) - -BLOCK L1_CC4_CC6 : 4 -CP1 M1 (10,226) (10,426) (46,426) (46,226) -CP2 M1 (592,226) (592,426) (628,426) (628,226) -CN1 M1 (82,0) (82,128) (118,128) (118,0) -CN2 M1 (520,0) (520,128) (556,128) (556,0) - -BLOCK L1_CC1_CC3 : 4 -CP1 M1 (10,226) (10,426) (46,426) (46,226) -CP2 M1 (592,226) (592,426) (628,426) (628,226) -CN1 M1 (82,0) (82,128) (118,128) (118,0) -CN2 M1 (520,0) (520,128) (556,128) (556,0) - -BLOCK L1_CC0_CC2 : 4 -CP1 M1 (10,226) (10,426) (46,426) (46,226) -CP2 M1 (592,226) (592,426) (628,426) (628,226) -CN1 M1 (82,0) (82,128) (118,128) (118,0) -CN2 M1 (520,0) (520,128) (556,128) (556,0) - -gnd! M1 terminal -vdd! M1 terminal -Vinp M1 terminal -Vinn M1 terminal -Vbiasn M1 terminal -Vbiasp1 M1 terminal -Vbiasp2 M1 terminal -Voutp M1 terminal -Voutn M1 terminal -phi1 M1 terminal -phi2 M1 terminal -Id terminal - diff --git a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_10_09/Bookshelf_format_files/sc.const b/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_10_09/Bookshelf_format_files/sc.const deleted file mode 100644 index afb588d3c9..0000000000 --- a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_10_09/Bookshelf_format_files/sc.const +++ /dev/null @@ -1,22 +0,0 @@ -CritNet(net7, min) -CritNet(net23, min) -SymmNet({Voutn,L1_CC0_CC2/CN2,L0_MM7/D,I0/Voutn},{Voutp,L1_CC0_CC2/CN1,L0_MM8/S,I0/Voutp}) -SymmNet({net7,L1_CC5_CC7/CP2,L1_CC0_CC2/CP2,I0/Vinp,L0_MM3/D},{net23,L1_CC5_CC7/CP1,L1_CC0_CC2/CP1,I0/Vinn,L0_MM1/S}) -SymmNet({net11,L0_MM6/D,L0_MM7/S,L1_CC1_CC3/CN1},{net12,L0_MM11/S,L0_MM8/D,L1_CC1_CC3/CN2}) -SymmNet({net5,L1_CC4_CC6/CP2,L1_CC1_CC3/CP1,L0_MM5/D,L0_MM3/S},{net6,L1_CC4_CC6/CP1,L1_CC1_CC3/CP2,L0_MM9/S,L0_MM1/D}) -SymmNet({net4,L1_CC4_CC6/CN2,L0_MM2/D,L0_MM4/D},{net3,L1_CC4_CC6/CN1,L0_MM0/S,L0_MM10/S}) -SymmNet({Vinn,L1_CC5_CC7/CN1,L0_MM2/S},{Vinp,L1_CC5_CC7/CN2,L0_MM0/D}) -ShieldNet(Vinn) -ShieldNet(Vinp) -ShieldNet(net3) -ShieldNet(net4) -ShieldNet(net5) -ShieldNet(net6) -ShieldNet(net7) -ShieldNet(net23) -MatchBlock(L0_MM0,L0_MM2) -MatchBlock(L0_MM10,L0_MM4) -MatchBlock(L0_MM9,L0_MM5) -MatchBlock(L0_MM3,L0_MM1) -MatchBlock(L0_MM6,L0_MM11) -MatchBlock(L0_MM7,L0_MM8) diff --git a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_10_09/Bookshelf_format_files/sc.nets b/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_10_09/Bookshelf_format_files/sc.nets deleted file mode 100644 index 695855cefb..0000000000 --- a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_10_09/Bookshelf_format_files/sc.nets +++ /dev/null @@ -1,102 +0,0 @@ -#UMN nets 1.0 -# Created : August 31 19:15:43 -# User : madhu028@umn.edu -# Platform : Linux - -NumNets : 20 -NumPins : 61 - -net23 : 4 -L1_CC5_CC7 : CP1 -L1_CC0_CC2 : CP1 -L0_MM1 : S -I0 : Vinn -net3 : 3 -L0_MM0 : S -L0_MM10 : S -L1_CC4_CC6 : CN1 -net12 : 3 -L0_MM11 : S -L0_MM8 : D -L1_CC1_CC3 : CN2 -net7 : 4 -L0_MM3 : D -L1_CC5_CC7 : CP2 -L1_CC0_CC2 : CP2 -I0 : Vinp -net5 : 4 -L0_MM5 : D -L0_MM3 : S -L1_CC4_CC6 : CP2 -L1_CC1_CC3 : CP1 -net6 : 4 -L0_MM9 : S -L0_MM1 : D -L1_CC4_CC6 : CP1 -L1_CC1_CC3 : CP2 -Vbiasn : 2 -terminal Vbiasn -I0 : Vbiasn -Vbiasp1 : 2 -terminal Vbiasp1 -I0 : Vbiasp1 -Vbiasp2 : 2 -terminal Vbiasp2 -I0 : Vbiasp2 -Vinn : 3 -L0_MM2 : S -L1_CC5_CC7 : CN1 -terminal Vinn -Vinp : 3 -L0_MM0 : D -L1_CC5_CC7 : CN2 -terminal Vinp -Voutn : 4 -L0_MM7 : D -L1_CC0_CC2 : CN2 -I0 : Voutn -terminal Voutn -Voutp : 4 -L0_MM8 : S -L1_CC0_CC2 : CN1 -I0 : Voutp -terminal Voutp -phi1 : 7 -L0_MM11 : G -L0_MM6 : G -L0_MM1 : G -L0_MM3 : G -L0_MM0 : G -L0_MM2 : G -terminal phi1 -net4 : 3 -L0_MM2 : D -L0_MM4 : D -L1_CC4_CC6 : CN2 -phi2 : 7 -L0_MM8 : G -L0_MM7 : G -L0_MM9 : G -L0_MM5 : G -L0_MM4 : G -L0_MM10 : G -terminal phi2 -vdd! : 2 -I0 : vdd! -terminal vdd! -Id : 2 -terminal Id -I0 : Id -gnd! : 7 -L0_MM11 : D -L0_MM6 : S -L0_MM9 : D -L0_MM5 : S -L0_MM4 : S -L0_MM10 : D -I0 : gnd! -terminal gnd! -net11 : 3 -L0_MM6 : D -L0_MM7 : S -L1_CC1_CC3 :CN1 diff --git a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_10_09/Bookshelf_format_files/sc_modified_netlist b/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_10_09/Bookshelf_format_files/sc_modified_netlist deleted file mode 100644 index c6638454a7..0000000000 --- a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_10_09/Bookshelf_format_files/sc_modified_netlist +++ /dev/null @@ -1,93 +0,0 @@ -//SUB MODULE DEFINATIONS -//Block_type -instance_name -external_nets -internal_nets -size - -Level_0 -NMOS -L0_MM0 -(Vinp,phi1,net3) -(Vinp,phi1,net3,gnd!) -3 -NMOS -L0_MM1 -(net6,phi1,net23) -(net6,phi1,net23,gnd!) -3 -NMOS -L0_MM2 -(net4,phi1,Vinn) -(net4,phi1,Vinn,gnd!) -3 -NMOS -L0_MM3 -(net7, phi1,net5) -(net7,phi1,net5,gnd!) -3 -NMOS -L0_MM4 -(net4, phi2,gnd!) -(net4,phi2,gnd!,gnd!) -3 -NMOS -L0_MM5 -(net5, phi2,gnd!) -(net5,phi2,gnd!,gnd!) -3 -NMOS -L0_MM6 -(net11, phi1,gnd!) -(net11,phi1,gnd!,gnd!) -3 -NMOS -L0_MM7 -(Voutn, phi2,net11) -(Voutn,phi2,net11,gnd!) -3 -NMOS -L0_MM8 -(net12, phi2,Voutp) -(net12,phi2,Voutp,gnd!) -3 -NMOS -L0_MM9 -(gnd!, phi2,net6) -(gnd!,phi2,net6,gnd!) -3 -NMOS -L0_MM10 -(gnd!, phi2,net3) -(gnd!,phi2,net3,gnd!) -3 -NMOS -L0_MM11 -(gnd!, phi1,net12) -(gnd!,phi1,net12,gnd!) -3 - - -Level_1 -CMC_CAP -L1_CC5_CC7 -(net23, net7, Vinn, Vinp) -((net23,Vinn),(net7,Vinp)) -5p -CMC_CAP -L1_CC4_CC6 -(net6, net5, net3, net4) -((net6,net3),(net5,net4)) -10p -CMC_CAP -L1_CC1_CC3 -(net5, net6, net11, net12) -((net5,net11),(net6,net12)) -10p -CMC_CAP -L1_CC0_CC2 -(net23, net7, Voutp, Voutn) -((net23,Voutp),(net7,Voutn)) -10p - - diff --git a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_10_09/Circuit Description/Switched_capacitor_filter1.pdf b/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_10_09/Circuit Description/Switched_capacitor_filter1.pdf deleted file mode 100644 index 5f7d00cdab..0000000000 Binary files a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_10_09/Circuit Description/Switched_capacitor_filter1.pdf and /dev/null differ diff --git a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_10_09/Circuit Description/Switched_capacitor_filter_ota.pdf b/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_10_09/Circuit Description/Switched_capacitor_filter_ota.pdf deleted file mode 100644 index e1151dbcae..0000000000 Binary files a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_10_09/Circuit Description/Switched_capacitor_filter_ota.pdf and /dev/null differ diff --git a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_10_09/Circuit Description/layout_switched_cap.jpg b/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_10_09/Circuit Description/layout_switched_cap.jpg deleted file mode 100644 index 6cd564fc63..0000000000 Binary files a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_10_09/Circuit Description/layout_switched_cap.jpg and /dev/null differ diff --git a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_10_09/Circuit Description/schematic_switched_cap.PNG b/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_10_09/Circuit Description/schematic_switched_cap.PNG deleted file mode 100644 index 09ee40bd78..0000000000 Binary files a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_10_09/Circuit Description/schematic_switched_cap.PNG and /dev/null differ diff --git a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_10_09/Netlist/netlist b/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_10_09/Netlist/netlist deleted file mode 100644 index ae9d66c520..0000000000 --- a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_10_09/Netlist/netlist +++ /dev/null @@ -1,68 +0,0 @@ -** Generated for: hspiceD -** Generated on: Aug 30 07:11:40 2018 -** Design library name: pcell -** Design cell name: switched_capacitor_filter_tamu -** Design view name: schematic -.GLOBAL vdd! -.PARAM c1=5p c2=10p c3=10p ca=10p idc=20u vbiasn=0.55 vbiasp1=0.7 vbiasp2=0.4 -+ vcm=0.4 vdd=1 _gpar0=1 vnac=-0.5 vpac=0.5 - - -.TEMP 25.0 -.OPTION -+ ARTIST=2 -+ INGOLD=2 -+ PARHIER=LOCAL -+ PSF=2 - -** Library name: pcell -** Cell name: cascode_current_mirror_ota -** View name: schematic -.subckt cascode_current_mirror_ota vbiasn vbiasp1 vbiasp2 vinn vinp voutn voutp -m10 voutn vbiasn net10 0 nmos_rvt w=135e-9 l=20e-9 nfin=5 -m4 net1 net1 0 0 nmos_rvt w=270e-9 l=20e-9 nfin=10 -m3 net6 net1 0 0 nmos_rvt w=270e-9 l=20e-9 nfin=10 -m2 voutp vbiasn net11 0 nmos_rvt w=135e-9 l=20e-9 nfin=5 -m1 net10 vinp net6 0 nmos_rvt w=270e-9 l=20e-9 nfin=10 -m0 net11 vinn net6 0 nmos_rvt w=270e-9 l=20e-9 nfin=10 -m9 net13 vbiasp2 vdd! vdd! pmos_rvt w=81e-9 l=20e-9 nfin=3 -m8 net12 vbiasp2 vdd! vdd! pmos_rvt w=81e-9 l=20e-9 nfin=3 -m7 voutn vbiasp1 net13 net13 pmos_rvt w=135e-9 l=20e-9 nfin=5 -m6 voutp vbiasp1 net12 net12 pmos_rvt w=135e-9 l=20e-9 nfin=5 -i3 vdd! net1 DC=idc -.ends cascode_current_mirror_ota -** End of subcircuit definition. - -** Library name: pcell -** Cell name: switched_capacitor_filter_tamu -** View name: schematic -v5 vdd! 0 DC=vdd -v4 vinp 0 DC=vcm AC vpac -v3 vinn 0 DC=vcm AC vnac -v2 vbiasp2 0 DC=vbiasp2 -v1 vbiasp1 0 DC=vbiasp1 -v0 vbiasn 0 DC=vbiasn -xi0 vbiasn vbiasp1 vbiasp2 net23 net7 voutn voutp cascode_current_mirror_ota -c7 net7 vinp c1 -c6 net5 net4 c2 -c5 net23 vinn c1 -c4 net6 net3 c2 -c3 net6 net12 c3 -c2 net7 voutn ca -c1 net5 net11 c3 -c0 net23 voutp ca -m11 0 phi1 net12 0 nmos_rvt w=81e-9 l=20e-9 nfin=3 -m10 0 phi2 net3 0 nmos_rvt w=81e-9 l=20e-9 nfin=3 -m9 0 phi2 net6 0 nmos_rvt w=81e-9 l=20e-9 nfin=3 -m8 net12 phi2 voutp 0 nmos_rvt w=81e-9 l=20e-9 nfin=3 -m7 voutn phi2 net11 0 nmos_rvt w=81e-9 l=20e-9 nfin=3 -m6 net11 phi1 0 0 nmos_rvt w=81e-9 l=20e-9 nfin=3 -m5 net5 phi2 0 0 nmos_rvt w=81e-9 l=20e-9 nfin=3 -m4 net4 phi2 0 0 nmos_rvt w=81e-9 l=20e-9 nfin=3 -m3 net7 phi1 net5 0 nmos_rvt w=81e-9 l=20e-9 nfin=3 -m2 net4 phi1 vinn 0 nmos_rvt w=81e-9 l=20e-9 nfin=3 -m1 net6 phi1 net23 0 nmos_rvt w=81e-9 l=20e-9 nfin=3 -m0 vinp phi1 net3 0 nmos_rvt w=81e-9 l=20e-9 nfin=3 -v7 phi2 0 PULSE _gpar0 0 0 20e-9 -v6 phi1 0 PULSE 0 _gpar0 0 20e-9 -.END diff --git a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_10_09/Telescopic OTA/layout.jpg b/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_10_09/Telescopic OTA/layout.jpg deleted file mode 100644 index fa75137ccf..0000000000 Binary files a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_10_09/Telescopic OTA/layout.jpg and /dev/null differ diff --git a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_10_09/Telescopic OTA/ota.blocks b/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_10_09/Telescopic OTA/ota.blocks deleted file mode 100644 index a449b46cd5..0000000000 --- a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_10_09/Telescopic OTA/ota.blocks +++ /dev/null @@ -1,69 +0,0 @@ -#UMN blocks 1.0 -# Created : August 31 19:15:43 -# User : madhu028@umn.edu -# Platform : Linux - -NumSoftRectangularBlocks : 0 -NumHardRectilinearBlocks : 5 -NumTerminals : 10 - -L1_MM4_MM3 hardrectilinear 4 (0, 0) (0, 782) (648, 782) (648, 0) -L1_MM1_MM0 hardrectilinear 4 (0, 0) (0, 842) (648, 842) (648, 0) -L1_MM10_MM2 hardrectilinear 4 (0, 0) (0, 572) (648, 572) (648,0) -L1_MM7_MM6 hardrectilinear 4 (0, 0) (0, 572) (648, 572) (648, 0) -L1_MM9_MM8 hardrectilinear 4 (0, 0) (0, 464) (648, 464) (648, 0) - -BLOCK L1_MM10_MM2 : 6 -G1 M1 (108, 414) (108, 572) (148, 572) (148, 414) -S1 M1 (198, 342) (198, 564) (234, 564) (234, 342) -D1 M1 (88, 4) (88, 146) (128, 146) (128, 4) -S2 M1 (416, 340) (416, 566) (452, 566) (452, 340) -G2 M1 (504, 414) (504, 566) (544, 566) (544, 414) -D2 M1 (520, 0) (520, 143) (560, 143) (560, 0) - -BLOCK L1_MM7_MM6 : 6 -G1 M1 (108, 414) (108, 572) (148, 572) (148, 414) -S1 M1 (198, 342) (198, 564) (234, 564) (234, 342) -D1 M1 (88, 4) (88, 146) (128, 146) (128, 4) -S2 M1 (416, 340) (416, 566) (452, 566) (452, 340) -G2 M1 (504, 414) (504, 566) (544, 566) (544, 414) -D2 M1 (520, 0) (520, 143) (560, 143) (560, 0) - -BLOCK L1_MM1_MM0 : 5 -G1 M1 (108, 684) (108, 842) (148, 842) (148, 684) -S M1 (198, 802) (198, 838) (452, 838) (452, 802) -D1 M1 (88, 4) (88, 146) (128, 146) (128, 4) -G2 M1 (504, 684) (504, 836) (544, 836) (544, 684) -D2 M1 (520, 0) (520, 146) (560, 146) (560, 0) -INT M1 (198, 612) (198, 830) (234, 830) (234, 612) -INT M1 (416, 612) (416, 830) (452, 830) (452, 612) - -BLOCK L1_MM4_MM3 : 3 -D1 M1 (88, 615) (88, 757) (128, 757) (128, 615) -S M1 (198, 746) (196, 782) (452, 782) (452, 746) -D2 M1 (520, 615) (520, 761) (560, 761) (560, 615) -INT M1 (110, 39) (110, 75) (471, 75) (471, 39) -INT M1 (89, 39) (89, 148) (146, 148) (146, 39) -INT M1 (198, 615) (198, 782) (234, 782) (234, 615) -INT M1 (416, 615) (415, 782) (452, 782) (451, 615) - -BLOCK L1_MM9_MM8 : 6 -G1 M1 (108, 306) (108, 464) (148, 464) (148, 306) -S1 M1 (198, 234) (198, 458) (234, 458) (234, 234) -D1 M1 (88, 4) (88, 146) (128, 146) (128, 4) -S2 M1 (416, 234) (416, 458) (452, 458) (452, 234) -G2 M1 (504, 306) (504, 458) (544, 458) (544, 306) -D2 M1 (520, 0) (520, 143) (560, 143) (560, 0) - - -gnd! M1 terminal -vdd! M1 terminal -Vinp M1 terminal -Vinn M1 terminal -Vbiasn M1 terminal -Vbiasp1 M1 terminal -Vbiasp2 M1 terminal -Voutp M1 terminal -Voutn M1 terminal -Id M1 terminal - diff --git a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_10_09/Telescopic OTA/ota.const b/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_10_09/Telescopic OTA/ota.const deleted file mode 100644 index 81e011b4b7..0000000000 --- a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_10_09/Telescopic OTA/ota.const +++ /dev/null @@ -1,8 +0,0 @@ -SymmNet( {Vinp,L1_MM1_MM0/G1,Vinp} , {Vinn,L1_MM1_MM0/G2,Vinn}) -SymmNet( {net10,L1_MM1_MM0/D1,L1_MM10_MM2/S1} , {net11,L1_MM1_MM0/D2,L1_MM10_MM2/S2}) -SymmNet( {Voutn,L1_MM10_MM2/D1,L1_MM7_MM6/D1,Voutn} , {Voutp,L1_MM10_MM2/D2,L1_MM7_MM6/D2,Voutp}) -SymmNet( {net13,L1_MM7_MM6/S1,L1_MM9_MM8/D1}, {net12,L1_MM7_MM6/S2,L1_MM9_MM8/D2}) -CritNet(net6, mid) -CritNet(Vbiasn, mid) -CritNet(Vbiasp1, mid) -CritNet(Vbiasp2, mid) diff --git a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_10_09/Telescopic OTA/ota.nets b/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_10_09/Telescopic OTA/ota.nets deleted file mode 100644 index 13faec5694..0000000000 --- a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_10_09/Telescopic OTA/ota.nets +++ /dev/null @@ -1,59 +0,0 @@ -#UMN blocks 1.0 -# Created : August 31 19:15:43 -# User : madhu028@umn.edu -# Platform : Linux - -NumNets : 15 -NumPins : 26 - -Vinp : 2 -L1_MM1_MM0 G1 -terminal Vinp -net13 : 2 -L1_MM7_MM6 S1 -L1_MM9_MM8 D1 -Voutp : 3 -L1_MM7_MM6 D2 -L1_MM10_MM2 D2 -terminal Voutp -Voutn : 3 -L1_MM7_MM6 D1 -L1_MM10_MM2 D1 -terminal Voutn -net10 : 2 -L1_MM10_MM2 S1 -L1_MM1_MM0 D1 -vdd! : 3 -terminal vdd! -L1_MM9_MM8 S1 -L1_MM9_MM8 S2 -Vbiasn : 3 -L1_MM10_MM2 G1 -L1_MM10_MM2 G2 -terminal Vbiasn -net11 : 2 -L1_MM10_MM2 S2 -L1_MM1_MM0 D2 -Vbiasp2 : 3 -L1_MM9_MM8 G1 -L1_MM9_MM8 G2 -terminal Vbiasp2 -Vbiasp1 : 3 -L1_MM7_MM6 G1 -L1_MM7_MM6 G2 -terminal Vbiasp1 -gnd! : 2 -L1_MM4_MM3 S -terminal gnd! -net12 : 2 -L1_MM7_MM6 S2 -L1_MM9_MM8 D2 -net6 : 2 -L1_MM1_MM0 S -L1_MM4_MM3 D2 -Vinn : 2 -L1_MM1_MM0 G2 -terminal Vinn -net1 : 2 -L1_MM4_MM3 D1 -terminal Id diff --git a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_10_09/Telescopic OTA/ota_modified_netlist b/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_10_09/Telescopic OTA/ota_modified_netlist deleted file mode 100644 index cc641fc9b8..0000000000 --- a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_10_09/Telescopic OTA/ota_modified_netlist +++ /dev/null @@ -1,33 +0,0 @@ -//SUB MODULE DEFINATIONS -//Block_type -instance_name -external_nets -internal_nets -size -Level_1 -SCM_NMOS -L1_MM4_MM3 (net1,net6,gnd!) -((net1,net1,gnd!,gnd!),(net6,net1,gnd!,gnd!)) -10 -DP_NMOS - -L1_MM1_MM0 (net10,net11,Vinp,Vinn,net6) -((net10,Vinp,net6,gnd!),(net11,Vinn,net6,gnd!)) -10 -CMC_NMOS -L1_MM10_MM2 (Voutn,Voutp,Vbiasn,Vbiasn,net10,net11) -((Voutn,Vbiasn,net10,gnd!),(Voutp,Vbiasn,net11,gnd!)) -5 -CMC_PMOS -L1_MM7_MM6 (Voutn,Voutp,Vbiasp1,Vbiasp1,net13,net12) -((Voutn,Vbiasn,net10,gnd!),(Voutp,Vbiasn,net11,gnd!)) -5 -CMC_PMOS -L1_MM9_MM8 (net13,net12,Vbiasp2,Vbiasp2,vdd!,vdd!) -((net13,Vbiasp2,vdd!,vdd!),(net12,Vbiasp2,vdd!,vdd!)) -3 - - - - - diff --git a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_10_09/Telescopic OTA/schematic_ota.PNG b/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_10_09/Telescopic OTA/schematic_ota.PNG deleted file mode 100644 index af2f83ddb3..0000000000 Binary files a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_10_09/Telescopic OTA/schematic_ota.PNG and /dev/null differ diff --git a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_11_01/Circuit Description/Switched_capacitor_filter1.pdf b/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_11_01/Circuit Description/Switched_capacitor_filter1.pdf deleted file mode 100644 index 5f7d00cdab..0000000000 Binary files a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_11_01/Circuit Description/Switched_capacitor_filter1.pdf and /dev/null differ diff --git a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_11_01/Circuit Description/Switched_capacitor_filter_ota.pdf b/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_11_01/Circuit Description/Switched_capacitor_filter_ota.pdf deleted file mode 100644 index e1151dbcae..0000000000 Binary files a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_11_01/Circuit Description/Switched_capacitor_filter_ota.pdf and /dev/null differ diff --git a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_11_01/Constraints/switched_capacitor_filter.const b/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_11_01/Constraints/switched_capacitor_filter.const deleted file mode 100644 index afb588d3c9..0000000000 --- a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_11_01/Constraints/switched_capacitor_filter.const +++ /dev/null @@ -1,22 +0,0 @@ -CritNet(net7, min) -CritNet(net23, min) -SymmNet({Voutn,L1_CC0_CC2/CN2,L0_MM7/D,I0/Voutn},{Voutp,L1_CC0_CC2/CN1,L0_MM8/S,I0/Voutp}) -SymmNet({net7,L1_CC5_CC7/CP2,L1_CC0_CC2/CP2,I0/Vinp,L0_MM3/D},{net23,L1_CC5_CC7/CP1,L1_CC0_CC2/CP1,I0/Vinn,L0_MM1/S}) -SymmNet({net11,L0_MM6/D,L0_MM7/S,L1_CC1_CC3/CN1},{net12,L0_MM11/S,L0_MM8/D,L1_CC1_CC3/CN2}) -SymmNet({net5,L1_CC4_CC6/CP2,L1_CC1_CC3/CP1,L0_MM5/D,L0_MM3/S},{net6,L1_CC4_CC6/CP1,L1_CC1_CC3/CP2,L0_MM9/S,L0_MM1/D}) -SymmNet({net4,L1_CC4_CC6/CN2,L0_MM2/D,L0_MM4/D},{net3,L1_CC4_CC6/CN1,L0_MM0/S,L0_MM10/S}) -SymmNet({Vinn,L1_CC5_CC7/CN1,L0_MM2/S},{Vinp,L1_CC5_CC7/CN2,L0_MM0/D}) -ShieldNet(Vinn) -ShieldNet(Vinp) -ShieldNet(net3) -ShieldNet(net4) -ShieldNet(net5) -ShieldNet(net6) -ShieldNet(net7) -ShieldNet(net23) -MatchBlock(L0_MM0,L0_MM2) -MatchBlock(L0_MM10,L0_MM4) -MatchBlock(L0_MM9,L0_MM5) -MatchBlock(L0_MM3,L0_MM1) -MatchBlock(L0_MM6,L0_MM11) -MatchBlock(L0_MM7,L0_MM8) diff --git a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_11_01/Constraints/telescopic_ota.const b/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_11_01/Constraints/telescopic_ota.const deleted file mode 100644 index ec6dda3f30..0000000000 --- a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_11_01/Constraints/telescopic_ota.const +++ /dev/null @@ -1,15 +0,0 @@ -SymmNet( {Vinp,L1_MM1_MM0/G1,Vinp} , {Vinn,L1_MM1_MM0/G2,Vinn}) -SymmNet( {net10,L1_MM1_MM0/D1,L1_MM10_MM2/S1} , {net11,L1_MM1_MM0/D2,L1_MM10_MM2/S2}) -SymmNet( {Voutn,L1_MM10_MM2/D1,L1_MM7_MM6/D1,Voutn} , {Voutp,L1_MM10_MM2/D2,L1_MM7_MM6/D2,Voutp}) -SymmNet( {net13,L1_MM7_MM6/S1,L1_MM8_MM9/D1}, {net12,L1_MM7_MM6/S2,L1_MM8_MM9/D2}) -CritNet(net6, mid) -CritNet(Vbiasn, mid) -CritNet(Vbiasp1, mid) -CritNet(Vbiasp2, mid) -CritNet(net10, min) -CritNet(net11, min) -CritNet(Voutn, min) -CritNet(Voutp, min) -CritNet(net13, min) -CritNet(net12, min) - diff --git a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_11_01/LEF/sc.lef b/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_11_01/LEF/sc.lef deleted file mode 100644 index 68ece8c50b..0000000000 --- a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_11_01/LEF/sc.lef +++ /dev/null @@ -1,597 +0,0 @@ -VERSION 5.7 ; -BUSBITCHARS "[]" ; -DIVIDERCHAR "/" ; - -MACRO CMC_NMOS_X40 - ORIGIN 0 0 ; - FOREIGN CMC_NMOS_X40 0 0 ; - SIZE 0.324 BY 1.188 ; - PIN D1 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M1 ; - RECT 0.045 0 0.063 1.089 ; - END - END D1 - PIN S1 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M1 ; - RECT 0.099 0.027 0.117 1.107 ; - END - END S1 - PIN S2 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M1 ; - RECT 0.207 0.027 0.225 1.107 ; - END - END S2 - PIN D2 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M1 ; - RECT 0.261 0 0.279 1.089 ; - END - END D2 - PIN G - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M1 ; - RECT 0.063 1.137 0.261 1.155 ; - END - END G -END CMC_NMOS_X40 - -MACRO CMC_PMOS_X40 - ORIGIN 0 0 ; - FOREIGN CMC_PMOS_X40 0 0 ; - SIZE 0.324 BY 1.188 ; - PIN D1 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M1 ; - RECT 0.045 0.027 0.063 1.089 ; - END - END D1 - PIN S1 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M1 ; - RECT 0.099 0.045 0.117 1.107 ; - END - END S1 - PIN G - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M1 ; - RECT 0.063 1.137 0.261 1.155 ; - END - END G - PIN D2 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M1 ; - RECT 0.261 0.027 0.279 1.089 ; - END - END D2 - PIN S2 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M1 ; - RECT 0.207 1.089 0.225 1.107 ; - END - END S2 -END CMC_PMOS_X40 - -MACRO CMC_PMOS_X70 - ORIGIN 0 0 ; - FOREIGN CMC_PMOS_X70 0 0 ; - SIZE 0.324 BY 1.998 ; - PIN G - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M1 ; - RECT 0.063 1.947 0.261 1.965 ; - END - END G - PIN S1 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M1 ; - RECT 0.099 0.027 0.117 1.917 ; - END - END S1 - PIN D1 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M1 ; - RECT 0.045 0.027 0.063 1.917 ; - END - END D1 - PIN D2 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M1 ; - RECT 0.261 0.027 0.279 1.917 ; - END - END D2 - PIN S2 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M1 ; - RECT 0.207 0.027 0.225 1.917 ; - END - END S2 -END CMC_PMOS_X70 - -MACRO DP_NMOS_X50 - ORIGIN 0 0 ; - FOREIGN DP_NMOS_X50 0 0 ; - SIZE 0.324 BY 1.476 ; - PIN D2 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M1 ; - RECT 0.261 0.029 0.279 1.37 ; - END - END D2 - PIN S - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M1 ; - RECT 0.099 0.182 0.225 0.2 ; - END - PORT - LAYER M1 ; - RECT 0.099 0.146 0.225 0.164 ; - END - PORT - LAYER M1 ; - RECT 0.099 0.11 0.225 0.128 ; - END - PORT - LAYER M1 ; - RECT 0.099 0.074 0.225 0.092 ; - END - PORT - LAYER M1 ; - RECT 0.099 0.038 0.225 0.056 ; - END - PORT - LAYER M1 ; - RECT 0.099 0.254 0.225 0.272 ; - END - PORT - LAYER M1 ; - RECT 0.099 0.218 0.225 0.236 ; - END - PORT - LAYER M1 ; - RECT 0.099 0.29 0.225 0.308 ; - END - PORT - LAYER M1 ; - RECT 0.099 0.326 0.225 0.344 ; - END - PORT - LAYER M1 ; - RECT 0.099 0.362 0.225 0.38 ; - END - PORT - LAYER M1 ; - RECT 0.099 0.398 0.225 0.416 ; - END - PORT - LAYER M1 ; - RECT 0.099 0.434 0.225 0.452 ; - END - PORT - LAYER M1 ; - RECT 0.099 0.47 0.225 0.488 ; - END - PORT - LAYER M1 ; - RECT 0.099 0.506 0.225 0.524 ; - END - PORT - LAYER M1 ; - RECT 0.099 0.542 0.225 0.56 ; - END - PORT - LAYER M1 ; - RECT 0.099 0.578 0.225 0.596 ; - END - PORT - LAYER M1 ; - RECT 0.099 0.65 0.225 0.668 ; - END - PORT - LAYER M1 ; - RECT 0.099 0.614 0.225 0.632 ; - END - PORT - LAYER M1 ; - RECT 0.099 0.722 0.225 0.74 ; - END - PORT - LAYER M1 ; - RECT 0.099 0.686 0.225 0.704 ; - END - PORT - LAYER M1 ; - RECT 0.099 0.794 0.225 0.812 ; - END - PORT - LAYER M1 ; - RECT 0.099 0.866 0.225 0.884 ; - END - PORT - LAYER M1 ; - RECT 0.099 0.938 0.225 0.956 ; - END - PORT - LAYER M1 ; - RECT 0.099 0.974 0.225 0.992 ; - END - PORT - LAYER M1 ; - RECT 0.099 1.01 0.225 1.028 ; - END - PORT - LAYER M1 ; - RECT 0.099 1.046 0.225 1.064 ; - END - PORT - LAYER M1 ; - RECT 0.099 1.082 0.225 1.1 ; - END - PORT - LAYER M1 ; - RECT 0.099 1.118 0.225 1.136 ; - END - PORT - LAYER M1 ; - RECT 0.099 1.154 0.225 1.172 ; - END - PORT - LAYER M1 ; - RECT 0.099 1.19 0.225 1.208 ; - END - PORT - LAYER M1 ; - RECT 0.099 1.226 0.225 1.244 ; - END - PORT - LAYER M1 ; - RECT 0.099 1.262 0.225 1.28 ; - END - PORT - LAYER M1 ; - RECT 0.207 0.029 0.225 1.406 ; - END - PORT - LAYER M1 ; - RECT 0.099 1.298 0.225 1.316 ; - END - PORT - LAYER M1 ; - RECT 0.099 1.37 0.225 1.388 ; - END - PORT - LAYER M1 ; - RECT 0.099 0.029 0.117 1.406 ; - END - END S - PIN D1 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M1 ; - RECT 0.045 0.029 0.063 1.37 ; - END - END D1 - PIN G1 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M1 ; - RECT 0.063 1.436 0.081 1.476 ; - END - END G1 - PIN G2 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M1 ; - RECT 0.243 1.436 0.261 1.476 ; - END - END G2 -END DP_NMOS_X50 - -MACRO SCM_NMOS_X50 - ORIGIN 0 0 ; - FOREIGN SCM_NMOS_X50 0 0 ; - SIZE 0.324 BY 1.476 ; - PIN D1 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M1 ; - RECT 0.045 1.436 0.063 1.454 ; - END - END D1 - PIN S - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M1 ; - RECT 0.099 0.182 0.225 0.2 ; - END - PORT - LAYER M1 ; - RECT 0.099 0.146 0.225 0.164 ; - END - PORT - LAYER M1 ; - RECT 0.099 0.11 0.225 0.128 ; - END - PORT - LAYER M1 ; - RECT 0.099 0.074 0.225 0.092 ; - END - PORT - LAYER M1 ; - RECT 0.099 0.038 0.225 0.056 ; - END - PORT - LAYER M1 ; - RECT 0.099 0.254 0.225 0.272 ; - END - PORT - LAYER M1 ; - RECT 0.099 0.218 0.225 0.236 ; - END - PORT - LAYER M1 ; - RECT 0.099 0.29 0.225 0.308 ; - END - PORT - LAYER M1 ; - RECT 0.099 0.326 0.225 0.344 ; - END - PORT - LAYER M1 ; - RECT 0.099 0.362 0.225 0.38 ; - END - PORT - LAYER M1 ; - RECT 0.099 0.398 0.225 0.416 ; - END - PORT - LAYER M1 ; - RECT 0.099 0.434 0.225 0.452 ; - END - PORT - LAYER M1 ; - RECT 0.099 0.47 0.225 0.488 ; - END - PORT - LAYER M1 ; - RECT 0.099 0.506 0.225 0.524 ; - END - PORT - LAYER M1 ; - RECT 0.099 0.542 0.225 0.56 ; - END - PORT - LAYER M1 ; - RECT 0.099 0.578 0.225 0.596 ; - END - PORT - LAYER M1 ; - RECT 0.099 0.65 0.225 0.668 ; - END - PORT - LAYER M1 ; - RECT 0.099 0.614 0.225 0.632 ; - END - PORT - LAYER M1 ; - RECT 0.099 0.722 0.225 0.74 ; - END - PORT - LAYER M1 ; - RECT 0.099 0.686 0.225 0.704 ; - END - PORT - LAYER M1 ; - RECT 0.099 0.794 0.225 0.812 ; - END - PORT - LAYER M1 ; - RECT 0.099 0.866 0.225 0.884 ; - END - PORT - LAYER M1 ; - RECT 0.099 0.938 0.225 0.956 ; - END - PORT - LAYER M1 ; - RECT 0.099 0.974 0.225 0.992 ; - END - PORT - LAYER M1 ; - RECT 0.099 1.01 0.225 1.028 ; - END - PORT - LAYER M1 ; - RECT 0.099 1.046 0.225 1.064 ; - END - PORT - LAYER M1 ; - RECT 0.099 1.082 0.225 1.1 ; - END - PORT - LAYER M1 ; - RECT 0.099 1.118 0.225 1.136 ; - END - PORT - LAYER M1 ; - RECT 0.099 1.154 0.225 1.172 ; - END - PORT - LAYER M1 ; - RECT 0.099 1.19 0.225 1.208 ; - END - PORT - LAYER M1 ; - RECT 0.099 1.226 0.225 1.244 ; - END - PORT - LAYER M1 ; - RECT 0.099 1.262 0.225 1.28 ; - END - PORT - LAYER M1 ; - RECT 0.207 1.388 0.225 1.406 ; - END - PORT - LAYER M1 ; - RECT 0.099 1.298 0.225 1.316 ; - END - PORT - LAYER M1 ; - RECT 0.099 1.37 0.225 1.388 ; - END - PORT - LAYER M1 ; - RECT 0.099 1.388 0.117 1.406 ; - END - END S - PIN D2 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M1 ; - RECT 0.261 1.388 0.279 1.406 ; - END - END D2 -END SCM_NMOS_X50 - -MACRO matching_cap_X1 - ORIGIN 0 0 ; - FOREIGN matching_cap_X1 0 0 ; - SIZE 0.324 BY 0.4 ; - PIN CN1 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M1 ; - RECT 0.054 0.038 0.072 0.338 ; - END - END CN1 - PIN CN2 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M1 ; - RECT 0.108 0.038 0.126 0.338 ; - END - END CN2 - PIN CP1 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M1 ; - RECT 0.2 0.038 0.218 0.338 ; - END - END CP1 - PIN CP2 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M1 ; - RECT 0.261 0.038 0.279 0.338 ; - END - END CP2 -END matching_cap_X1 - -MACRO nmos_rvt - ORIGIN 0 0 ; - FOREIGN nmos_rvt 0 0 ; - SIZE 0.162 BY 0.351 ; - PIN D - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M1 ; - RECT 0.045 0 0.063 0.261 ; - END - END D - PIN S - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M1 ; - RECT 0.099 0 0.117 0.261 ; - END - END S - PIN G - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M1 ; - RECT 0.063 0.307 0.081 0.351 ; - END - END G -END nmos_rvt - -MACRO pmos_rvt - ORIGIN 0 0 ; - FOREIGN pmos_rvt 0 0 ; - SIZE 0.162 BY 0.351 ; - PIN D - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M1 ; - RECT 0.045 0 0.063 0.261 ; - END - END D - PIN S - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M1 ; - RECT 0.099 0 0.117 0.261 ; - END - END S - PIN G - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M1 ; - RECT 0.063 0.307 0.081 0.351 ; - END - END G -END pmos_rvt - -END LIBRARY diff --git a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_11_01/README.md b/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_11_01/README.md deleted file mode 100644 index efe95f8ba8..0000000000 --- a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_11_01/README.md +++ /dev/null @@ -1,22 +0,0 @@ -# INPUT for PnR tool -sc_block.v : block level netlist for switched capacitor -   This netlist contains two modules which need to be placed and routed hierarchicaly. -      1.switched_capacitor_filter : top level module , corresponding constraint are there in switched_capacitor_filter.const -      2.cascode_current_mirror_ota : sub module , corresponding constraint are there in cascode_current_mirror_ota.const - -sc.lef : lef file with block dimensions and pin locations - -sc_transistor.v : transistor level netlist (not required for PnR/ redundant) - -# BLOCKS used (defined in lef, used in netlist) -1.CMC_NMOS_X40 : common centroid transistors with gate connection -2.CMC_PMOS_X40 : common centroid transistors with gate connection -3.CMC_PMOS_X70 : common centroid transistors with gate connection -4.DP_NMOS_X50 : Differential pair -5.SCM_NMOS_X50 : current mirror -6.matching_cap_X1: capacitance -7.nmos_rvt : transistor building block with 10 fins -8.pmos_rvt : transistor building block with 10 fins - -X50 : denotes number of fins in parallel - diff --git a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_11_01/Verilog Netlist/__Previews/sc_block.vPreview b/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_11_01/Verilog Netlist/__Previews/sc_block.vPreview deleted file mode 100644 index ff87a46a49..0000000000 --- a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_11_01/Verilog Netlist/__Previews/sc_block.vPreview +++ /dev/null @@ -1,14 +0,0 @@ -[Preview] -LargeImageOriginalSize=2832000 -LargeImageWidth=708 -LargeImageHeight=1000 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283C5F2D43D38F056BAF8C9C6ECB9BCEF7E53295ED695B9BAEB6DB995C917FDFC37A7054B2B6E5D276275917455F9812FE13B8DF9F8A1F20FB736C64D39ECFB16897DCED26FD3448DBA9F79B35A41DA2666C7627DBC9B2ABD5C634EA8BCDCDD6883FB6237C5B37606BE2CF07D6FF7B732F2AF1B8F3188F1B63EC1C54C5C091F1E9F09C95CC7BC82477AACEA9959E57BC66A7E3DCFC0F8B98E44FCC18F0D3DA8B9AF321B0DD084D6E98F71D9AF8CD31CFF23EE5DF0F1EED71DF6F79D6A72FCD37EE7F58F8FE43FFAAC78BD75CC99F353E9DD56E561FB8C942C9F41BDC683AEAF56AA5333235C7EA509ED58522241FCCD45DF71A8DC7E116175DFAD1459D706F3159B7FF61B73C7C39F60B7CDEF788FB8755EBCFE2B46ED6B96FEEED98EF70186B018FC5F42767F72CFE6930BE4B6E49175A88FB2C7C5555CF9C7C3CBAC5401889241BEE4BD1B76B0700946CE5EB66B7E9A53464132B663F885AA5DEB243DB613C4B2FBBA5562AF14A650CA59CCD8FB9B41BFA18C77DD26EF83C5DEF5B3675E3BDC53D4BEC75371FFF38B6CE2A50C3EF1258E7ECB65B5CCF98F104F19E7C37ABD3738A1181F1C6ECF50AEFA7F7FC7DA6CBDEF26B69D3DB55B1E4EDF5036D5358DF1231D471BCC0B766B99E36F898BF3F705F88DA9619AFD96EB7F5C5179EE9D4AA8BC7B1A9FD39BEEA637A2D57F67F9D33405F98B7E5ADB1781CAA5F6BB50D78F0280185B206C6B865894C8EB75DC2AE06AB73C1F2B3AAD78CAB83FE6CF5F81A8F2192617AF09E6FA4EAB944DB1D95ACFE485B5917455F38C8F320FAC279FEDCF27824F2392E3F87763DECF41CBBD90DCF5FF92E686A5DB45D4AAFE4E3FA0D8DEB63F4C79D8A57FB13B7979D3D6FF636A699581D4EB616362AC185CE0EC7F8EE0421A9159F0E752AC61231B205B3FF6E557C3AA774E2CB9897C3BAE2D3A904A2BF57696A2796321FD87BA20EBE7BAF2C7DCE043B3F30FE848F8DF40FFF02ABA127956B2BF72A637ED74A476D473046C5B701ECAF8EA78771DC196398DAF530EF139771ACA554A55371DFC4CDB186D3B15FCF2B1D8CC7B1ECBF6CFE3DB73057577AF6D8F0C7A1D9F8744E79D829C72B35D83B901A97C5FEACA8DA417DA7B36B0AFBFB95D376271D72DAF19AED765B4C64E19E433C64AFB293B6C378963206A793DD543FF26A7C50CB7617BBA1AE5B0B3CB3FCBD19ADC4CC398D18B0F6F8744E3AEDB3D1B0258630722BB86BD62B691FFBFD60FE37A3D6F76E7BFD40FDF0B5EF196BAF9EF31867619FB3BF4E1EFB29B463EA61BBDD22DFA07D0F5CD339CDBA68CF77D8F795CD06EE7AD8C9D66EBAAEFFF31B55DFD8A4EEF58A0D63BF8E1377C2ACBFDA7F59653BFB38C389D64DF66EA0A687CF717669DAF158A7E7D8CD6EBCBFF10F5BECA6C693F48A47C46DE350765E796BE639F6B2358E75E7D3ED8D7B439C6DBC62A8C83EFEFA588A8FF7C8FEE938F1437AAE3EE59A7326F21CD2ABAFAAD2F9EBE59FF8D809EA61A7F96E6A7E31C61D7E130CB16B2DCD55C7E276E3927F177662D6B82EFC5B8BB6C163D1ABFDB071648DB5D3AE78CDF88C5F1FD358395CAFD2C331DD6076FB2B8F3FE7D4268DF9634CD3EC34948EFD7A5EE9E098CAA58B9D50CC67583F5D82E4CA83BAEECB1E1BFE38A8BA4EE6B71E5B3BE541D572377D95986238B627E3ED2291F298B05A87457AF5EBE15C5C773C07396D3D6CB71BAFFF385FD94113BB959DB45DB27008C948CAD56E724C58A4D9B81E8E8C3C36FFC6B40AC95796BC9DA4DD44FC2D6127756E947D2CF10BEC9B158D6628712FB15E49FBF0EF4743150D26ECB565B956AD1851AA0D9199C55D3ECF241ADD86FF5C7FED6AB7EFBFDFA92B9DD3D2C37A26070166CBD0F4147FF7B7E6CD5D0FDB6D2DEA4F813D5F41F35CD90604EF4E59CA2414499A73678FA387F1DBD8FCD7138EB63B693D8C63B5D1688CDD4B80F5851813C93A463DCB7467DA41773A3DC76E76C36F4C6A8C53B45D2C58797F6E460F5BF2E6D0C6B4520FE35AF26CC23B462BF1E7A6D6F8707CE315E80B29DECF05BE7FD1D2F16131D6FAC1928EB1FF81F719F58C0F5F63FA59C6B0AB9754FE0096E653E01B4955CDAFD082AFB92656FB611CA758FEE6B74A9EDBA487E31B8F987D34560E49560EDF5BF4F0982FC8EC66305BDD746C9350AFBE59639AA6567C3A251DFBF5BCD2C176EBBF7E8C363C7FB899F9126E343B3EEC9407DFCDCA185A4CFF60D1262B8FF6D87D6EF13139FD3F441DC1399EFD834FB91EC6F83A6A3C1F9C8F8EDF1BE4B7075CDB8F7516D3ED1FDE823BB77F86704007DF950D73EE85C4ED1B752BF1B29B04FBBDA0CFFA8DC1ADEC54DB4D613CF5F23BAADD6EF2B9E5F363CBDFFA715EAB8CB764B79B1AAF12632D5D1F7CCCDA8F677C1EECCABCF55DB899EFAC8D621F1F76C2FE0D1FE7D4C8F702AC57D23EA85303833F41684A874880DDCFF433F37E64AC4EA718513FAEBFE59A570B59E3C921A179A687035B3013D9861B7F79E46A3723FBBBE5BC46E74BB412D45B7C8E67C9B9FD6864BE04CE1FEE1F9E61CFD7FF627608B2E7EBBAA9B756D9BEA0CFC7DF61429A06E9D507E53A67B073FCACCE0D568D7DAA79706A4B506B4DFA034C6F2D3ADACEE91B7E2BB93636C59E0FEFF570DA820EC59C75CEB6FD3916ED92B3DD709FA6CDB3ED01D376E65A93681C7AFA7A5DDF0D11B7B29379B3B731AD9C2F81748F442078A9F344CB81F8B831F87C23A62B795F7C0879650E1FEAD49B9F2D72DD88E3A79D9D0FB94EC473E697DE424EDFAE3AA716520FE3D8EEE2F46FFC7C351DDCE7F3EF82FF867847779B3F8C4C627F826B93784C728C71E9AD53F9BD4EE0F907BC9FB93FFDB46ABFB65000FF3F74CBB854E81F153D3475B7F1F9C3CDEC57419D7AF3B31E3E274C94439FA987BBFFF295393F18D71FF86F54BF4F17F8B8D4CDAAB9A35EE9D8AF572B9DF9B9C5AAB524F5D06C6C783BAAAED3E657EB9E3F6CCF038E99E17B99DC877D807FEC78B123DDC639BDF05AC3D44ADCECA633CDA0AED999BA1BAC3AD75E7676DBF9636F2DF3644FC36E48A3EB709A617E09E70F8B38D1385FD277B53A8EB07D8DD7EDA9CAB786A2629F66FD3E9C044E7AF8B4EA22EAE17C52AC3DB8AFE7994D7CB6BCB9EB61A7B58BCDD5B963CE97B0E5CF6B8D572B99BC3DC5DB5FD1174E02CECDC33AA63EC7A82F0BC96A8DDFAA36B8D1F1617BDEEC6D4C2BD7D31144BD88B5DFBB628D777C177676C4FB15AE3756FD2F44F95AA0CA774FE9F7413DC70B75ADB4BACEDC9E8E1C1391E3414EFE252AF9166BD637E3F87DDB7B5EAF4C9FFBCB28FB91906BB2CD6BB2F6A4E3FC634B3F8CEB0523211D26B5E7ECF8BD9AF7A97E4375F2EB5B4FCC74157CF74E2BDF79705D2E8E5DC835D7F21D1DD713CB77739CB33CDCFFA5990FDFD59E9AE9D9D391D74B2593AEE9C863F9DA8DA979B63D02A906BE49B5C26797979F8446E3D3CB35F6E88344D679D5D74953F963F5A7D1EF18A7E13BC8CB6E58C653777C10086AE0D382904FAD7ADA8D3F4F8AEDE433ACFA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B71FFD8AB075BE0A5E662F1FB45A18747A5C7F79D3EFEED69ADC66D6E436B797AF7FCCD6C8CAD532D937F2FE56F9DBFB3EC0FAED5BFDDFBAED6FDEEFD5576BF7B7DD06010101010101010101010101811F26AA52014707FDC9717C9DD96D995DB95D50D1C8A4D1AA76B88F6A35A740B5EF43B2FBD1CCC6A050994626854A22836EA5042D91465BCD43B6BA91B7EEF3BA9A952632DB5B2847A9BCC78356A980BCDD8192CF8B5230828E564746AF47AB5CE3F671E64377DDFD2220F04D7191BD5C8DE490D85886FBAB7B083EBC8D66B585A27D9BDF93AC76D44B3594DD3427E239A43657115DDDA479A42038BF8CC4CA3CCD270F628BA3BDD198DDD0FCFB2F2059CC3447BDC87BED2838DD48ACAFC37DFB014A7E0724C728B637BCB489F209BF720181B70D2DADC1FD8CC64776ADDB6873DF55C693C6E57A9AC67D7C0A9E512CED495F866EF3BC2DBD143EFF4DE9B2FB956C417C2F141010101010101010101078AB518E5CAD03BD49B0B83EE687D73B63DFD35219EE2BFB3A75B1D8455697160D5F7B1F0AFC707099BD7C8CF8E60EB44804CD5299FB6CD7A591FD5CF644D04885B8FD9C1DC7E573FB766E3FCF3A7CA8467CDCAECEFCCF8BC12806AD06D46008B55C0E5A8C9E4F27B9BDBC59A872FB79471EC5140D0F8E5008FAD190F348ED59913698A03A9C6848792436B678EC3BF3776EAA0548463DB7E597031EA24D81968CA09255D152A6FBD0E6BDF40E29894A46E636FE31CDCCC6DF54A4898D3F6BB162D81AC5E7B29829E6EFCA6C96639A4B61AA3B1C83160EA2E08FA0E071206B76709AD87C67DF0E58AC71664FCF73C7B0361CFC013E76026F27F20EFBA923038BB1287A7C48EAAD486E188847C4B8CF766445C7EDE783E1118AAE519CECF8C820BB42883E7B0AE3875F233AFB005ABE8C835A1EA185679CEF64AD4EEEBB1D5B5E87E275C271E36B24B7F750703AA11876781DBDDE73A8FE00B7FF7967E721B93C90369FA1E4F6C0F4FB5BA8045DDCDFB95354115B5A42B5D4407CE1318F894F6CACF27C2C89A5195A1F4636C78A52437A791683761B259B69427354B7CEE302BD8FE6B88D3FBE6DE27EE4E3B6A4F4366476D727342736F710DB36C0F3D54D248C76383EFC35F5C71AA7E94093E09B79C2FDCC238B4BA8E78BBC0D8D4C92F7E375FFC7027F3C5C642F6770DFA33158BD38BE6FD01DA04CEB34B39FB3E355F50F6A657435EDD4B55AF6BC7FF8CBECEB17D27E6CB33F5BFF59284E2F863CCEB730A199D9F88F069D577ED745349FC49886B3319157F5A3C0F70B6F2A9F653593C3E03B9A1B4940E08F85CBE2737BFD23249716497E0B22B5B6CCE349595C2ED34158BC6EDA1186E6314F625D73263BB227F65E4F6EED20B3B3C5E5A16220C8635B4B81910FC4E0E005424BEBA892DCA6905E145FDD21FD691FD5C0486EEC34DA24CF79A185823C7EB44B3C93C58B766B0D1E9FCBF247B0B8D162288AD8B305686A1345DB2ECF41C49EAFE52B68C4BD135A99BE945CD321B96BE171B82C5E5736EB27B44AA4F3B136C4749B3C9FC475FF27026F372ECA679932FB500AF948AF58E2B2118B2765394EFACD3A8DFD511C2E8B916D9735BAEFA7312BD3B89CCE27F79D47F0DDF91A89AD2D648C7AAEAB30796B7CBF1C4FA2A5CA505C3E6E1328B843DCB6C0EEB198D69CD14CFCAE82BCD38D4EA50AFFC3879CB6497CAED1806EA38BB4DECC75FFC0F17D768FE5B3F0DFB9CBF5A593B4D68846E6EFD12C54A03AA7399AEA529EB7418D29A885451E75813F0CAF9BCF92C7EB92FEC472D6BD493A5AC5D24BCB8CE3735F16375A57543E7F5939A62F355EA2FB8C514D655EA99C8080808080808080808080808080C0ABE3FF03E027FF21 - diff --git a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_11_01/Verilog Netlist/debug.log b/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_11_01/Verilog Netlist/debug.log deleted file mode 100644 index e69de29bb2..0000000000 diff --git a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_11_01/Verilog Netlist/sc_block.v b/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_11_01/Verilog Netlist/sc_block.v deleted file mode 100644 index 7ae311515a..0000000000 --- a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_11_01/Verilog Netlist/sc_block.v +++ /dev/null @@ -1,99 +0,0 @@ -// Verilog HDL and netlist files of -// "pcell switched_capacitor_filter schematic" - -// Netlisted models - -// Library - pcell, Cell - cascode_current_mirror_ota, View - schematic -// LAST TIME SAVED: Aug 30 07:09:12 2018 -// NETLIST TIME: Nov 13 07:44:10 2018 -`timescale 1ns / 1ns - - -module telescopic_ota ( Voutn, Voutp, Vbiasn, Vbiasp1, - Vbiasp2, Vinn, Vinp ); - -output Voutn, Voutp; - -input Vbiasn, Vbiasp1, Vbiasp2, Vinn, Vinp; - - -specify - specparam CDS_LIBNAME = "pcell"; - specparam CDS_CELLNAME = "telescopic_ota"; - specparam CDS_VIEWNAME = "schematic"; -endspecify - -SCM_NMOS_X50 L1_MM4_MM3 ( .D1(net1), .D2(net6), .S(cds_globals.gnd_) ); -CMC_NMOS_X40 L1_MM10_MM2 ( .D1(Voutn), .D2(Voutp), .G(Vbiasn), .S1(net10), .S2(net11) ); -CMC_PMOS_X40 L1_MM7_MM6 ( .D1(Voutn), .D2(Voutp), .G(Vbiasp1), .S1(net13), .S2(net12) ); -CMC_PMOS_X70 L1_MM8_MM9 ( .D1(net13), .D2(net12), .G(Vbiasp2), .S1(cds_globals.vdd_), .S1(cds_globals.vdd_) ); -DP_NMOS_X50 L1_MM1_MM0 ( .D1(net10), .D2(net11), .G1(Vinp), .G2(Vinn), .S(net6) ) -//idc I3 ( .PLUS(cds_globals.vdd_), .MINUS(net1)); - -endmodule -// Library - pcell, Cell - switched_capacitor_filter, View - -//schematic -// LAST TIME SAVED: Aug 30 07:08:50 2018 -// NETLIST TIME: Nov 13 07:44:10 2018 -`timescale 1ns / 1ns - - -module switched_capacitor_filter ( Vinp, Vinn, Vbiasp2, Vbiasp1, Vbiasn, phi2, phi1 ); - - -specify - specparam CDS_LIBNAME = "pcell"; - specparam CDS_CELLNAME = "switched_capacitor_filter"; - specparam CDS_VIEWNAME = "schematic"; -endspecify - -//vdc V5 ( .PLUS(cds_globals.vdd_), .MINUS(cds_globals.gnd_)); -//vdc V4 ( .PLUS(Vinp), .MINUS(cds_globals.gnd_)); -//vdc V3 ( .PLUS(Vinn), .MINUS(cds_globals.gnd_)); -//vdc V2 ( .PLUS(Vbiasp2), .MINUS(cds_globals.gnd_)); -//vdc V1 ( .PLUS(Vbiasp1), .MINUS(cds_globals.gnd_)); -//vdc V0 ( .PLUS(Vbiasn), .MINUS(cds_globals.gnd_)); -telescopic_ota I0 ( Voutn, Voutp, Vbiasn, Vbiasp1, Vbiasp2, - net23, net7); -matching_cap_X1 L1_CC0_CC2 ( .CN1(Voutp), .CN2(Voutn), .CP1(net23), .CP2(net7)); -matching_cap_X1 L1_CC5_CC7 ( .CN1(Vinp), .CN2(Vinn), .CP1(net23), .CP2(net7)); -matching_cap_X1 L1_CC1_CC3 ( .CN1(net11), .CN2(net12), .CP1(net5), .CP2(net6)); -matching_cap_X1 L1_CC4_CC6 ( .CN1(net3), .CN2(net4), .CP1(net6), .CP2(net5)); -nmos_rvt L0_MM11 ( .B(cds_globals.gnd_), .S(net12), .G(phi1), - .D(cds_globals.gnd_)); -nmos_rvt L0_MM10 ( .B(cds_globals.gnd_), .S(net3), .G(phi2), - .D(cds_globals.gnd_)); -nmos_rvt L0_MM9 ( .B(cds_globals.gnd_), .S(net6), .G(phi2), - .D(cds_globals.gnd_)); -nmos_rvt L0_MM8 ( .B(cds_globals.gnd_), .S(Voutp), .G(phi2), .D(net12)); -nmos_rvt L0_MM7 ( .B(cds_globals.gnd_), .S(net11), .G(phi2), .D(Voutn)); -nmos_rvt L0_MM6 ( .B(cds_globals.gnd_), .S(cds_globals.gnd_), .G(phi1), - .D(net11)); -nmos_rvt L0_MM5 ( .B(cds_globals.gnd_), .S(cds_globals.gnd_), .G(phi2), - .D(net5)); -nmos_rvt L0_MM4 ( .B(cds_globals.gnd_), .S(cds_globals.gnd_), .G(phi2), - .D(net4)); -nmos_rvt L0_MM3 ( .B(cds_globals.gnd_), .S(net5), .G(phi1), .D(net7)); -nmos_rvt L0_MM2 ( .B(cds_globals.gnd_), .S(Vinn), .G(phi1), .D(net4)); -nmos_rvt L0_MM1 ( .B(cds_globals.gnd_), .S(net23), .G(phi1), .D(net6)); -nmos_rvt L0_MM0 ( .B(cds_globals.gnd_), .S(net3), .G(phi1), .D(Vinp)); -//vpulse V7 ( .PLUS(phi2), .MINUS(cds_globals.gnd_)); -//vpulse V6 ( .PLUS(phi1), .MINUS(cds_globals.gnd_)); - -endmodule - - -// End HDL models -// Global nets module - -`celldefine -module cds_globals; - - -supply0 gnd_; - -supply1 vdd_; - - -endmodule -`endcelldefine diff --git a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_11_01/Verilog Netlist/sc_transistor.v b/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_11_01/Verilog Netlist/sc_transistor.v deleted file mode 100644 index 3f854dc1e6..0000000000 --- a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_11_01/Verilog Netlist/sc_transistor.v +++ /dev/null @@ -1,156 +0,0 @@ -// Verilog HDL and netlist files of -// "pcell switched_capacitor_filter schematic" - -// Netlisted models - -// Library - pcell, Cell - cascode_current_mirror_ota, View - schematic -// LAST TIME SAVED: Aug 30 07:09:12 2018 -// NETLIST TIME: Nov 13 07:44:10 2018 -`timescale 1ns / 1ns -module SCM_NMOS_X50 ( D1, S, D2 ); - -inout D1, S, D2; - -nmos_rvt M4 ( .B(cds_globals.gnd_), .S(S), .G(D1), - .D(D1)); -nmos_rvt M3 ( .B(cds_globals.gnd_), .S(S), .G(D1), - .D(D2)); - -endmodule - -module CMC_NMOS_X40 ( D1, S1, S2, D2, G ); - -inout D1, S1, S2, D2, G; - -nmos_rvt M10 ( .B(cds_globals.gnd_), .S(S1), .G(G), - .D(D1)); -nmos_rvt M2 ( .B(cds_globals.gnd_), .S(S2), .G(G), .D(D2)); - -endmodule - -module CMC_PMOS_X40 ( D1, S1, S2, D2, G ); - -inout D1, S1, S2, D2, G; - -pmos_rvt M7 ( .B(S1), .S(S1), .G(G), .D(D1)); -pmos_rvt M6 ( .B(S2), .S(S2), .G(G), .D(D1)); - -endmodule - - -module CMC_PMOS_X70 ( D1, S1, S2, D2, G ); - -inout D1, S1, S2, D2, G; - -pmos_rvt M9 ( .B(S1), .S(S1), .G(G), .D(D1)); -pmos_rvt M8 ( .B(S2), .S(S2), .G(G), .D(D1)); - -endmodule - -module DP_NMOS_X50 ( D1, S, D2, G1, G2 ); - -inout D1, S, D2, G1, G2; - -nmos_rvt M1 ( .B(cds_globals.gnd_), .S(S), .G(G1), .D(D1)); -nmos_rvt M0 ( .B(cds_globals.gnd_), .S(S), .G(G2), .D(D2)); - -endmodule - -module cascode_current_mirror_ota ( Voutn, Voutp, Vbiasn, Vbiasp1, - Vbiasp2, Vinn, Vinp ); - -output Voutn, Voutp; - -input Vbiasn, Vbiasp1, Vbiasp2, Vinn, Vinp; - - -specify - specparam CDS_LIBNAME = "pcell"; - specparam CDS_CELLNAME = "cascode_current_mirror_ota"; - specparam CDS_VIEWNAME = "schematic"; -endspecify - -SCM_NMOS_X50 L1_MM4_MM3 ( net1, net6, cds_globals.gnd_ ); -CMC_NMOS_X40 L1_MM10_MM2 ( Voutn, Voutp, Vbiasn, net10, net11 ); -CMC_PMOS_X40 L1_MM7_MM6 ( Voutn, Voutp, Vbiasp1, net13, net12 ) -CMC_PMOS_X70 L1_MM8_MM9 ( net13, net12, Vbiasp2, cds_globals.vdd_ ); -DP_NMOS_X50 L1_MM1_MM0 ( net10, net11, Vinp, Vinn, net6 ) -idc I3 ( .PLUS(cds_globals.vdd_), .MINUS(net1)); - -endmodule -// Library - pcell, Cell - switched_capacitor_filter, View - -//schematic -// LAST TIME SAVED: Aug 30 07:08:50 2018 -// NETLIST TIME: Nov 13 07:44:10 2018 -`timescale 1ns / 1ns - -module matching_cap_X1 ( CN1, CN2, CP1, CP2 ); - -output CP1, CP2; -input IN1, IN2; - -cap C0 ( .MINUS(CN1), .PLUS(CP1)); -cap C2 ( .MINUS(CN2), .PLUS(CP2)); - -endmodule - - -module switched_capacitor_filter ( ); - - -specify - specparam CDS_LIBNAME = "pcell"; - specparam CDS_CELLNAME = "switched_capacitor_filter"; - specparam CDS_VIEWNAME = "schematic"; -endspecify - -vdc V5 ( .PLUS(cds_globals.vdd_), .MINUS(cds_globals.gnd_)); -vdc V4 ( .PLUS(Vinp), .MINUS(cds_globals.gnd_)); -vdc V3 ( .PLUS(Vinn), .MINUS(cds_globals.gnd_)); -vdc V2 ( .PLUS(Vbiasp2), .MINUS(cds_globals.gnd_)); -vdc V1 ( .PLUS(Vbiasp1), .MINUS(cds_globals.gnd_)); -vdc V0 ( .PLUS(Vbiasn), .MINUS(cds_globals.gnd_)); -cascode_current_mirror_ota I0 ( Voutn, Voutp, Vbiasn, Vbiasp1, Vbiasp2, - net23, net7); -matching_cap_X1 L1_CC0_CC2 ( Voutp, Voutn, net23, net7); -matching_cap_X1 L1_CC5_CC7 ( Vinp, Vinn, net23, net7); -matching_cap_X1 L1_CC1_CC3 ( net11, net12, net5, net6); -matching_cap_X1 L1_CC4_CC6 ( net3, net4, net6, net5); -nmos_rvt L0_MM11 ( .B(cds_globals.gnd_), .S(net12), .G(phi1), - .D(cds_globals.gnd_)); -nmos_rvt L0_MM10 ( .B(cds_globals.gnd_), .S(net3), .G(phi2), - .D(cds_globals.gnd_)); -nmos_rvt L0_MM9 ( .B(cds_globals.gnd_), .S(net6), .G(phi2), - .D(cds_globals.gnd_)); -nmos_rvt L0_MM8 ( .B(cds_globals.gnd_), .S(Voutp), .G(phi2), .D(net12)); -nmos_rvt L0_MM7 ( .B(cds_globals.gnd_), .S(net11), .G(phi2), .D(Voutn)); -nmos_rvt L0_MM6 ( .B(cds_globals.gnd_), .S(cds_globals.gnd_), .G(phi1), - .D(net11)); -nmos_rvt L0_MM5 ( .B(cds_globals.gnd_), .S(cds_globals.gnd_), .G(phi2), - .D(net5)); -nmos_rvt L0_MM4 ( .B(cds_globals.gnd_), .S(cds_globals.gnd_), .G(phi2), - .D(net4)); -nmos_rvt L0_MM3 ( .B(cds_globals.gnd_), .S(net5), .G(phi1), .D(net7)); -nmos_rvt L0_MM2 ( .B(cds_globals.gnd_), .S(Vinn), .G(phi1), .D(net4)); -nmos_rvt L0_MM1 ( .B(cds_globals.gnd_), .S(net23), .G(phi1), .D(net6)); -nmos_rvt L0_MM0 ( .B(cds_globals.gnd_), .S(net3), .G(phi1), .D(Vinp)); -vpulse V7 ( .PLUS(phi2), .MINUS(cds_globals.gnd_)); -vpulse V6 ( .PLUS(phi1), .MINUS(cds_globals.gnd_)); - -endmodule - - -// End HDL models -// Global nets module - -`celldefine -module cds_globals; - - -supply0 gnd_; - -supply1 vdd_; - - -endmodule -`endcelldefine diff --git a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_11_10/Circuit Description/Switched_capacitor_filter1.pdf b/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_11_10/Circuit Description/Switched_capacitor_filter1.pdf deleted file mode 100644 index 5f7d00cdab..0000000000 Binary files a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_11_10/Circuit Description/Switched_capacitor_filter1.pdf and /dev/null differ diff --git a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_11_10/Circuit Description/Switched_capacitor_filter_ota.pdf b/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_11_10/Circuit Description/Switched_capacitor_filter_ota.pdf deleted file mode 100644 index e1151dbcae..0000000000 Binary files a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_11_10/Circuit Description/Switched_capacitor_filter_ota.pdf and /dev/null differ diff --git a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_11_10/Constraints/switched_capacitor_filter.const b/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_11_10/Constraints/switched_capacitor_filter.const deleted file mode 100644 index 6167279df8..0000000000 --- a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_11_10/Constraints/switched_capacitor_filter.const +++ /dev/null @@ -1,22 +0,0 @@ -CritNet(net7, min) -CritNet(net23, min) -SymmNet({Voutn,CC2/MINUS,L0_MM7/D,I0/Voutn},{Voutp,CC0/MINUS,L0_MM8/S,I0/Voutp}) -SymmNet({net7,CC7/PLUS,CC2/PLUS,I0/Vinp,L0_MM3/D},{net23,CC5/PLUS,CC0/PLUS,I0/Vinn,L0_MM1/S}) -SymmNet({net11,L0_MM6/D,L0_MM7/S,CC1/MINUS},{net12,L0_MM11/S,L0_MM8/D,CC3/MINUS}) -SymmNet({net5,CC6/PLUS,CC1/PLUS,L0_MM5/D,L0_MM3/S},{net6,CC4/PLUS,CC3/PLUS,L0_MM9/S,L0_MM1/D}) -SymmNet({net4,CC6/MINUS,L0_MM2/D,L0_MM4/D},{net3,CC4/MINUS,L0_MM0/S,L0_MM10/S}) -SymmNet({Vinn,CC5/MINUS,L0_MM2/S},{Vinp,CC7/MINUS,L0_MM0/D}) -ShieldNet(Vinn) -ShieldNet(Vinp) -ShieldNet(net3) -ShieldNet(net4) -ShieldNet(net5) -ShieldNet(net6) -ShieldNet(net7) -ShieldNet(net23) -MatchBlock(L0_MM0,L0_MM2) -MatchBlock(L0_MM10,L0_MM4) -MatchBlock(L0_MM9,L0_MM5) -MatchBlock(L0_MM3,L0_MM1) -MatchBlock(L0_MM6,L0_MM11) -MatchBlock(L0_MM7,L0_MM8) diff --git a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_11_10/Constraints/telescopic_ota.const b/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_11_10/Constraints/telescopic_ota.const deleted file mode 100644 index 81e011b4b7..0000000000 --- a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_11_10/Constraints/telescopic_ota.const +++ /dev/null @@ -1,8 +0,0 @@ -SymmNet( {Vinp,L1_MM1_MM0/G1,Vinp} , {Vinn,L1_MM1_MM0/G2,Vinn}) -SymmNet( {net10,L1_MM1_MM0/D1,L1_MM10_MM2/S1} , {net11,L1_MM1_MM0/D2,L1_MM10_MM2/S2}) -SymmNet( {Voutn,L1_MM10_MM2/D1,L1_MM7_MM6/D1,Voutn} , {Voutp,L1_MM10_MM2/D2,L1_MM7_MM6/D2,Voutp}) -SymmNet( {net13,L1_MM7_MM6/S1,L1_MM9_MM8/D1}, {net12,L1_MM7_MM6/S2,L1_MM9_MM8/D2}) -CritNet(net6, mid) -CritNet(Vbiasn, mid) -CritNet(Vbiasp1, mid) -CritNet(Vbiasp2, mid) diff --git a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_11_10/LEF/sc.lef b/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_11_10/LEF/sc.lef deleted file mode 100644 index 08fe1397dd..0000000000 --- a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_11_10/LEF/sc.lef +++ /dev/null @@ -1,506 +0,0 @@ -VERSION 5.7 ; -BUSBITCHARS "[]" ; -DIVIDERCHAR "/" ; - -MACRO CMC_NMOS_25_1 - ORIGIN 0 0 ; - FOREIGN CMC_NMOS_25_1 0 0 ; - SIZE 2.16 BY 0.466 ; - PIN D2 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.256 0.192 2.012 0.21 ; - END - END D2 - PIN VDD - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER M2 ; - RECT 0 0.448 2.16 0.466 ; - END - END VDD - PIN G - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.094 0.32 2.066 0.338 ; - END - END G - PIN D1 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.148 0.256 1.904 0.274 ; - END - END D1 - PIN S2 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.364 0.064 2.12 0.082 ; - END - END S2 - PIN S1 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.04 0.128 1.796 0.146 ; - END - END S1 - PIN VSS - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER M2 ; - RECT 0 0 2.16 0.018 ; - END - END VSS - OBS - LAYER M1 ; - RECT 0 0 2.16 0.466 ; - END -END CMC_NMOS_25_1 - -MACRO CMC_PMOS_10_1 - ORIGIN 0 0 ; - FOREIGN CMC_PMOS_10_1 0 0 ; - SIZE 0.864 BY 0.402 ; - PIN D1 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.148 0.128 0.608 0.146 ; - END - END D1 - PIN VDD - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER M2 ; - RECT 0 0.384 0.864 0.402 ; - END - END VDD - PIN VSS - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER M2 ; - RECT 0 0 0.864 0.018 ; - END - END VSS - PIN G - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.094 0.064 0.77 0.082 ; - END - END G - PIN S2 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.364 0.32 0.824 0.338 ; - END - END S2 - PIN D2 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.256 0.192 0.716 0.21 ; - END - END D2 - PIN S1 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.04 0.256 0.5 0.274 ; - END - END S1 - OBS - LAYER M1 ; - RECT 0 0 0.864 0.402 ; - END -END CMC_PMOS_10_1 - - -MACRO CMC_PMOS_15_1 - ORIGIN 0 0 ; - FOREIGN CMC_PMOS_15_1 0 0 ; - SIZE 1.296 BY 0.402 ; - PIN S1 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.04 0.256 0.932 0.274 ; - END - END S1 - PIN VSS - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER M2 ; - RECT 0 0 1.296 0.018 ; - END - END VSS - PIN VDD - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER M2 ; - RECT 0 0.384 1.296 0.402 ; - END - END VDD - PIN S2 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.364 0.32 1.256 0.338 ; - END - END S2 - PIN G - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.094 0.064 1.202 0.082 ; - END - END G - PIN D2 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.256 0.192 1.148 0.21 ; - END - END D2 - PIN D1 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.148 0.128 1.04 0.146 ; - END - END D1 - OBS - LAYER M1 ; - RECT 0 0 1.296 0.402 ; - END -END CMC_PMOS_15_1 - -MACRO Cap_192f - ORIGIN 0 0 ; - FOREIGN Cap_192f 0 0 ; - SIZE 24.184 BY 4.024 ; - PIN MINUS - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 0.005 24.184 0.023 ; - END - END MINUS - PIN PLUS - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 4.001 24.184 4.019 ; - END - END PLUS -END Cap_192f - - -MACRO Cap_32f - ORIGIN 0 0 ; - FOREIGN Cap_32f 0 0 ; - SIZE 4.024 BY 4.024 ; - PIN MINUS - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 0.005 4.024 0.023 ; - END - END MINUS - PIN PLUS - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 4.001 4.024 4.019 ; - END - END PLUS -END Cap_32f - -MACRO Cap_352f - ORIGIN 0 0 ; - FOREIGN Cap_352f 0 0 ; - SIZE 13.384 BY 13.384 ; - PIN PLUS - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 13.361 13.384 13.379 ; - END - END PLUS - PIN MINUS - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 0.005 13.384 0.023 ; - END - END MINUS -END Cap_352f - - -MACRO Cap_96f - ORIGIN 0 0 ; - FOREIGN Cap_96f 0 0 ; - SIZE 12.087 BY 4.024 ; - PIN PLUS - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 4.001 12.087 4.019 ; - END - END PLUS - PIN MINUS - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 0.005 12.088 0.023 ; - END - END MINUS -END Cap_96f - -MACRO DP_NMOS_70_1 - ORIGIN 0 0 ; - FOREIGN DP_NMOS_70_1 0 0 ; - SIZE 6.048 BY 0.402 ; - PIN VSS - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER M2 ; - RECT 0 0 6.048 0.018 ; - END - END VSS - PIN G1 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.094 0.32 5.954 0.338 ; - END - END G1 - PIN D1 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.148 0.256 5.792 0.274 ; - END - END D1 - PIN D2 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.256 0.192 5.9 0.21 ; - END - END D2 - PIN G2 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.31 0.128 5.954 0.146 ; - END - END G2 - PIN S - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.04 0.064 6.008 0.082 ; - END - END S - PIN VDD - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER M2 ; - RECT 0 0.384 6.048 0.402 ; - END - END VDD - OBS - LAYER M1 ; - RECT 0 0 6.048 0.402 ; - END -END DP_NMOS_70_1 - -MACRO SCM_NMOS_50 - ORIGIN 0 0 ; - FOREIGN SCM_NMOS_50 0 0 ; - SIZE 2.592 BY 0.402 ; - PIN D1 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 1.228 0.192 1.364 0.21 ; - END - PORT - LAYER M2 ; - RECT 1.336 0.192 1.364 0.21 ; - END - END D1 - PIN VSS - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER M2 ; - RECT 0 0 2.592 0.018 ; - END - END VSS - PIN S - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.04 0.064 2.552 0.082 ; - END - END S - PIN VDD - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER M2 ; - RECT 0 0.384 2.592 0.402 ; - END - END VDD - PIN D2 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.148 0.128 2.444 0.146 ; - END - END D2 - OBS - LAYER M1 ; - RECT 0 0 2.592 0.402 ; - END -END SCM_NMOS_50 - -MACRO Switch_NMOS_10 - ORIGIN 0 0 ; - FOREIGN Switch_NMOS_10 0 0 ; - SIZE 0.432 BY 0.466 ; - PIN S - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.04 0.064 0.392 0.082 ; - END - END S - PIN VSS - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER M2 ; - RECT 0 0 0.432 0.018 ; - END - END VSS - PIN D - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.148 0.384 0.284 0.402 ; - END - END D - PIN G - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.094 0.128 0.338 0.146 ; - END - END G - PIN VDD - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER M2 ; - RECT 0 0.448 0.432 0.466 ; - END - END VDD -END Switch_NMOS_10 - -MACRO Switch_PMOS_10 - ORIGIN 0 0 ; - FOREIGN Switch_PMOS_10 0 0 ; - SIZE 0.432 BY 0.466 ; - PIN S - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.04 0.32 0.392 0.338 ; - END - END S - PIN VSS - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER M2 ; - RECT 0 0 0.432 0.018 ; - END - END VSS - PIN D - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.148 0.064 0.284 0.082 ; - END - END D - PIN G - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.094 0.256 0.338 0.274 ; - END - END G - PIN VDD - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER M2 ; - RECT 0 0.448 0.432 0.466 ; - END - END VDD -END Switch_PMOS_10 - -END LIBRARY diff --git a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_11_10/README.md b/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_11_10/README.md deleted file mode 100644 index 8c7cb9dc1d..0000000000 --- a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_11_10/README.md +++ /dev/null @@ -1,17 +0,0 @@ -# INPUT for PnR tool -sc_block.v : block level netlist for switched capacitor -   This netlist contains two modules which need to be placed and routed hierarchicaly. -      1.switched_capacitor_filter : top level module , corresponding constraint are there in switched_capacitor_filter.const -      2.cascode_current_mirror_ota : sub module , corresponding constraint are there in cascode_current_mirror_ota.const - -sc.lef : lef file with block dimensions and pin locations - -# BLOCKS used (defined in lef, used in netlist) -1.CMC_NMOS_25_1 : common centroid transistors with gate connection -2.CMC_PMOS_10_1 : common centroid transistors with gate connection -3.CMC_PMOS_15_1 : common centroid transistors with gate connection -4.DP_NMOS_70_1 : Differential pair -5.SCM_NMOS_50 : current mirror -6.Cap_xxf: capacitance -7.Switch_NMOS_10 : transistor building block with 10 fins -8.Switch_PMOS_10 : transistor building block with 10 fins diff --git a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_11_10/Verilog Netlist/__Previews/sc_block.vPreview b/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_11_10/Verilog Netlist/__Previews/sc_block.vPreview deleted file mode 100644 index 56937131e0..0000000000 --- a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_11_10/Verilog Netlist/__Previews/sc_block.vPreview +++ /dev/null @@ -1,14 +0,0 @@ -[Preview] -LargeImageOriginalSize=2832000 -LargeImageWidth=708 -LargeImageHeight=1000 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287F4F2BF1B8ECFB6A711AFD9C4A90E95B7BBB6AE4F910DF3D84DD78BAEAD87A6D506F3DD8DB95533BB2D7B7936693C778F531F34B0588849EF3F1DF81EBA99A7AB8D1FBC4DEAE305E848C51D10EBC749FD4A937986EC7710BA987EFD9EAB7117AAE3DE3B69D89BC84F4EA9BAA7CBEBAF20B8FAB897AD8694E9B5ADE227B6FC171F92996D6D29C78AFAFA70C4E7568F031397C877BCFDFB9BE9FC23679FAB1EB9AD1C3E843FEAB2B5FF15898769D7A632CC0E3E6AA7A988F67CE4498ED34988B54C74B75CCAB817CD4F1E1C0F42C04C34108DE1885C1AFC6EA7E6EE23DA9DD6A6C7CD809550FABE5AD551798FF97F89CB7E996A16B38E7538C65CA7AC2B194D0FD494B5B8A86FE56C9F3187A186D189C5F35C71B65D94E5B0FCB36A05EE3B88B2676AA3BBBDDA4CDD1766A0CD7297C672ACFC76B560F23180B38EDA0894F5ABBDD0B27CD7717756E941A17CCA95D491D8CCF8564A4D2E7E1D88D3A3730BA7DC0AEB9322E574FDF13BE57E9AB671677F877514DDB82FF5A7B6B8EF5625F1B1979AAD4FF214BF78DA5BE6713EF994DAB35F169E861FCE6A26951D69784616A7A92BF7B5BECEE710FD9ED7D3F64FDD68FDF8C3146D38FB1F7967791E1F12DF35983C7CC4CE916DB7996176D1D7DC7D215EFDE7CACEC9A755CD4A9EE44FD56D634A23EC0E721D64F68C87A2F4CDE777EE6A9F55DB14FB51E766B0B5E4C2AB11343ECFAB06DE2B5FDF8BF2BED42370ED93D203439DAD46D5F2D4EA39F93ED6A2A12641A62AAAA5D35F27CC077DA64A4F2AEAAB62B2F1B345A0F6ABBE26D24561D2BCC5EDFD8AE447B3932DB63E8BEB8D65A7D8CD9AE1CBEE33BB561FBF5D4530FB25DE17D1362EF76ED9A0F5D6B7C38B6FE86EB76ECAF833FBC6AE9F8B078BFFD68C9C7D8FFC86373D6333E7C9DE96719C7AE119CEA10FB9BE9F15F211ADB6E683EB25B7ADEC7B7560F8FF942CC6E06B3D56D8B4E8DAD3F61360DB0BA4BB2BAFBC1DC97C817219F7CC27FCFAE6DD7B51EA0917CA48689EF96CCF84AD8577CED8F57E900379A992FE144B3E3C34EDFC3701EECC0975F4020300D017F10520FA7CD6357D9BE90CFC7B5CF542060EA44A778C4F658CE6EF51D4B65F9DCD9E02D9FE59DC56BBE44ABF01A1F96F0B8EAE518DE5E75E768B7B27DF0D840601EC2C1204C8582EC1DF991A3DDEA8D81AD1258D0CDD8E312B76FFBADC2697CD88ED37C09DFEDCAD8DF241F77133A07C76EE6E7533035A94324988695E9E7E63E9C4B3A38FED2B1EFF9694DC4230E300D9757E6E44DCDB36755701366225B70F32F4F581D8B73D1BFC48DC1A7AC4F7ECEFBBF957967AD155828543DAB4EDAA6C8F5B14956FF39D775088DCC97E0F36A023A88B5F93AF47EB9CE9F6B7C3C6B9E3DDFC29BAC4DEA303CB86ED1C353BE94C576B5CA8C6D7BEEFB6D9ECF77D39BF0C5974F2CF323DD9E1B2B4FF620AC6DF2B15EFD3FC53B093E9F8283BFF076806598666531B215EDEE56DF15FB54EB61B7B6E006B6B79EEE457E0D383E3C1E79CB7D92E03C583DFB11422CEF20BBD67BD329A6F7C4731B6DEAB6AF16A7D1CF99EDCA657FA3F3E91EADFE019110BB57D9B5AAEDCACB068DD683DAAE2291347C75F71584309EA5F28EE754DF59D6861F3E7AC5CF9B7BB4656A27D9C7C876A5F63139A6DDB5C81B7ECEFC24F64B0736FB54B761FBF5D4AA03B55DE11C81BE9E9FCD76759275EF8488D998E2F366D10679E380BDC78A6B409D7AFBD222B733AE9BE8EC7CCCEB17CFC1F9B6397DABEA9C5A483D8C63BB8BD3FFE4E7ABF9E03E9F7F07FC3785A6729B3F8C4CE073A374C0E75B5E1BC07927F56958373D2CC6A2EBD7C15EE9791FDF3A3DDCFD976F589F1128DB2DCAEC76C9DC77FB520FD751A2EEFA2AFBD833BBB42BE698E11C4D757CCE8D46F271D2C3F8FDF0FF5BC03EA0FED84F8DAEA77342D5C381F955589A0FD45D174EEB259AE1B8F325EC65F45A4FD72AEC7A186D87F387B12FCEA62AEF3493F7438EE7B7A2EE1A1D1FC6B2E9E8FFA8FCEE80CFD342B2F2BCF25AFBD52A44DF88F38757459E46D112CB596D57D23EF25BA1DCEFC771B76DF1CD3084DF329BE8935A85A8EFDFCDBFEDE397A7615364E2EEA4B946F5A19EAF8A6FEC750F357B1F373267AE191A796E34EBFFA3621FF7F912ADC66B4E4423F3254EA39F93ED4A688889AA767512CF87466C701AF57D9C3EA651EDF32920D744F27587B11DD8DE16EFFAB84E555D9F883A5EF54F29D7E8AAE778A1AE49B4AC9DB5E523D734CBF71727FF1295728B75B81B317C57AE3DBFE1A7F81EF87E78E3A88787FB9FB27C5E38AECB6C343D37D46FA8F635963FC5932CAD27E0BB3D50575A72FDAB1C6B936BFF711C0DF7497F10A2EE52E63E7C664FCD3DE27F3F7D84EBCBBCD7BBC835DCF67C52C9A4633E72EE2CFF46189C65C706E1C9DC14E433FFD550BB3CAECFAE5AFE25A4BDBDC6185BE14F07FD6ED8C736B91DF306ACAFAD39D6F7ECA355F65E3EC3CB1E08F84CDB7BF95B6B256EFE2590F99504044301F00542904FAD9E48DD79D9CDABEEB06D4EDEF3F1EFEAF33E7CF7A9BC7FB9F9063B0992E85F42D3408F4541DFA8D631AABF35E9A306C74364DF876BBED3F90F70ADE767F07A568D32CD76D2CFA3F9953D56DF293EB635EFB38E119D964DA50F12EEBF2519837C5AE824AF7BC86EEF46EE63AC872FFAD74F4C0F7B8DED3B81E3F7C9F0B386F391EDC9776DA9E1739B25C4AECD6D4E84D73E95D3EAE74CDF365A986988A4D9AE90937A3ED46B836668B4BEF1BB47AD3EC62B9F46DA3041100441100441100441100441100441FC19708BE77E9A71B75B1917FD2CC4A71765D02CFEA8ECF10C4E321FA7791D0441100441108433A4874FCAA6A48709A21632AEA5BAF68068CC76EAFA108220088220DA4F2BD6641D97B3109F5EC56B9D09FA441BEF45BF1F8DC7C6FE1CEA8EFB68F5582BEDB6F6AB1D7653D7D39D059AF55F70966C5ACBDE67E93EF65A8738128C371C7BEDCF6237D9FF35BA86F334D7D2129F36187F42C43FDF8218C6452F1D5A62AC63BCC8B48C638D7F97D7178B18DA95736AE5A3FA97903EA7EDF9E036395681F1DAF16F27FF1222F67841F89768C05FB05CCB6DBF167E3DF98FCC0E6FC5F5D419DBC32B3D2754FF12927C3A514E2BE6B8DD096137719CF4EF108E26C4FAEB44C2DC877E09709DBE539AE81FA29E6B8C26D28EF9A8A8F9A8B1DEF9B8B3166536D5C0C8671A6A978DFAECB2C745AFE55FA299F8F4DC6EE90F66DB54B1C78657DB95DC8EEBCAD5EF0B59E380DF43181F1E635CE2B644FA83D9FE4B18379DB531F51C2F3F449D97FD0D3F4B9DE2C9BBF99790BE4524312D5C77DDB9D94DF513237DCEA876C3ED99DD0F55DF65D096BC5FC808DF36520F670DE18B55B7DDC75EBEC19AB11BDAC2ED3B4D0CFD4B60BB62F62915ADFBEDFED6DCEC837D2EF62959D6B7C97623E329ABFDA6BDFF44BF2E9AEC433305DE7EB0BFC57B713B55E0318C785A4A9F29F5B03D1FD116DE5AF251CB781A36157D7DCAF42F918955FCD9A46DFD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DF73C7932E51DA2F711CCEB74E45E2B1E692C517F6454A9C67238B03B7E5A8F6571DF5943390CF5F51DBBDDFAA941A5A8DEC35A5D123B9575DCECB4C3656B3E3B5725F5135B4C7C8AA145A8150168B4CB90CA9C98B1E45188AFB03E558E7B91CB6D205EA89031D9FC5CD6388AC805636CDD50A70A42218F92DF379BD22954AD79C40A951459F2AC58302FD4BE37A651CFC7E19ED3A2676206D291118C4A5598D36A2055299E9B474827CE33EB24BE52D241645536E55B5ADBC1CC507B4B59DDAEEA3AA8374B75ACC66A791B6EFD34E6E34F90F5AA6BE93A76790762F9F4E41935D97F174323326C97566BFF89F5403F1B656B9718A01BAADA7FFADC4AC582AD65F3066B6BD562D9AC8B611827A54DB2A9BD592643A36C418F83FDF7243EDF241B85B8AD21A22B4136DAFF5E77EB776462A92C62412FB6E818514EC1E2F0A2F7D1DDA6B2BB247A6CEFF26B4647DD181FF5368D1FE9EE27FD2E2176D83CEA247DF60C898518D3D5CE6EFEE7C9439F3DB3EED53A7962A9629DAE1AE519EE32B594E7493CC1BEABBDEBB56BA1EF047968DF3D4F1EEA33558A790C4F98C8BD263BD2586A1B9E4625ED84C9547D5EB7B7E0E334F61DBDCF07FB47F0B2732D8E7A087658A5596176988E95C57805497BB82EDDE0900F3AA91B0A2979DE12DFB7ABC789AF3E1B6FB2C3A3E47EB09862C4DF6BDE77A1F7D6D8900B15F269562D413541E75E1B4DE90EB2C3077DA7A0365572EF3BFCE67C3BB3C31FFDE61B8C3EEE20ED923F378F904E9C67DA14C14E2942646DB6C325D2E691475D2D651520D8E14469ABA51DEEEEEC05F5171FF68C42362183714AC1E69713C3C3981A97129FB58C7397AF31DF8B727CC56D6894ADF3F1187CFAE117ECFF3DD9E8F768BA88F919559D6C939620AE5EBB05D9605F9D6CE5F40A1E48CD90F5DE4636156BD2AFB8ADA660E18564A36345B3FB7CC9E5B24D654F98C2C8F967D8B89B94B831265DC2CE56050EEF8F908D39599A873D1EA2533F028BC4179684D1717316538A25A2C70DA62BCA0339AC3CD40E37CA23D655A33CF38175245C51268F7126589367B4C74AFA3840749AAD5D0B7DF722F25074B477C2619923F75AEE486349A337413A26ADCDA784395C231AFBEEFC954E6C659B394F1C47075D97A0EBB27ED1BA845A4DC774BD9FDADEED469AAE4B483D181EF5A3925BC3A0C4CFD622C4EB120E6F0613AA1032E14C5D7E7FB044CA0D625C525D6BD2CED0F590667BBBB2BA4ED235FBD2C2BA84B096BBB29A21E9C69BD22DB8A308D84DD0181731299341313E8248AA04B356FADC3C34DD2499478BF3509D286472D8F6799F4EA3D11EA85F615DC23C53E52E8FEBED588B2DD4FEF7917A129EF903CBF0879644FAD96B43A36C3364CEFC22EFB809EB12826CEA190326140AC4839E43CB1626F3F1ADB595967D226EEB0CE36EBFD8FB775E6F08BA9919F85C3656F6E8C81E1F85DA693DD1BD235084DB1286CE9A21F3F56594C9EF164BF37CAE11555DBDD8BD2296C7EEF2D7E9AA519E58AACCD643A83CEED7248FCE68C2D8C008B9D77C471A4BCC7792EB10F4BBD8589A9F692DC351FA8EE3D5A3BA17B6B7E746D7B35EB40CA32555DB8F8B053387AAE745F7EC28BCC1586DFF8DCE6F5F348FC3F2F6BDBFCCF1878957713FBC4E1CE69E7E93BA12CB73141BC5F1D3C061FC91E7E5D73FC7BF3E2CC43E4C998C51D9F0D04B97F93CDFFFB070F8522824DC2F259BE07FBE0A792E7C6F42365568F99FD84F1D1A519079E2CBDDDF2F2BF7822383819EA38FB1D709F198A3BA4AF94C2F55DECBDE0F5457DD833E94578FF719711878C3794C69A3981C76635CBB8CB03D8C215D1241F269B627215786115EAC9F5725D21BB87D7F1E95E206C9936479C2897548061D64AE16C2C84400D9781663936168A6C2587234F3221E8D47A0ECAF72AB945351C85501F8ECF5E9F2C5A775E9C4FF8DCD2C42DAFF0063BD3D6C2FFDDEFDDBB5BD7401E35A3B867A3A19F7A1FB710F1EDCBB8F7CA180F6FBF7108B2730A556C1E7B436B42D5FCB739BA413E7296D6D61563B8368A03537E8719F14DBA277B8F7DA3A0DE7F4385B07B87FEF0169AF0EABBB1C002AB7C07DA0F983B332A4F365A2CB1EF44946B19A4A61C63C87D9690DE327C472158C0D0D307E022D4F68F716F59D260D181C1945A59080C612C1AA4F5F93E15F3EF8B7261D8A65A3D7F7DB7BA0A1EF25BB17D1DDAF845A25ABF101A8FDE8EBECAA93CD6792C1ED0B10FB3C8568C45B934DAFD3D6CA56923E5A2D5570E37617C627D5585B09133DEE40DAD7FD5CD9DCCB25745E395DBDF606A1554F41315EB5D9A64096E98A5EEB6693709AC3C897B771E5AA11AAC910D149142E7F9EE8C7C2B81373F63426869D44FFF388673630F4D00AE9B81FB9780E3D5D4E68A742F03A13A4DD41D2EE00E9E7302BBBF7F170ED1D93BB23B3B0AB5A730ABE3C7D05DBA565C4D67630FCF821D4CA2952768CD8022FEB23811F23C81D4D55209FF04135E8C10A9141A508E0FA4D1BD2D1247AFBDCD069C27035DC37BE70016A851F3F7CAF65EB088F2441720F2C302E86D39D85461746D09DC4F53B56A60383D28748EE69ADDD740F9DF237A84E681EB93C54578FD0067A3D4B742A69AFDE4F5333310CCA02D04A166175A6C9F80DE126D1F356B97E6F473CE6A8AE2E7FFD514B5D09634ED0D5D4888CE96ABFFB818E3DC9B01F13A341A62BB13C8D6D1090266381EAEA6A970F596FB8AEDD54575AA2ABF9D908DB379890BA98AEE8BE41DF900F77BBBDE419B25CCB43C74F633DE2FB86EA6A7EF6E5CEA057C8F7D6DBD5F379CCC89CB8D1EDC6D8801333F2FDD7E2CF5D35C16E8AD6F2C87AADE890F9312FAFDA28C5849FD88667D0CD4430AD6CB65BF3F12DA61F7A9D4C94502957A0996CAE4F9CAEFEF7EA1E5024588D35B1DFFE5B47AF94C8D6CEF689D50A15EEDDBACDAE7DD1351855A364BE37D9946FBF3C745F5D4EECD4BDAB57B0538A35E57BD8DE9A3B2106DD17A33EA04636D52437CBBF56EDCFC1B151F69F6E31898B97AE31BEDEE2ECF481FC040A3B19CB618B89ED71AB07DA5E682C50D9D8FD4464A3F33C49AFA416932990DF8141D25E271BD5FFFDB62EB69EA31C1F6D924DBC4FB79C2E9271B2F79EF7FD072F261BE58464779F3B748FE9E190AEA6AB31891BA34355FFBABFA71A9B42B13B96843DDF58A20C95DC8FB63BD57527AD3E8EC17E37B11B490CF656F7F566B4D1DD76BB904F549FA7F7298F217BB8F52D01A1481C936A25BCBBEF1ED6F5F1AEDC4A6584AD33647365E8882FB3BDF6234665E41E7F9287DD95213635068B215A57AE4649F7180B181F7337DD1B93CAE0EEA75FA48330B1D74FEBDA2DD6496479AD653D14B2312F64EA28D64A25CC4D0691A83CC3BCD40BDD64B59ED1A166AEF451C61CD55547775F6B5DEDDE0F81DC3344CC21F69CA5BA12CBB35F1B74D319A6AB59FF939A8E84768B754579345B852CD355622184697D0C97EEB9489FA75F485763E33E6C958E3E579212DBB9BDB5099B7599D9D4E1BB3A7C74C68285B910C646DD28579EC2E74A36E7A3DC1BF2CC55CFA7599EB1611F69931343DD7684521B98D3F8ABFB79A52770D99AFD61F1181A1EF2C264A4FB7CCD1CB6E7D9E1BDB1D5DA0EFFEBAF3E26B2C920950EE0EB6F6F115F478BDB17BE86399C43296287C6D01C7368BF3C8B292A8B0E0A99063B95D5A67CFBF9C362505BE708A76050299BE416FBC303432330117F9DFA02B3261BA6944A66130FE227A4B24574F6CAC83CCCDBE40F1F06821D9E944E2297CD319BA49055CB17FBC3826C541E4F2046649B443EB55C932DB81B134FE8239A9796A773AD622D3CD7E40F1F0672D924F1F35398B756DF8917FCCA4CF9198CE4393FA1A5F753813C33E7C9F33C846438CDF6CA4CFAAAAD2E91FB76D69482C352D5DB942606F9988FF8E794FBB504AD3280642C4BE47CC2DA3D26ADFA0E627FF8B018EC7D4C7CEE526DFF4CDC4782DCD49F552B43508CB950592B424DEEF14BDF5B991DB6DAD2C43F8FC0B3587FDF650A9BD0E9A2908C78D8FA679D2F935C2763398CDC6A11038FDD4C07DEF96A5BC5ED16DB96506CAD653D546F1AE24FB942E49940F437EF4863441D2476CF87A55891F9C30FAF3773D38F32E6A8AE6C565F4B5D09F703BD36CCAE6068C4CF74259667BF3630DE23D1D53899CF8716E375EDA6BA9A9E2173F8A53419EB09E2E77A7775F58CCCEF0AD0313BBDFD42BA526A9699AE5EA4ED6254B688CF4AC640CC9F62EF5050BF9D964DD7CB52649E6933C65028D48F43BA2E41D7C223A14C2D4F918CF3A037C5F22C5AE37B651B22C8A58A4DF56A2D499433D5F7456689FF4FB914B41C719A62F9695D3A31288F53D853A37BE9B685E67141E73961BF8BBD6B406DC382B5BA0661B3DB502E1731A59B697A3F83CEF5853C96B9B9BA3CCC1F56AA918CB6E6D53DEF7D265A36F51D435E574BB969FEE7BD93952F6FD5F86B4532879899DEE383CE18CCC4CF9257EDE311DE8152EB8C647E40EC66A58C5832CDF80065D1BB862F225BB58F9DA4EFAAFAB5B93DBBBCAF2D04422932A74DBFE038DDC69CDD8D25CF629D3C74FCF9899F40F9612E571AAE86773F0FC39DA8BBAFC83D3AA10820E6ABCA77143D7A4311CCCD19199F6C291283CF6BABFB7F3F3DEA8D44D75BCD3CCEFD20D52EB7BC37F4D3917DF3503DF95C89176E5388D884157F5A5447B35F78545D39E6AADCBB17B91F1AE5791EF66BB77E9AFA88CDFE9F90C7F412B6F55583F325383838388E17DC0E1F0E2F1B8FE130FEF06121F64DE87AB4D7FAF27BEC4795CD1E5DC7FDDBF38C5F4EBF8BFDE19791ED55E9EA7EBB635FBEC4AB8ED9F12AE57EDB626434CAD66ACE43D76378BC8A66BC0D7C8945771A1ACD1212B1FAF7895E275F82EE5F1B0CF34DB1280FE24BD03975BF7C0A06ADAAE59922AF8A2F41AF050E001DB733B309F66CCA26F35870AE92EF1148FA1CEC39D53BE8835E17423ABFC9F43FE3CCC1670ABC36BE8458367A2DDEA71764EB7AB8C0649B9C8A6242BE8468BE821BD7E61827617539F756F325E83A07CDE35AA88EF9D7C597A0EF2886EC5AB4B777B07793C49C18B3CD53E3C488C748265D649C9809763ECD769D6CC1DCD6A1F8099DFD2335D91AFB58904DE0C4CC38C38C13D3C8D7E91D94324E8C98AF43EF0D3127868EBFFDF600C4729FFAF67B7ECEE2CEDBC19750EDD6A39A78737C09FABF95DCE721B3A229DF7E792CF13246EF7F0BBD418FAD6CF31AF1ABE44B081C007DE009DBDFA56BD34AA59FC5F6A8E6AB8FA1403138E6AEE9EB75F2256AFC046A6B457BCFFBC9167FB253C749A09F6F2B5F429C87C9F99AF812945B92F3EB6BFF89393174AC1DC489918C6AD8390847912D5728D5646BEC63B14E292746B8C71AF93AE2181562D9C49C183AFEF6EB63B1DC465B00AB7EEE1FBF0D7C89697568F75E7B713BBCDF58A538882F21A4196AF10EC17E7972951D8CF4F5229568BD0FF2AAF8128D1C000FF153E8F38CCEEBF5FA28DB47A57B0ED4773B776186ED8F527F7880D822B9C4C7DE497F5D7C09B16CF6197FDD3EBD201BDDDBA073192A9BC5188137BE8EA10117F13983640EF5E4ADE64B54FB64CF0EBF2EBE048D61A7924DC0B750B5B7624E0C8D01711027A6AFEBFED165EBEFABC9D6D8C7627F987262E4F45C1E224F235FE7DC85F3354E8C58363127E6B0FEF01CD143C8FE62E3F4A788B7812FF1FFB7F7E65F6D66699EE7F75F999FE69C993E67A667EB9E5353935399D533DD39D97DBA2A6AAA2B4F5655765646464666446646668463CD08C7E22D1CB6C30EEF3BD8C60B60402C02090909814008219040FB2E2124248524103232960F73EF15AFFC0A610C84C3D811CF0F9FA357D2DDF5EA79EF7BEFF77D9E089B97AAFBF97F74A926CDB7A9977039FCAC0F6AF63FD5D6E4D94C2FC15F9DAE282CE651E143707D7D4F4B2F21D700ACF7FFB91EAE3FDDE8F36F4B2F51A34F98DC5C8BF0B8B63DCF7A09EEDF646AF291C6EB59EA251E8D5BB6AA3B919F235C8FC235319651FD8EDB96CCE6AB6DDBA92686B78F1FAFD7EBC83531B43EFCF4F9AEEFD3C9E1F38D9A3D3B8AE14E10C47300D9E1ED8FD9D38865F1B4F6AEE5B1169EAA766287BE16E4FA84F57120262DBC6DDBD7243CADB1AA2B97F4123B6E1BCD87B7CE4EF4128AAE3062A104CE9F32ED482F315F7888CB67CCE8EDACFCE6BBE15F221E8DD5E4191A19656DD78A6721A5FC5C3B21CFD374FB0E72A9382EDCB88D71A38EF5E12CEBC3C63E6A9EA49DE0C76D8ABEAA3E617D1FE4FA8458BE8CAE86CAE7727D42387D1FBA7E678D3E41A50A602E9E63ED9DAC6A2778BEE65B5BD3277CF0DE7B756D1B9AF4D7F455DE36CEB9AF4C356DE3CFEDF3F7EDDD1E5CBF3929AEDBE6A994685B8AB54DAE4F58DFB63D9F1C7DA22661763E5FD54EF0E744D68F95D41EC9CF02D74EF0B534C91F4378FE5E553BC1FD08C87D07DC6C7389181E8D8DB68A1EE539D24B701BC6CF53E370658FF779D34BC8FB4A7A89EDB113BD048F31A33506D17ED5BC63BD846D3A03F7DA3ADC6EF89790E7E17EE987551A840BABF0196AFDBDCBF3F0E3C65B4A768E5E15FBD9B6693FEBC3C63EA5B6AA9DE0AF1B69276AF409CA00BAD8EF51A74F6063CF9F837F927682BFDFAE3E617DDBE47D95B78DFB3BE77B70F3AE684DDB2A63E7DBB86D35FA84F237D24EC41C86BAB192DAB35E3B218D07B76755ED041B3FB9EF80B66E8F6893D4EEE7492FA11B0B8BF354DBCBEDDEF3A79790BF27BDC4F6D8895E42C9ECB0B27D5CC4E690F26C472FC1E72F8B997BD567F877C3BF843C0FD784197506B8322B888ED7FAD993E76955A8D935A81B7F7AFD775860FF93C54C96F5A1BE5ECE56B513FC95EB13D6F741AE4FE0317FB8DFAC3A7D82358DC56CA1469FC0D7744AA512EE2ABC55ED042FAFF931B1C7B6D2B62C9B1FC9FB2A9F7F4AF188782C20A96DFCB97D3EFF0C79E6A11DF057DA76C224DAC6351FEBF509DB6D9B7E78B2AA9D583F1F96B747F2B3C0B5137C1F59FE1CF023ED44B9C6778086D9E33ED63ECFE4DA5CFD39D24B9867E6C579D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677C1FE3CBD9BA23363FEE3E788C5DF2A96E7DF1B1C197F7FA5DFCDD7FBD8193E9C5F5461BAB667CAE8919787E58CFD5EF57C697A79365D20B75832FCFA4AABC5CE4CB633CCF628E97CC7F62FBE9B59AF375E88B791575B077BCCD6E8722CB884783C80945D2452252F1145C76F63D694CBA217F41A64A7796173399CCF238DD5C567A69CE480FCD4D3721912F72FD64B73BE0F785C86F0B23120C239E4AF16FC8A3E3D30B6BA318F49C9287BEB8B16792B97792895701DB9FF387E0CBD9587D13BE9C7110DF79CD59DC06FB8EF57DE53C1F5BA2A3DA994222BD6CC66B9878197E28BEDCEB61F981E7DF587F08BE9CD5E3F578E7FB405DC293B3F5468C27BF7FFF2E1C3191EBA7F567DB1778F280C361F0E41BDB1286BD194FDE6C0E384FBEBA9FC7FEA3180AF9C685F51141E7D15B791626DE7FC4E255832FCFA5AB707B55BE07857EBEDF9BF1E581A00AA74326FB6FC0733DAE3D9BFB4F6C3E592C8790C8DE6325B3F70AE50E8AD9795E4BB78F8DFFE5FD35D87C62BE89DFEDC1FEDE061CF618D2721A3B6BFB7844FE17B3F7EC363BD96302425E37D472957C9E201C0999FB4FE3D1185EB6CEEE6CFDDE556DFCF45F3EC6C79F7CC2BF3BB1F9F4D1EF3EC1FADA36F6B777B0BBB183878F1E231509F03DAD7AED061DCF607F334D3EDC2CBEC97220229B6FC27D2462D01B2DADDF63A5B9DEC8C4AB627A72CAF75E194F9FA3C7E28CDA63F4C97FE9D1FC5BF49FCE23164BD0D89B9F67E3F2C5C9D5DF86AEC26074F53D6CBF28C6EFE97959DE061673C7F47A17ED53331F8B89B7816C36BFB42F5141D6F8BE44D1788AE75F61FCC364D05DDA8F88CDA145EE7938EC1BDC73F32CC716DBC7885D97CD5CAD5F4C98F8A9C1EA742118F4626D6D036E9BCDC8F5582894D0AA96516FB1BDCA22640FB27C0C73BB8EE5887CB263856DEB29F93292719FDB33DB9F46E79CD74DCED9C4070C9D43CE0A79BE1F513E2FA1AC7DF77A6B76DFE4F405F68F5C9874CB2FDDC7C884890F0599E49B71D3CCB67BDDFC967C1FB0D7F0BDD81A447EDFF75CEFFD26F767851686FDF9BE71FD37FCDE108D96BFB72C267E7CD47A277C9F5C4DEB229FABF1FD73ED4779085293FF9F4E37E87C05996C13995899EF3F984955F0F4710A72BE8140B2C5BFF37AFD259495F9FAA27DB2E3580EFD7832897A753E36589CEE627E4BCB9EC8D75CC413B3354F0EB7C27346FA9C05A40A5DBE7E432EF7E03DDC32EE617332EE9690135B8886341AC30D58AD7988721B79FA9BC5186769BEAF6F1F2CF1E7191AEBA3760F9BDB02DF93F4E0A8C065B71C4A08055478BD1ACFE3EEF315118B68585D5D5DEA2B266B38D644D82FA3D56031C502F98575EC51A990ACA178092E1BD5152EA3DD9D901C024AEDD152AECD4AE798CB6EB1D2751E85F7772E5A443054E2F1D1914885F7F7D64696B781C5436B24D32AB7874FBFF7F336F1C3C29168F37D72F36C3D5170B63680E53062E384FD1F4F36E075CA108436DF833691A6F94463716B33C3E75354987D6F0D06CB3CF7A35EAF9E3BFFFC7E5076BBC758CB309C9EF21C92F110ABB74A73B5814CAE8E72A146632E87747180C3DDDC059903C10A7C749F20D17C62B2262AF47B25BEE76F59EBF09C9CD94BF427FB2D76DFC65A86CF277DFF4E51EAA02835B0B993A779D1C216CDB75271390F9F2EEBD66A1631BF84416FC8FB83EFF9E155F8BEBAF7EE27E0F2A808854A463F5E25C3FE6E9ECFA75A638861B38D4673CCF389B2BD7D597F6FEDE4781BD8778CC425F5987837319A3E5FFABFD618A159EFBDF2FDF5F6E576582C91E2FA89ED07753C99DB776C9D84BE0681BDC32B959EF11D6B116C8DC655BFC962838B5A0FD3735CFAF025DC3A8344F34F229DA616673AAB5C7EF576EAB246824CD79E7CE7FDFDC194E7DDBD4C0626BB7AF6AD81AD799C0EAF5E2BA5A82C5FA869EBBD2FE86895A5F294306AB630E98FD09224B28FDA18D62EBEEBC7DD3E5E9C1E63DC1BE0643C1F0F27A72FD05CE0BE87CDD998AAD0FC3AA1B95489C530286B68C9329EB36BF333FD534BCFF6B519773A18B6BA68CB0A5FEBC4AE1FB73BA867B2FC37DB420EFD5A035D4D432327E2F974884EB583AE38E7359EB36F437DBA5694D02A14A96D647F8902B547A4FABB18767A6407F6490685C672CF90B957ADE3F9644475935EA8565023999F4FE6BE90B07B48B2AB5CA6E7F48E68150A86ACAC6DF58C8041AD3693F94C56DE26EACF617788E4BDBBE814352EBBDEBF27C3D91A938620F3B6D4D299F9FF93FE6B3F4F13D70B367F2A9180516A7101B2ED005A2801E12884A26D1BED228B1B5CD6178AC707CD1F4029128516081BC747E3172839E66BC987DDD93B5C38B4A3A348749F9BC66A1D25AF178ACB834A2A87662E0DF17096AF25B1B6838E2CA2E677A01C09437638D1522B08DE7A8CF17088ECBE03A530FDA6D74F321F433A5BA3C0C6B1319F08D31EF983645B06BFB97F26AF17456F00911B5F40717B21D36F3704F24D424143668DDAD25155A8BE3052ABEB28FA43D4368F516785CE178E0E795D9D5A1F0395FCA6808FCB9AA7F665F6AC386EAAFCBC2EEB90AE19369BA809124A82467504B9EC7AFF4EAA79E339B0B670BDE673E284DE09B2DD5CC7F43EA29A95E81D5AE5653D9540AF54E1E3B19197E9D97BB96E60BA68F19E82DD49E32F896A3C0EC5B9BCE793E60B5EF80DD51F46251CE0F370D4A8D1FD0E1A9B7654E22934D2698C691C75E87DAFBA5D28D01C4A3D794CEFEB31CD81D95C65FA8C954D926948FAAA5D98BDFB4B91F095EDCA6C5B492F4649A7903FB5B50DC945F33F4CF2BAE8B76D765463496A9FDB9079329AA0A71549B70C21EEEDA35F6F63B0B0D762BFDE44AF5C8212C9F3FE607AEC643C3064EDB0F5B8A72710F6AD86ACC70B6B283A6A112DD2994CF653D2897AFFEAE7595B06C3637432B33C01C385F5F9264CFC5068E4D97ADD1F97EB623623B755EB756E3BBE693D83669BBF4F168FE97630C375F7AD89EF87A652C671AF65946CEF4F956C9A5A4AA0F7EE066AD9241AD98BDF5C4BD10CBDBB5534D5327A85F9F9C188F49D676EA714C333AE38B777C0C74D6E7B0BD56818E2C101B7AD14D245FDAA46B6CEEC9EFCDE21D9526DA81E277AA41BB29B5BA827B324CB3A1AA242B69A0F82E500A5508CEB0AC9B28F66B1864E3E85617F827AD83D6F9B467E563E43F62BE923970F2D45A1777F98EB46F1D08A22CB53998A5319443D97E4B23FEF16514A2449D76890AD4E5E3FB345DB677E5EBF3544C1E9217D4EB26D6F531B2AA4A7C3681414089BCFB8EDCB641DB6BBFC7C2D93239D3BCB3F5DB0BB48D78B747E85E48FA214A4DF4F66907ABC6AE87F2594C271B76694A5848849BBFA569EB5891F07C5339B8395923300D9E9223B2E85DC8107CAC10ED9464E7ADECBDF2599DDA6FA679C7825E0378E1F33BBFFF0629E1FC172844A3482A2C783E3F184E68B97FB316A30866E5186C2D69FD398CADB3CA8464248DDBB43F33843F36F1F23F2DDDD5FDCE4BC41E8E603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- diff --git a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_11_10/Verilog Netlist/sc_block.v b/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_11_10/Verilog Netlist/sc_block.v deleted file mode 100644 index a52261fe3f..0000000000 --- a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_11_10/Verilog Netlist/sc_block.v +++ /dev/null @@ -1,103 +0,0 @@ -// Verilog HDL and netlist files of -// "pcell switched_capacitor_filter schematic" - -// Netlisted models - -// Library - pcell, Cell - cascode_current_mirror_ota, View - schematic -// LAST TIME SAVED: Aug 30 07:09:12 2018 -// NETLIST TIME: Nov 13 07:44:10 2018 -`timescale 1ns / 1ns - - -module telescopic_ota ( Voutn, Voutp, Vbiasn, Vbiasp1, - Vbiasp2, Vinn, Vinp ); - -output Voutn, Voutp; - -input Vbiasn, Vbiasp1, Vbiasp2, Vinn, Vinp; - - -specify - specparam CDS_LIBNAME = "pcell"; - specparam CDS_CELLNAME = "telescopic_ota"; - specparam CDS_VIEWNAME = "schematic"; -endspecify - -SCM_NMOS_50 L1_MM4_MM3 ( .D1(net1), .D2(net6), .S(cds_globals.gnd_) ); -CMC_NMOS_25_1 L1_MM10_MM2 ( .D1(Voutn), .D2(Voutp), .G(Vbiasn), .S1(net10), .S2(net11) ); -CMC_PMOS_10_1 L1_MM7_MM6 ( .D1(Voutn), .D2(Voutp), .G(Vbiasp1), .S1(net13), .S2(net12) ); -CMC_PMOS_15_1 L1_MM8_MM9 ( .D1(net13), .D2(net12), .G(Vbiasp2), .S1(cds_globals.vdd_), .S1(cds_globals.vdd_) ); -DP_NMOS_70_1 L1_MM1_MM0 ( .D1(net10), .D2(net11), .G1(Vinp), .G2(Vinn), .S(net6) ); -//idc I3 ( .PLUS(cds_globals.vdd_), .MINUS(net1)); - -endmodule -// Library - pcell, Cell - switched_capacitor_filter, View - -//schematic -// LAST TIME SAVED: Aug 30 07:08:50 2018 -// NETLIST TIME: Nov 13 07:44:10 2018 -`timescale 1ns / 1ns - - -module switched_capacitor_filter ( Vinp, Vinn, Vbiasp2, Vbiasp1, Vbiasn, phi2, phi1 ); - - -specify - specparam CDS_LIBNAME = "pcell"; - specparam CDS_CELLNAME = "switched_capacitor_filter"; - specparam CDS_VIEWNAME = "schematic"; -endspecify - -//vdc V5 ( .PLUS(cds_globals.vdd_), .MINUS(cds_globals.gnd_)); -//vdc V4 ( .PLUS(Vinp), .MINUS(cds_globals.gnd_)); -//vdc V3 ( .PLUS(Vinn), .MINUS(cds_globals.gnd_)); -//vdc V2 ( .PLUS(Vbiasp2), .MINUS(cds_globals.gnd_)); -//vdc V1 ( .PLUS(Vbiasp1), .MINUS(cds_globals.gnd_)); -//vdc V0 ( .PLUS(Vbiasn), .MINUS(cds_globals.gnd_)); -telescopic I0 ( Voutn, Voutp, Vbiasn, Vbiasp1, Vbiasp2, - net23, net7); -Cap_192f CC7 ( .PLUS(net7), .MINUS(Vinp)); -Cap_352f CC6 ( .PLUS(net5), .MINUS(net4)); -Cap_192f CC5 ( .PLUS(net23), .MINUS(Vinn)); -Cap_352f CC4 ( .PLUS(net6), .MINUS(net3)); -Cap_32f CC3 ( .PLUS(net6), .MINUS(net12)); -Cap_96f CC2 ( .PLUS(net7), .MINUS(Voutn)); -Cap_32f CC1 ( .PLUS(net5), .MINUS(net11)); -Cap_96f CC0 ( .PLUS(net23), .MINUS(Voutp)); -Switch_NMOS_10 L0_MM11 ( .B(cds_globals.gnd_), .S(net12), .G(phi1), - .D(cds_globals.gnd_)); -Switch_NMOS_10 L0_MM10 ( .B(cds_globals.gnd_), .S(net3), .G(phi2), - .D(cds_globals.gnd_)); -Switch_NMOS_10 L0_MM9 ( .B(cds_globals.gnd_), .S(net6), .G(phi2), - .D(cds_globals.gnd_)); -Switch_NMOS_10 L0_MM8 ( .B(cds_globals.gnd_), .S(Voutp), .G(phi2), .D(net12)); -Switch_NMOS_10 L0_MM7 ( .B(cds_globals.gnd_), .S(net11), .G(phi2), .D(Voutn)); -Switch_NMOS_10 L0_MM6 ( .B(cds_globals.gnd_), .S(cds_globals.gnd_), .G(phi1), - .D(net11)); -Switch_NMOS_10 L0_MM5 ( .B(cds_globals.gnd_), .S(cds_globals.gnd_), .G(phi2), - .D(net5)); -Switch_NMOS_10 L0_MM4 ( .B(cds_globals.gnd_), .S(cds_globals.gnd_), .G(phi2), - .D(net4)); -Switch_NMOS_10 L0_MM3 ( .B(cds_globals.gnd_), .S(net5), .G(phi1), .D(net7)); -Switch_NMOS_10 L0_MM2 ( .B(cds_globals.gnd_), .S(Vinn), .G(phi1), .D(net4)); -Switch_NMOS_10 L0_MM1 ( .B(cds_globals.gnd_), .S(net23), .G(phi1), .D(net6)); -Switch_NMOS_10 L0_MM0 ( .B(cds_globals.gnd_), .S(net3), .G(phi1), .D(Vinp)); -//vpulse V7 ( .PLUS(phi2), .MINUS(cds_globals.gnd_)); -//vpulse V6 ( .PLUS(phi1), .MINUS(cds_globals.gnd_)); - -endmodule - - -// End HDL models -// Global nets module - -`celldefine -module cds_globals; - - -supply0 gnd_; - -supply1 vdd_; - - -endmodule -`endcelldefine diff --git a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_11_20/Circuit Description/Switched_capacitor_filter1.pdf b/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_11_20/Circuit Description/Switched_capacitor_filter1.pdf deleted file mode 100644 index 5f7d00cdab..0000000000 Binary files a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_11_20/Circuit Description/Switched_capacitor_filter1.pdf and /dev/null differ diff --git a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_11_20/Circuit Description/Switched_capacitor_filter_ota.pdf b/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_11_20/Circuit Description/Switched_capacitor_filter_ota.pdf deleted file mode 100644 index e1151dbcae..0000000000 Binary files a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_11_20/Circuit Description/Switched_capacitor_filter_ota.pdf and /dev/null differ diff --git a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_11_20/Constraints/switched_capacitor_filter.const b/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_11_20/Constraints/switched_capacitor_filter.const deleted file mode 100644 index 6167279df8..0000000000 --- a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_11_20/Constraints/switched_capacitor_filter.const +++ /dev/null @@ -1,22 +0,0 @@ -CritNet(net7, min) -CritNet(net23, min) -SymmNet({Voutn,CC2/MINUS,L0_MM7/D,I0/Voutn},{Voutp,CC0/MINUS,L0_MM8/S,I0/Voutp}) -SymmNet({net7,CC7/PLUS,CC2/PLUS,I0/Vinp,L0_MM3/D},{net23,CC5/PLUS,CC0/PLUS,I0/Vinn,L0_MM1/S}) -SymmNet({net11,L0_MM6/D,L0_MM7/S,CC1/MINUS},{net12,L0_MM11/S,L0_MM8/D,CC3/MINUS}) -SymmNet({net5,CC6/PLUS,CC1/PLUS,L0_MM5/D,L0_MM3/S},{net6,CC4/PLUS,CC3/PLUS,L0_MM9/S,L0_MM1/D}) -SymmNet({net4,CC6/MINUS,L0_MM2/D,L0_MM4/D},{net3,CC4/MINUS,L0_MM0/S,L0_MM10/S}) -SymmNet({Vinn,CC5/MINUS,L0_MM2/S},{Vinp,CC7/MINUS,L0_MM0/D}) -ShieldNet(Vinn) -ShieldNet(Vinp) -ShieldNet(net3) -ShieldNet(net4) -ShieldNet(net5) -ShieldNet(net6) -ShieldNet(net7) -ShieldNet(net23) -MatchBlock(L0_MM0,L0_MM2) -MatchBlock(L0_MM10,L0_MM4) -MatchBlock(L0_MM9,L0_MM5) -MatchBlock(L0_MM3,L0_MM1) -MatchBlock(L0_MM6,L0_MM11) -MatchBlock(L0_MM7,L0_MM8) diff --git a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_11_20/Constraints/telescopic_ota.const b/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_11_20/Constraints/telescopic_ota.const deleted file mode 100644 index 35f2a449e6..0000000000 --- a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_11_20/Constraints/telescopic_ota.const +++ /dev/null @@ -1,14 +0,0 @@ -SymmNet( {Vinp,L1_MM1_MM0/G1,Vinp} , {Vinn,L1_MM1_MM0/G2,Vinn}) -SymmNet( {net10,L1_MM1_MM0/D1,L1_MM10_MM2/S1} , {net11,L1_MM1_MM0/D2,L1_MM10_MM2/S2}) -SymmNet( {Voutn,L1_MM10_MM2/D1,L1_MM7_MM6/D1,Voutn} , {Voutp,L1_MM10_MM2/D2,L1_MM7_MM6/D2,Voutp}) -SymmNet( {net13,L1_MM7_MM6/S1,L1_MM8_MM9/D1}, {net12,L1_MM7_MM6/S2,L1_MM8_MM9/D2}) -CritNet(net6, mid) -CritNet(Vbiasn, mid) -CritNet(Vbiasp1, mid) -CritNet(Vbiasp2, mid) -CritNet(net10, min) -CritNet(net11, min) -CritNet(Voutn, min) -CritNet(Voutp, min) -CritNet(net13, min) -CritNet(net12, min) diff --git a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_11_20/LEF/sc.lef b/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_11_20/LEF/sc.lef deleted file mode 100644 index 7506420b57..0000000000 --- a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_11_20/LEF/sc.lef +++ /dev/null @@ -1,668 +0,0 @@ -VERSION 5.7 ; -BUSBITCHARS "[]" ; -DIVIDERCHAR "/" ; - -MACRO CMC_NMOS_25_1x10 - ORIGIN 0 0 ; - FOREIGN CMC_NMOS_25_1x10 0 0 ; - SIZE 2.16 BY 0.402 ; - PIN S2 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.256 0.32 2.012 0.338 ; - END - END S2 - PIN VSS - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER M2 ; - RECT 0 0 2.16 0.018 ; - END - END VSS - PIN VDD - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 0.384 2.16 0.402 ; - END - END VDD - PIN G - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER M2 ; - RECT 0.094 0.064 2.066 0.082 ; - END - END G - PIN D1 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.148 0.128 1.904 0.146 ; - END - END D1 - PIN D2 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.364 0.192 2.12 0.21 ; - END - END D2 - PIN S1 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.04 0.256 1.796 0.274 ; - END - END S1 - OBS - LAYER M1 ; - RECT 0 0 2.16 0.402 ; - END -END CMC_NMOS_25_1x10 - -MACRO CMC_PMOS_10_1x4 - ORIGIN 0 0 ; - FOREIGN CMC_PMOS_10_1x4 0 0 ; - SIZE 0.864 BY 0.402 ; - PIN S - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.04 0.32 0.716 0.338 ; - END - END S - PIN VDD - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER M2 ; - RECT 0 0.384 0.864 0.402 ; - END - END VDD - PIN VSS - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER M2 ; - RECT 0 0 0.864 0.018 ; - END - END VSS - PIN G - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.094 0.064 0.77 0.082 ; - END - END G - PIN D1 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.148 0.128 0.824 0.146 ; - END - END D1 - PIN D2 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.364 0.192 0.608 0.21 ; - END - END D2 - OBS - LAYER M1 ; - RECT 0 0 0.864 0.402 ; - END -END CMC_PMOS_10_1x4 - -MACRO CMC_PMOS_15_1x6 - ORIGIN 0 0 ; - FOREIGN CMC_PMOS_15_1x6 0 0 ; - SIZE 1.296 BY 0.402 ; - PIN S2 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.256 0.32 1.148 0.338 ; - END - END S2 - PIN VDD - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER M2 ; - RECT 0 0.384 1.296 0.402 ; - END - END VDD - PIN VSS - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER M2 ; - RECT 0 0 1.296 0.018 ; - END - END VSS - PIN G - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.094 0.064 1.202 0.082 ; - END - END G - PIN D1 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.148 0.128 1.04 0.146 ; - END - END D1 - PIN D2 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.364 0.192 1.256 0.21 ; - END - END D2 - PIN S1 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.04 0.256 0.932 0.274 ; - END - END S1 - OBS - LAYER M1 ; - RECT 0 0 1.296 0.402 ; - END -END CMC_PMOS_15_1x6 - -MACRO Cap_32f_1x1 - ORIGIN 0 0 ; - FOREIGN Cap_32f_1x1 0 0 ; - SIZE 4.024 BY 4.06 ; - PIN PLUS - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 4.037 4.024 4.055 ; - END - END PLUS - PIN MINUS - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 0.005 4.024 0.023 ; - END - END MINUS -END Cap_32f_1x1 - -MACRO Cap_50f_2x3 - ORIGIN 0 0 ; - FOREIGN Cap_50f_2x3 0 0 ; - SIZE 7.048 BY 4.7 ; - PIN PLUS - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 4.677 4.672 4.695 ; - END - END PLUS - PIN MINUS - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 0.005 7.048 0.023 ; - END - END MINUS -END Cap_50f_2x3 - -MACRO Cap_60f_2x3 - ORIGIN 0 0 ; - FOREIGN Cap_60f_2x3 0 0 ; - SIZE 7.048 BY 4.7 ; - PIN PLUS - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 4.677 7.048 4.695 ; - END - END PLUS - PIN MINUS - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 0.005 7.048 0.023 ; - END - END MINUS -END Cap_60f_2x3 - -MACRO DP_NMOS_75_3x10 - ORIGIN 0 0 ; - FOREIGN DP_NMOS_75_3x10 0 0 ; - SIZE 2.16 BY 1.298 ; - PIN S - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.04 1.152 2.012 1.17 ; - END - PORT - LAYER M2 ; - RECT 0.148 0.576 2.12 0.594 ; - END - PORT - LAYER M2 ; - RECT 0.04 0.256 2.012 0.274 ; - END - END S - PIN VSS - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER M2 ; - RECT 0 0.896 2.16 0.914 ; - END - PORT - LAYER M2 ; - RECT 0 0.832 2.16 0.85 ; - END - PORT - LAYER M2 ; - RECT 0 0 2.16 0.018 ; - END - END VSS - PIN VDD - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER M2 ; - RECT 0 1.28 2.16 1.298 ; - END - PORT - LAYER M2 ; - RECT 0 0.448 2.16 0.466 ; - END - PORT - LAYER M2 ; - RECT 0 0.384 2.16 0.402 ; - END - END VDD - PIN D1 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.148 1.024 1.904 1.042 ; - END - PORT - LAYER M2 ; - RECT 0.256 0.704 2.012 0.722 ; - END - PORT - LAYER M2 ; - RECT 0.148 0.128 1.904 0.146 ; - END - END D1 - PIN D2 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.364 1.088 2.12 1.106 ; - END - PORT - LAYER M2 ; - RECT 0.04 0.64 1.796 0.658 ; - END - PORT - LAYER M2 ; - RECT 0.364 0.192 2.12 0.21 ; - END - END D2 - PIN G1 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.094 0.96 1.85 0.978 ; - END - PORT - LAYER M2 ; - RECT 0.31 0.768 2.066 0.786 ; - END - PORT - LAYER M2 ; - RECT 0.094 0.064 1.85 0.082 ; - END - END G1 - PIN G2 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.31 1.216 2.066 1.234 ; - END - PORT - LAYER M2 ; - RECT 0.094 0.512 1.85 0.53 ; - END - PORT - LAYER M2 ; - RECT 0.31 0.32 2.066 0.338 ; - END - END G2 - OBS - LAYER M1 ; - RECT 0 0 2.16 0.402 ; - RECT 0 0.402 2.16 0.85 ; - RECT 0 0.85 2.16 1.298 ; - END -END DP_NMOS_75_3x10 - -MACRO DiodeConnected_NMOS_5_1x1 - ORIGIN 0 0 ; - FOREIGN DiodeConnected_NMOS_5_1x1 0 0 ; - SIZE 0.216 BY 0.402 ; - PIN VSS - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER M2 ; - RECT 0 0 0.216 0.018 ; - END - END VSS - PIN D - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.094 0.064 0.176 0.082 ; - END - END D - PIN S - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 0.128 0.068 0.146 ; - END - END S - PIN VDD - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER M2 ; - RECT 0 0.384 0.216 0.402 ; - END - END VDD -END DiodeConnected_NMOS_5_1x1 - -MACRO DiodeConnected_PMOS_10_1x2 - ORIGIN 0 0 ; - FOREIGN DiodeConnected_PMOS_10_1x2 0 0 ; - SIZE 0.432 BY 0.402 ; - PIN VSS - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER M2 ; - RECT 0 0 0.432 0.018 ; - END - END VSS - PIN D - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.094 0.064 0.392 0.082 ; - END - END D - PIN S - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 0.128 0.284 0.146 ; - END - END S - PIN VDD - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER M2 ; - RECT 0 0.384 0.432 0.402 ; - END - END VDD -END DiodeConnected_PMOS_10_1x2 - -END LIBRARY -VERSION 5.7 ; -BUSBITCHARS "[]" ; -DIVIDERCHAR "/" ; - -VIA M2_M1_0 - VIARULE M2_M1 ; - CUTSIZE 0.018 0.018 ; - LAYERS M1 V1 M2 ; - CUTSPACING 0.018 0.018 ; - ENCLOSURE 0 0.005 0.005 0 ; - ROWCOL 1 1 ; -END M2_M1_0 - -VIA M2_M1_1 - VIARULE M2_M1 ; - CUTSIZE 0.018 0.018 ; - LAYERS M1 V1 M2 ; - CUTSPACING 0.018 0.018 ; - ENCLOSURE 0 0.005 0.005 0 ; - ROWCOL 1 1 ; -END M2_M1_1 - -MACRO DiodeConnected_PMOS_20_1x4 - ORIGIN 0 0 ; - FOREIGN DiodeConnected_PMOS_20_1x4 0 0 ; - SIZE 0.864 BY 0.402 ; - PIN VSS - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER M2 ; - RECT 0 0 0.864 0.018 ; - END - END VSS - PIN D - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.094 0.064 0.824 0.082 ; - END - END D - PIN S - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 0.128 0.716 0.146 ; - END - END S - PIN VDD - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER M2 ; - RECT 0 0.384 0.864 0.402 ; - END - END VDD -END DiodeConnected_PMOS_20_1x4 - -MACRO SCM_NMOS_50_1x12 - ORIGIN 0 0 ; - FOREIGN SCM_NMOS_50_1x12 0 0 ; - SIZE 2.592 BY 0.402 ; - PIN D1 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 1.228 0.192 1.472 0.21 ; - END - PORT - LAYER M2 ; - RECT 1.444 0.192 1.472 0.21 ; - END - END D1 - PIN VSS - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER M2 ; - RECT 0 0 2.592 0.018 ; - END - END VSS - PIN S - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.04 0.256 2.444 0.274 ; - END - END S - PIN VDD - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER M2 ; - RECT 0 0.384 2.592 0.402 ; - END - END VDD - PIN D2 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.148 0.128 2.552 0.146 ; - END - END D2 - OBS - LAYER M1 ; - RECT 0 0 2.592 0.402 ; - END -END SCM_NMOS_50_1x12 - -MACRO Switch_NMOS_10_1x1 - ORIGIN 0 0 ; - FOREIGN Switch_NMOS_10_1x1 0 0 ; - SIZE 0.432 BY 0.402 ; - PIN S - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.04 0.064 0.284 0.082 ; - END - END S - PIN VSS - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER M2 ; - RECT 0 0 0.432 0.018 ; - END - END VSS - PIN D - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.148 0.192 0.392 0.21 ; - END - END D - PIN G - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.094 0.128 0.338 0.146 ; - END - END G - PIN VDD - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER M2 ; - RECT 0 0.384 0.432 0.402 ; - END - END VDD -END Switch_NMOS_10_1x1 - -MACRO Switch_PMOS_10_1x1 - ORIGIN 0 0 ; - FOREIGN Switch_PMOS_10_1x1 0 0 ; - SIZE 0.432 BY 0.402 ; - PIN S - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.04 0.192 0.284 0.21 ; - END - END S - PIN VSS - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER M2 ; - RECT 0 0 0.432 0.018 ; - END - END VSS - PIN D - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.148 0.064 0.392 0.082 ; - END - END D - PIN G - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.094 0.128 0.338 0.146 ; - END - END G - PIN VDD - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER M2 ; - RECT 0 0.384 0.432 0.402 ; - END - END VDD -END Switch_PMOS_10_1x1 - -END LIBRARY diff --git a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_11_20/README.md b/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_11_20/README.md deleted file mode 100644 index 8c7cb9dc1d..0000000000 --- a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_11_20/README.md +++ /dev/null @@ -1,17 +0,0 @@ -# INPUT for PnR tool -sc_block.v : block level netlist for switched capacitor -   This netlist contains two modules which need to be placed and routed hierarchicaly. -      1.switched_capacitor_filter : top level module , corresponding constraint are there in switched_capacitor_filter.const -      2.cascode_current_mirror_ota : sub module , corresponding constraint are there in cascode_current_mirror_ota.const - -sc.lef : lef file with block dimensions and pin locations - -# BLOCKS used (defined in lef, used in netlist) -1.CMC_NMOS_25_1 : common centroid transistors with gate connection -2.CMC_PMOS_10_1 : common centroid transistors with gate connection -3.CMC_PMOS_15_1 : common centroid transistors with gate connection -4.DP_NMOS_70_1 : Differential pair -5.SCM_NMOS_50 : current mirror -6.Cap_xxf: capacitance -7.Switch_NMOS_10 : transistor building block with 10 fins -8.Switch_PMOS_10 : transistor building block with 10 fins diff --git a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_11_20/Verilog Netlist/sc_block.v b/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_11_20/Verilog Netlist/sc_block.v deleted file mode 100644 index 2a6dc075c9..0000000000 --- a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_11_20/Verilog Netlist/sc_block.v +++ /dev/null @@ -1,95 +0,0 @@ -// Verilog HDL and netlist files of -// "pcell switched_capacitor_filter schematic" - -// Netlisted models - -// Library - pcell, Cell - cascode_current_mirror_ota, View - schematic -// LAST TIME SAVED: Aug 30 07:09:12 2018 -// NETLIST TIME: Nov 13 07:44:10 2018 -`timescale 1ns / 1ns - - -module telescopic_ota ( Voutn, Voutp, Vbiasn, Vbiasp1, Vbiasp2, Vinn, Vinp ); - -output Voutn, Voutp; - -input Vbiasn, Vbiasp1, Vbiasp2, Vinn, Vinp; - - -specify - specparam CDS_LIBNAME = "pcell"; - specparam CDS_CELLNAME = "telescopic_ota"; - specparam CDS_VIEWNAME = "schematic"; -endspecify - -SCM_NMOS_50_1x12 L1_MM4_MM3 ( .D1(net1), .D2(net6), .S(cds_globals.gnd_) ); -CMC_NMOS_25_1x10 L1_MM10_MM2 ( .D1(Voutn), .D2(Voutp), .G(Vbiasn), .S1(net10), .S2(net11) ); -CMC_PMOS_15_1x6 L1_MM7_MM6 ( .D1(Voutn), .D2(Voutp), .G(Vbiasp1), .S1(net13), .S2(net12) ); -CMC_PMOS_10_1x4 L1_MM8_MM9 ( .D1(net13), .D2(net12), .G(Vbiasp2), .S(cds_globals.vdd_) ); -DP_NMOS_75_3x10 L1_MM1_MM0 ( .D1(net10), .D2(net11), .G1(Vinp), .G2(Vinn), .S(net6) ); -//idc I3 ( .PLUS(cds_globals.vdd_), .MINUS(net1)); - -endmodule -// Library - pcell, Cell - switched_capacitor_filter, View - -//schematic -// LAST TIME SAVED: Aug 30 07:08:50 2018 -// NETLIST TIME: Nov 13 07:44:10 2018 -`timescale 1ns / 1ns - - -module switched_capacitor_filter ( Vinp, Vinn, Vbiasp2, Vbiasp1, Vbiasn, phi2, phi1 ); - - -specify - specparam CDS_LIBNAME = "pcell"; - specparam CDS_CELLNAME = "switched_capacitor_filter"; - specparam CDS_VIEWNAME = "schematic"; -endspecify - -//vdc V5 ( .PLUS(cds_globals.vdd_), .MINUS(cds_globals.gnd_)); -//vdc V4 ( .PLUS(Vinp), .MINUS(cds_globals.gnd_)); -//vdc V3 ( .PLUS(Vinn), .MINUS(cds_globals.gnd_)); -//vdc V2 ( .PLUS(Vbiasp2), .MINUS(cds_globals.gnd_)); -//vdc V1 ( .PLUS(Vbiasp1), .MINUS(cds_globals.gnd_)); -//vdc V0 ( .PLUS(Vbiasn), .MINUS(cds_globals.gnd_)); -telescopic_ota I0 ( .Voutn(Voutn), .Voutp(Voutp), .Vbiasn(Vbiasn), .Vbiasp1(Vbiasp1), .Vbiasp2(Vbiasp2), .Vinn(net23), .Vinp(net7)); -Cap_60f_2x3 CC7 ( .PLUS(net7), .MINUS(Vinp)); -Cap_60f_2x3 CC6 ( .PLUS(net5), .MINUS(net4)); -Cap_60f_2x3 CC5 ( .PLUS(net23), .MINUS(Vinn)); -Cap_60f_2x3 CC4 ( .PLUS(net6), .MINUS(net3)); -Cap_32f_1x1 CC3 ( .PLUS(net6), .MINUS(net12)); -Cap_32f_1x1 CC2 ( .PLUS(net7), .MINUS(Voutn)); -Cap_32f_1x1 CC1 ( .PLUS(net5), .MINUS(net11)); -Cap_32f_1x1 CC0 ( .PLUS(net23), .MINUS(Voutp)); -Switch_NMOS_10_1x1 L0_MM11 ( .S(net12), .G(phi1), .D(cds_globals.gnd_)); -Switch_NMOS_10_1x1 L0_MM10 ( .S(net3), .G(phi2), .D(cds_globals.gnd_)); -Switch_NMOS_10_1x1 L0_MM9 ( .S(net6), .G(phi2), .D(cds_globals.gnd_)); -Switch_NMOS_10_1x1 L0_MM8 ( .S(Voutp), .G(phi2), .D(net12)); -Switch_NMOS_10_1x1 L0_MM7 ( .S(net11), .G(phi2), .D(Voutn)); -Switch_NMOS_10_1x1 L0_MM6 ( .S(cds_globals.gnd_), .G(phi1), .D(net11)); -Switch_NMOS_10_1x1 L0_MM5 ( .S(cds_globals.gnd_), .G(phi2), .D(net5)); -Switch_NMOS_10_1x1 L0_MM4 ( .S(cds_globals.gnd_), .G(phi2), .D(net4)); -Switch_NMOS_10_1x1 L0_MM3 ( .S(net5), .G(phi1), .D(net7)); -Switch_NMOS_10_1x1 L0_MM2 ( .S(Vinn), .G(phi1), .D(net4)); -Switch_NMOS_10_1x1 L0_MM1 ( .S(net23), .G(phi1), .D(net6)); -Switch_NMOS_10_1x1 L0_MM0 ( .S(net3), .G(phi1), .D(Vinp)); -//vpulse V7 ( .PLUS(phi2), .MINUS(cds_globals.gnd_)); -//vpulse V6 ( .PLUS(phi1), .MINUS(cds_globals.gnd_)); - -endmodule - - -// End HDL models -// Global nets module - -`celldefine -module cds_globals; - - -supply0 gnd_; - -supply1 vdd_; - - -endmodule -`endcelldefine diff --git a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_11_20/__Previews/sc_block.vPreview b/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_11_20/__Previews/sc_block.vPreview deleted file mode 100644 index 727ba863a2..0000000000 --- a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_11_20/__Previews/sc_block.vPreview +++ /dev/null @@ -1,14 +0,0 @@ -[Preview] -LargeImageOriginalSize=2832000 -LargeImageWidth=708 -LargeImageHeight=1000 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A733D5831CE327F9734C2E3EE96A2FCB7CECABE4E2E29C61F3BA608C7B18BDD8B3FEE0751EF8E3BCDA764AD38468A7AAEECDE64AB6DF7675A3E3BB58B4D742B2A587BDFA89DE16F45C73F277A8C7ADD85D673BFAFB4EC67E5E440CE64C266BAFF7E43A31A9E481F03B77B55617EBDAD2990C2BFDC746471B7F823EA9E41D51CBEEA5874D360DAA872FE2F9EEA077F3BE910353F6FDA2F2EE46ADDB2B13495779F57AC0DF3B19DBCF79583D0CD6F2FB6C773D75EC3600BA1ED6FD0BA6BEEAA5876103BC4F52D748C6A65AB9114D7A187DB7752F69FF0E6C9C9C30BF0F380EFB1004F17A526FD8639FFD6E74D6F10F609C477E50DCD7B10DEFF974BFE051FCC36A2E82D8DDF79DCF61F4F072BE2A9ED7753D0C9FC21F2EFE41F8156479F49C5FBA4FAEC4B50FEC9048C7D8FA628205F515E9E5AD69C7ED861E862F6A692ECAA2734B46DDD4EBFC74AA0609A3874DF5E0E8E1298BC5EFB8F5B0FD7C33257C8661F530F45CE6D6D1F3357BF507AFF398FCC3B26DFBF987315764BE99A3FCF3ED82CB2F6D2CD72BB77F38DD13FFB0794E7410FF30985F5B177A38C3F5F07F6E778EEBA0FA875136D53F7CE53A9E43EA6DE73B8A7F18F3227AA975D4E71D35BF8DDA672FA30C8A36ECE41F567D1061F430FCF5D3B7626DEBD57A6D03FB1ADC7A58D7F5A6BE8AFE2EF5AB7A5D99667B55AF2B1BFFC8F9DB2BC7A3BC9798BE83F32727CCEF92BCEC23E3E9ECE7BD7DD50441BCD9DC989AE5F7EB8AC8CDAA6E1F9E5961EB16DE57DBDB3127CC1A3ECB3046419FE9F992809CF78979A232679C1C0BF02E3A65259A6BE3E32C7AB3753F1AB87453E473C3BE04D6CD7758738C31649B6B326BCA9EF3A8EBE1A9489CD57EA989FCA6B14F3FB5F530FCDBCA7D0EE3CE5ED6BEFFE29E8BB914C20E21ED67F20F3FFCA0A52B8EAA87A19BFAFB47B85ECAB33CB7EF487F7FDB5CD35EEBE1CFE0DF39841E36D503C6C6DCE347ACB46C312B5D70B6CBDF21B716C6B1B07A187AF1D6E5A3EB61AFFEE0771EAFB6ADCF751D1B9DE47AE97DA75E13114BFC66EA4FAB2EFDE0853E7FD834CF5E6F0B983FBCB2DA9C3FBCBAE2F86D518FB1D1319630CC1FAE602E40FA73A16D2DDE2FABC5CD40ED24B1C4F5702CCDE6D31976F3DD0B81EA4C9D3F7CE9F28878F78E77DD23972F719BA5ECB9A157279D7B82C9A641F5F0E56BD1B6395FDD24B9F5ACCD1FAF83F76C72EE11C03CEEC9D14B2CCEEF7BEAFC61713CDE573EB8734DDC1B135ABE46CC53C0FC613FDF01345C3C3275AC3610ED549F2F21DECDB5CEA9F721397FF8DEDD7F6BAB6FECB3AC25319FDD1E1F2C679F9C1B6C7AEE00B897E0794BD7C378F6C33BCF306D04E305D6D3C42F9CEAA9ED0882383966EECEF2FE6FFB61564A55AE758E968736AC8E11BFB9E73F77520763F999D3E759AD64CFE552F570FFBBEFF37B9DFDDE3712CDB253A7864479A059EE8C8FB306BF9756EB0D363E7EC7B9AF420F570BF3C20E753E865C1F9961AA2FD90FE3FCE18F5B6B89BA317FB813BDD6C362FE7029EB7C0E723D5EF58031FEF6F901A1E3E0C391DBE5EF30865BCB7C0CFB3819BA1D5D9B5E76FC8D8725487F38EC79F4F912BD20685B384A5C83D729B645D0F912C25F387DADA76541DB5D5A2FB35AD97E7EA8D4EA2C72DD9D6F1A79AE518E20ED47F7AB0601FA71BFD8F23FABEF078EC30640D5C3F09DAC2F596DDFE9465F055EFE61591F781ED0BF83FB91E9DCC7651F82205E4F30573099B163D9170A39D79A183F30DF60E2DCB9B6EDF07B85894B23723A44AE07FE3E8E8F7805F6FA97D6BA09F8A265BC05A973C59A975CD189ED695F6B9665F96F1B75B75F2D572A0B3B60BEE44E0E6350E738059F6F1558E4D3476DDAC08E2F116733568CD5F671ACCE732FE4B122B7473A7E57B25FADB1C7DBDBA17EE385FA7ED7942364716D5BEC5B9AB33A5E8F5F3DC0A7A3C62351EBC769937C1CEB3B7329B41E86D6D0E7FBF6A23F1CE63CB0C1A5E13167BE44B7F17A67E305FC928779F60DE2973C2EA44D83E861F80AEBD5C3C75F0943A154116DA894CBB2D24EFBFAB4296BB963FB411F181EB57CF5F0047F1630AEA7DBB0E3E820E682EADB3F0E1B88BEDF8C910D6003D3F79C3E74C43877EABC3B63BDE3D9FABD7F71FE865F647EE6EA89B71182200882200882200882200882200882200882F043CCA35062EC4844ACCB63C8538BF795584FA49FDF3497E0248E77D2C8F5D69E75F41A94F14DC3AB8DA83695EFA2ABE5B7C3C6726E0DE6301DB61F04B1DBEB0AE67EC9F95E275D168220088220DE7CBA317FF8753A8F1FB19512AB575E6FAD1706AC715D9CED9D4DBDE6861E202ED920E2811C5FDE6075FEF071E66BF69B1F3B1EDB72D6271F07DD9A3F1C169A3F4C108409DC1B764A4567FD50595BFB00FF1FD6C6610D9BF45FA8F99A25BB5A4CC64C33CF40A55C628D466B5D5A0EEB4CB04E299B71E259C963C97CCDF07FF9F94CE5DA2C353F712663FB8CE5B1D43CC1C2F7D4CCA5ECB59E0EF9E9B2723D9D88DBE31FEF4DA2AE1B51F3358B9C1CD91CCBE13A038EB3EAB1D46B933E5899AF59F579ED2A6BE0BA91AF59F7ADB97350DBFB6BD5F6DCAB3A5EF5A022F335EBE7116DC463CD6327C2AE5937E5A7F3EB0F7EE731B56DDB6E768E8A3CDF9EDFC577B2225E1EF2D395CA7BBE6B8E741A0DBB5D61CDE7675F3F33E66B36F549B15614D753CA3936459DA0BDA0AFA2CDD7957A2D37EBC5F643979A79CB5AF99AF57AC46FE0A3DD2B9644EC66713CAD0F99F2988973556A4ED9646C0CB94656E66BD6EF09BA4DF3D96447DBF9C50E3875211A5A0B9AF2D3E96DC1D486F5F812520FEBF5206D8D75C3325FB3ECFB7EF520D7554AE4BAE34E3640DC98E941C4120BF75CA0D76BD0F5746A1F424C0CF40BDC074CF5ED5AE32AFA979A2BDD6E0B59BE5F1D6BD47AA894DCED2E6C7C09946F64E89A2BBF2941106F17888BB33033EA8CDF253E3695965B312EFB6F5A2C1B8D88FBC7D465C41E76DF2B4DB19D323B3556598F0B4D88FC5BC59C1D2360315761E5CD05F1B95CA9B3D4C418EB46BE66E4213A7FFA4CC77CCD7EF1D6AE47F89853290B3B4073A4ACA5C0EF6E4DE55D7D9417CF1138CFFA528A7FEEAC21E5B1749B8A18AD8B6BCEF1D61617991EFBA2D7F99A61BBC29A6DD7C46A21D0F51C265F3362559537E79D3AB22666DADA9C1787893FDCD73FCED2E3FD81FB83E93C759FB65DE6DAA4B03627AE011AEE5FFB47D8C3E87BE27B37B96D2BE575F17993EF2B2D273A96D75A5A15B6411B1DBCB114281FC7D26ADE6EDBB89E728D7D30B726DA3DFAD0E0997F11FB703C2BB5E2D46BE47DCBEE0BAF9A9A428BFF626AF3389E357A496812915BC39A77F521DDD6208FEBDEB073A86DF2B245CE9F71F679E5A733D9F4A8F187918333AC16448CC63EC65C31CDF14CB0B68D786BF67329EC1AB9ED8E73ABC71F86DD2687461C1D3CB7D6EA5F87C94F87BE1ABB15776CAFE7A2F7B201FCE4C8471CF6B9C054AF6ABCB532D7ABDB6B8B1DFBAA577E3A5CCFC683B8A375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93FE6857ECA7BC93EC3FBB1D19B313659F1B794F04C7DD1AAA9118958F7450931595B3B993E7BEE0F20A7A5216F13D9DB8EE7BB6447A6D0FF1F50DBCECD77E92FF878A0F1F922F84E37E5B49F9DAE1F808D1D52561D3FBBEFB16AD421339B2794A7E0F5C0F17707A3439F3550A8460FEC31D0C9B5564B6D7E1F9E13E7C4B3B08AD6E21B5B1AC7CA36073095D2B6574A0E8B020ADD120B1BB87D0C63E0A1633A2DB7BD4AE83A417F239D923E53DFFFA3E469D86D0078F061DFA7E00ADF4A43FBDA47E1A5CDB213DAD41F9ECE1A839B1A5F877746D09BD5A03FE474F44DFA88703A84493486976514F6691D5E9D0679D369F425267A6DF7B28B87DC859A6FDB946B659CE64A27E6613D78BC982B0AB32663B5AA9D8ADFFDF54BCBF381C0EE752152A54BC3ECEF3E5E56044F00B9D4A95F42B3FE94513F42A0D9A1752C85ADD486D6DA2E0F0A368B7097EAF5360AEC28741AD8C6A3C8116E97DB75D2E152A6E0BB37C79A7DA81EDCEFFDFDE7775C9915C677E3F6F1F765FF4B4F6E8487B96323C5A8AABB39456E29128EE521C521CC3D1109C0166060380F0A6BDAFAAAEAE2EEFBDF7559959DE9BAEEE46636F447596411B34C610034E3C7C272A2323236F4445C43579E3C667637B9D27808C768FE4B22D2EA7851EDC46746307BA9FFE02498315D1678F90367B699EA55197EB246FC9907C414876D71B6F9380C09B42A358E27672359DBDD7AC742E7DF688749393D1D8CF68D47C7BE3A609087C1D383C8DEB73784E7C9F2BD7313A9AFBF6F4321AC50A7A33BEB097A1FB25E2367E9DE8D79B280749BE55A4B9FCD769C32CD87738569FEAD371557479ECC8D78F8329F066D1A9B531A8CA9354CD67F6F2D8F2321A113FD25B1B4868F428923C98DAB3A2938B22BEA5478AF4A8D49E8DEB4D69931DC3DAF9B15D99BD3C70EF213AF91CB2560BDA651991A70FD0CA651059DE44BF5A45646919CF4703A434BAC938EAB586285A8D9049868C3C5B40BF362EC7CA33DA2E1A6F4C07CC68B610DF3670DB7C2D5BE46D603E544CD7637E444DD2F10A460B722613C2CB5BDC7F22BB6F43726363520FA3B547B4C6963691331A781B72660FC2ABDBE836EA901D46744A0AC2CF16F1FC7088A4568F6A2406D9EFE3CFC5579726750D5A5D4E73A744B42F2DA25BAEF1EBBAD246339D40D11D42746181F727EBDF66A58D9A6FC63FC4E1473B9742D2E845336CE73457433E44573621E9375EEB3F17F866A1FAEA145F8A4158B4DBB9AD5971BB504A55B88DB959AA21B5B94C6332899C7E07CD721B8AC74C651DBCBCFA6C2D9146572E4EAE933A3DEAB104CA9124CA3E0F642ADB91F2683787783E6CF16F412FD335181CA1EA75410925B88F052BA7FA1DA9A93A56190F38391AEF1D613A60CEA0E7FE82698B07834683B7A118CAA3958EA22595B98D3E6BB6F37A990F22F3F9A8445234D6A7679AAAB466ADD47E8F6DD286D8F62E468D32F777AA45C3A7BE532FE07FF884E64909A5400047FD3AA2AB6B34F7C76BCC09BBFFE03146BD1E8A66F3A40DCC662F1B36D0C84B90BD01DE9FAC7F5FEE8B82DD09C9E945B7DE423D1CE43437681EE66C6E14CCCC97EAF8DC7E17F8FD83CD9983566392BE7C7FD4ED72DF84E7578C0DF93A18343B381EF4F8BAFDE2E4E895E59BB9222FD7CCBEDE7EC3D139711A078DB36DED962BAF55EF45759F07E6EF34AC5727E55FB70DAFFB3E81DF3F944A0BDAF535B8BD21180C260443612C90DCB1ABD1627D430BA7CF8B58C88D70228765CA77FB7CD06CAFE2D1C22ABC4E23EC24A7C4CE89072C20F05DC4BF7EF809FEE62FFE1CB7BE78868F3EFC353EF9F8067EF6B37FC6CFDFBF86FFF81FFE0BAE7DF82EAE7DF03ECFFFD5AFDEC1ADCF6EE1DAF51B78F668879EEFE04FBEF77D7CF6D17B6FBC1D0202DF56AC2CADBE32FFD6CD87947E799BA08080808080808080808080808080C077176DB93C97B2EF40B54810A3DE10CD6C16C3568BC72879F9B94626C7BF1BF66A2D1C1F4CBF4B315F88467CFA6D76D018FBFF95C351BE978A7D77ED976434F379BE7FA9911EFBF0B03D7DE37AB3787172CCBFCDF44B65D4A2D398146C9F7AE4D1430C5A6D54C344E3F080FB2174CA15748A45F4EB6DB4F339EE7BD04CC5F97EF561B582517F84E37E0F87ECBCAFE3432AD7E2B477A8CDB3DF3EABB1384F8B4ECF5C5B07B52606CD2EF7CF68150ABC0D8366137DEA9751A74379791C1D8CD0C8A64FEB89A157AD53FD320EE9BD9D62FEB46D19EECFD48847514F51FB0F073C65F7BAB52E8695C21B1F0F025F0D4734C6EBB1D0246579799315B2CB8BB8D60EC9AA455B91CF3CC7FC1ADA313F46830124E7D49FBC37A0B9639D9E7359CB8DC76B6ACF44E3AFC47D285A8522F2ECEC58A71D8A3F865AD88B8C7E0FDDDE31DAA93032B610AA590545F33EF2562B46F5F1FB956014E56C09FD4C88FB16947C3E94D31252BB16D468CC66B7B508DCBDCBCB327F0DB64F376732A0DBECA0AF145170B82139ECBC6DD1C56548A7A94A6BCE396E7FB7DEC1F3D1F46C6BB63779383C46746985FB5CB177B33833BEBB8F91351A500D7950F2323F8B080ECA19DE967AB1854A3285F4FA0AD2FB761C762B28986D7CAD28D81CFCDB799E68636933E4E6FE1305BBD8CBFF8780D9FDB987DD3672FB06E24F23C89E20727A3D8D7B378D83D1DC332CCE0AF3A53B1C0E90DC5899BB97339CF58DCD9A6C90EC66A4F7F6B98F404AA3458AC6BFBA6F97ADCF7DA9C0F7CEB63229943C612AB3836A3C836163CC1F193F53F7E74657D7717870C8E7544D6E21F6F0360EBA1DD413637E165F5BE7316514D7340E2DE381D55812BD4A0DFE7B4FD02E483C9DF4432873693FF1BDC7777F87B4D5CF796CF0C91364F60CC8EAB4C86A75D46F56B473599A4759E269CCBFCF49FCA9C363BF1C8D46D45F4BC4C70E685E8EFDFA0AD6F1F9B035EFD84FAB120EBFF1B120F0F5221A4FF158E297F9FEB0F8E3AC4C2A1E9DCBEF0D46E7E65F1532C99AECF96AE92C3F64C810AF63F7AF72FEEE79E7E17E95720C837E9FB77DD8BFDAF9AEAF5B37EFC3DED5CF8E1D5E507FBDD3473193FCC6687E1D5A5FA73E86B7FDFCDC00C9503E8F0F917C19F5193DC96E71608FC52E2779CB6CB523128D22E8F7C2130821119CC6DA6AF40F71427A402018819C9FC688F47943904906B3D2F39944183AE273AC9F98BF52ED34DED76074049D4E8330D5C952D5A7939DC31E4C15B1B7B58272A5827C22083DBF3FAEDB6677C24E34B3F8E92C2D105F8B848373EDB29B0C93DF917411D5621A26B31DD9741AFE4401B5B28284DC8492F0C3E974C2E572C0E3F7A3DD6EC0477CBA4E7A17A3999DF7ACD26C22BECDE4B2D595797E6CDCDF47B1D683C3A4878778BAC3A83FCD37507F85E1743B214B1222911032C413599CF732E95716D31E4F3321074249050D2986F56D3D8E86ED39DAD9FE328F2F8858240093C532A1FD70D084C51EC4E1D1B81F1B8D1ABDCB0D03C913BB0B0BFC5CF7CB68AE36DA9C1637B57F966616277B4FA3E3674398F677E1207D92B5C1E170C0E9BA02ADA763E4B2FE958A0558DD3E283446188DB3B4A9D79B2463BCE9F9F1DAF3C91F44305C40305380659FC969E37D3A3B3B46AC933CF3747113776E7F0E0FFD471E9707E15098C6FFBCBF5EC4EB80DDEE41599AEAF6A97C09A9881F1BDA5D28D9048FF77F48F9717F0801CF34261ECB3F181E4CCE0F18CFC500DEF9E03A1CBA65DCF9EC2646B5F4DCFD3DA303D77EFD2B4E1B4BC32FD5C9EBB518CE6F2BD5AD9E61E0081530A4BA97563610A136DDBC750FF1A00F4F484F1AF43A9377AA341BF6CED6A942EA90DC960E221B0AC16619EB4146830126BB1B36D2B16C4E1F6EDFBC85EDDD3D1E275E6D3B4B3B12C9D5F5036403D673EB66FDE6A6FEF57B5DD373164205BEFEB0731592212F8C3437D93C5820DA4DF43FE9579768AC162FA5D9EF0DA254ADA2532BCED1EC0BA588E63D54EB4D5AA7BCD01ACCBC0D2CF53A6D97D2CAA08E91CBFAB74932FFFD878F5152A43334AAD7768BE58DCF8FD7055B1FCBB2845AA385C24CDC07595190CD4B28C945548847F48623745A75D4996D6D461E8BC5D350A41CA2A4970CFB53BFE750248A616FBAB737731A93289ECC902E319601187F62B2213B0F402A66E768EAB018CBB91C46A477D4886F56CAD37796CB65FE5F33DA58DAE9927C93CFCEB5AB5E3F2B132652197E6641A154BDB4DCE03426CDCB34D76B17EF3F6E913E99884688EE3EE2D1F02BEB6EB53B68D42B3C3D1CB42EAD9BA154A9A3456350A589A156A952DFE72151DB4B17ECC37C55BDD96C0E2DE2C1B334E78A32F5718968EDA3764EBDAFAA73768C5CD607925C459378EA6C7D4CDE6B37FEF0F679AB7AD468D0BBB0CC588F0A5FA847157399D77AE7D7A93FB1F3AB5E5586ADE7D215CAA92816F23864B10413578B1576151AA67533DE7E8C44FCF2BA5F8766A5D547D2371FCBA32C5DAD0D97D1AE8E0D268BC7A3C12BD1F265C600A355CD67F38C5DF78787937D6EDF46780341544A65AE1B2D3C7D4072BA8F5FABF7AD1E2F0AD934AC246F68B49B70905C60B739E0A779E4B14DF9B12A87844846F67BE7E5B9B11CB28A21ADF1BFBDBB8C563134773F9FC9CFC973417F000F36CD70EF2E23E0F32364D7C1A8D7CEDD67B4329A585A6FB5B0B6B438D7AEE08CCDBE58AAA15D2B71792FE09BCA7B264F1247ED023FA38ABD5F3DC3CAE9F1A0D39ECA7B955A0B218F037AFD58C748BC3416C3E13097F764D2153C3617951D8F61C3DE1ED5EDE5F598CC56ECEC1AE1F4FAE6CED9CAE414D23BB3F4FC31E22E03D285D2E41C1F95F611E9A76E921BF774DB139A7776CDE8D765EC6CEDC07B4A3F6F9341C7F52176DE56229944605F4FBA0BD1E570F1F3EE2E6B039351B6B7E8FEA8C3691F9FF5554088FE833DDDDEE40CB0C97F47FFC3BE41CFFB93C9AC5EFADFBD5E0FA7C9437A9C7A46D884368B1D5192872324D3309DFBD9CA16C9467944A9FEFBF757D12C6790764FEDB12AADB3D783C313986674E96F1B980CE4B19BB0BCA6C1C3474FA88FFCFC5ABD6FB23BE8BFB4E0D1832778F0E021AC36D22DED5618F68D48C5A67C899DF7C4529BD589A0CF3B973F3C3C46329546AF55C5EDA55DAE0FB17B4CDEDBA539AA9EFFA43E63B47AF074690B9BCB4FA0DBD4C061D662DF38BDAFD2FAF0EE7D9EFA683DB31AF7E7DA65359DB5D9EB76F711233DD9951CEF99559A03A4826E7E465583E41BF50CABD5CD6DAE3FA96DDAD6EDA3900AC362325ED88F994A0FB6DD6D64E2716C6D8EF56833D1C064A72CE5D59B1D24224118685E31FD89C9795EAF9D9F0169339B496749A3DF902EACDF6677214ECF339A431E3BE9BA7BD06834587EB2885EBB4EF367AC7384A3297E76033B6F4B2199DDEF72A241EFDED41A71D096E1B45CDC06A93E80C5C0FAF180D35EABB7E0A7B5A144F2F753FAEFD533C0D4F2B9A244BA929F9F01C6E693AC9468ADA86379610D32C926EA19611AEDD6E91CCE703B0FFB3D3A3AE1BC389B4A2046F2B4756F172E5F84E6D3745D9DA595F127F53A36F38DFF6DC1DB2EEF0908BC09D4995CE3F6C04B729E3F1C25B939CFAFD5FBA1581CBD4E8B640A0FDC1E1FCDB33892347FAC0E37CA3332B6939E61B66566379766CE5662F90AC98F8140008D8A047F34817A652C4F32FE64A2353F9548F254B59747A84C222FC36EDCE5327ABB5280549CAEDD5E5F90D3CAF8244BCB24A7B07572B65DB3FC49B5973B997D562EF26B667356F9532094C2F1419BD6F6389AB51A42B4FEB136FAA82D555A4F8324A324E363FEC4748FA78F1ECEBD8BD99E4B8D1EE7E3E1481C3ED7F8FBACF9948654C8875AAD497D10247E24C14672B2426B3D932D0D2403E6688D56F9D393C5F5736DD0915812B974628E66C6F7F7F4066E2363FDD722DDDEEB72214C7CD66DB1402239756F71118D7A9DDF67DF2BD81A7F511BD8D993418F9F78679BFACF38694380D6CC20D12A51DF4985CC8476465B2EEE47362321938AC1621EDBFC5E6E8389E40DD60636665AD49F06A315328D115F388536C9AC6C8D8C46C30805FD18D0FA6D7578D1EF7638CD59360E6CB639FEC4C0AE932137E4E610B9E8B7677FB8EFF41C24BBD38BCFAF7F34B99E8C4B92FF835E37D6B7F6F0E4F17D1A2BA40F900E100A85918E4FF9AE2A23FBFD612442E1B97CF6BF7F7EFB1E97F7EEDCBB8F7C2E3D77BFDD6C9FD19F3EB87E97EB4F4BCF16B87C689BF1C551696534B1745BABA73E9F97EF66F527154C7F0A798267F427BBDD092FE91C7A9261D9F9BD1692BF6C54DF938505F448EEBB4F326534E43D23CFCF42B597C7BD41D84FCF34603A48342DC145F327148E619FF4181B8D7326BBAA76F3C5A535B8ACD689FE745EDDCC5EEE728CEDE5B334CB24832E3C5946D8EF99C8548F9F2E201D09E131C95C3E5AC3B69F3CA07938FDDE70591B3A834358997E74D89F94676D58DBD1C1A0DDC6EAFA0EB41BAB13DA55BD89C9236683017A5BE8C2BAF9DA4CE382C92CD99C4C3A6386D7CD74EB8724B36AF6CCB8F7F9274845C2BCDF99CD41A5C166F79E4BBB7ABDB172FEFED737814AADC1F5253BE9D176A787DBA867F527C69FD8DA6CA77E66BA68349EE46B77281A9DD39FBCA776241BD5C3D6C997F35544A3696E2365BF197F723BAC5C7F0A87A66B4C20924280CA592D66649369A4A2EC7BEECE743E9DD26AA3F58BA5F55697748B79993A76CE59528C3FC9C502A2F9317F1C920C9F4DC669ADF593CEEE3E535E2ECFDB8A13D18BFD3E187FF210BF64766687CD3AA1C11708C31F8A9CF9E6FF72DDC94496C6D0C5F16ED8F708A63F319AA3E108A7D9E97451DF8C69BAC85ECE30DBBFD94B7C57F87C3259D1EBB748D7095FD88F2AEDAC1F078D3C2449412CE2BFB47FF858A2FB52368300D19FCFA451ACB4D1AD9F95EDD5FA19CD9DDE88747607E747B3B4B3EB56F9EDF11F7E13FAD3A43F4FF5A857E94957F18D527155FB79B77EB5789AAAFD96C94EBDC6F97107BF0C0DC6FDB14C533C9599AF623FBF2ACDE7D1FECDD8FEAF46FB97694395D6AD836EEDCCF5B7C58E1E217EC3F4A59D9D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- diff --git a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_12_06/Circuit Description/Switched_capacitor_filter1.pdf b/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_12_06/Circuit Description/Switched_capacitor_filter1.pdf deleted file mode 100644 index 5f7d00cdab..0000000000 Binary files a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_12_06/Circuit Description/Switched_capacitor_filter1.pdf and /dev/null differ diff --git a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_12_06/Circuit Description/Switched_capacitor_filter_ota.pdf b/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_12_06/Circuit Description/Switched_capacitor_filter_ota.pdf deleted file mode 100644 index e1151dbcae..0000000000 Binary files a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_12_06/Circuit Description/Switched_capacitor_filter_ota.pdf and /dev/null differ diff --git a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_12_06/Constraints/sc.const b/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_12_06/Constraints/sc.const deleted file mode 100644 index d05e31a8bb..0000000000 --- a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_12_06/Constraints/sc.const +++ /dev/null @@ -1,38 +0,0 @@ -CritNet(Vinp_ota, min) -CritNet(Vinn_ota, min) -SymmNet({Voutn,CC2/MINUS,L0_MM7/D,I0/Voutn},{Voutp,CC0/MINUS,L0_MM8/S,I0/Voutp}) -SymmNet({Vinp_ota,CC7/PLUS,CC2/PLUS,I0/Vinp,L0_MM3/D},{Vinn_ota,CC5/PLUS,CC0/PLUS,I0/Vinn,L0_MM1/S}) -SymmNet({net11,L0_MM6/D,L0_MM7/S,CC1/MINUS},{net12,L0_MM11/S,L0_MM8/D,CC3/MINUS}) -SymmNet({net5,CC6/PLUS,CC1/PLUS,L0_MM5/D,L0_MM3/S},{net6,CC4/PLUS,CC3/PLUS,L0_MM9/S,L0_MM1/D}) -SymmNet({net4,CC6/MINUS,L0_MM2/D,L0_MM4/D},{net3,CC4/MINUS,L0_MM0/S,L0_MM10/S}) -SymmNet({Vinn,CC5/MINUS,L0_MM2/S},{Vinp,CC7/MINUS,L0_MM0/D}) -ShieldNet(Vinn) -ShieldNet(Vinp) -ShieldNet(net3) -ShieldNet(net4) -ShieldNet(net5) -ShieldNet(net6) -ShieldNet(Vinp_ota) -ShieldNet(Vinn_ota) -MatchBlock(CC0,CC4) -MatchBlock(CC0,CC3) -MatchBlock(CC4,CC5) -MatchBlock(CC3,CC8) -MatchBlock(CC2,CC1) -MatchBlock(CC1,CC9) -MatchBlock(CC2,CC6) -MatchBlock(CC6,CC7) -SymmNet( {Vinp_ota,L1_MM1_MM0/G1,Vinp_ota} , {Vinn_ota,L1_MM1_MM0/G2,Vinn_ota}) -SymmNet( {net10_ota,L1_MM1_MM0/D1,L1_MM10_MM2/S1} , {net11_ota,L1_MM1_MM0/D2,L1_MM10_MM2/S2}) -SymmNet( {Voutn,L1_MM10_MM2/D1,L1_MM7_MM6/D1,Voutn} , {Voutp,L1_MM10_MM2/D2,L1_MM7_MM6/D2,Voutp}) -SymmNet( {net13_ota,L1_MM7_MM6/S1,L1_MM8_MM9/D1}, {net12_ota,L1_MM7_MM6/S2,L1_MM8_MM9/D2}) -CritNet(net6_ota, mid) -CritNet(Vbiasn_ota, mid) -CritNet(Vbiasp1_ota, mid) -CritNet(Vbiasp2_ota, mid) -CritNet(net10_ota, min) -CritNet(net11_ota, min) -CritNet(Voutn, min) -CritNet(Voutp, min) -CritNet(net13_ota, min) -CritNet(net12_ota, min) diff --git a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_12_06/LEF/sc.lef b/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_12_06/LEF/sc.lef deleted file mode 100644 index 7506420b57..0000000000 --- a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_12_06/LEF/sc.lef +++ /dev/null @@ -1,668 +0,0 @@ -VERSION 5.7 ; -BUSBITCHARS "[]" ; -DIVIDERCHAR "/" ; - -MACRO CMC_NMOS_25_1x10 - ORIGIN 0 0 ; - FOREIGN CMC_NMOS_25_1x10 0 0 ; - SIZE 2.16 BY 0.402 ; - PIN S2 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.256 0.32 2.012 0.338 ; - END - END S2 - PIN VSS - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER M2 ; - RECT 0 0 2.16 0.018 ; - END - END VSS - PIN VDD - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 0.384 2.16 0.402 ; - END - END VDD - PIN G - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER M2 ; - RECT 0.094 0.064 2.066 0.082 ; - END - END G - PIN D1 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.148 0.128 1.904 0.146 ; - END - END D1 - PIN D2 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.364 0.192 2.12 0.21 ; - END - END D2 - PIN S1 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.04 0.256 1.796 0.274 ; - END - END S1 - OBS - LAYER M1 ; - RECT 0 0 2.16 0.402 ; - END -END CMC_NMOS_25_1x10 - -MACRO CMC_PMOS_10_1x4 - ORIGIN 0 0 ; - FOREIGN CMC_PMOS_10_1x4 0 0 ; - SIZE 0.864 BY 0.402 ; - PIN S - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.04 0.32 0.716 0.338 ; - END - END S - PIN VDD - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER M2 ; - RECT 0 0.384 0.864 0.402 ; - END - END VDD - PIN VSS - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER M2 ; - RECT 0 0 0.864 0.018 ; - END - END VSS - PIN G - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.094 0.064 0.77 0.082 ; - END - END G - PIN D1 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.148 0.128 0.824 0.146 ; - END - END D1 - PIN D2 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.364 0.192 0.608 0.21 ; - END - END D2 - OBS - LAYER M1 ; - RECT 0 0 0.864 0.402 ; - END -END CMC_PMOS_10_1x4 - -MACRO CMC_PMOS_15_1x6 - ORIGIN 0 0 ; - FOREIGN CMC_PMOS_15_1x6 0 0 ; - SIZE 1.296 BY 0.402 ; - PIN S2 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.256 0.32 1.148 0.338 ; - END - END S2 - PIN VDD - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER M2 ; - RECT 0 0.384 1.296 0.402 ; - END - END VDD - PIN VSS - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER M2 ; - RECT 0 0 1.296 0.018 ; - END - END VSS - PIN G - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.094 0.064 1.202 0.082 ; - END - END G - PIN D1 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.148 0.128 1.04 0.146 ; - END - END D1 - PIN D2 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.364 0.192 1.256 0.21 ; - END - END D2 - PIN S1 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.04 0.256 0.932 0.274 ; - END - END S1 - OBS - LAYER M1 ; - RECT 0 0 1.296 0.402 ; - END -END CMC_PMOS_15_1x6 - -MACRO Cap_32f_1x1 - ORIGIN 0 0 ; - FOREIGN Cap_32f_1x1 0 0 ; - SIZE 4.024 BY 4.06 ; - PIN PLUS - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 4.037 4.024 4.055 ; - END - END PLUS - PIN MINUS - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 0.005 4.024 0.023 ; - END - END MINUS -END Cap_32f_1x1 - -MACRO Cap_50f_2x3 - ORIGIN 0 0 ; - FOREIGN Cap_50f_2x3 0 0 ; - SIZE 7.048 BY 4.7 ; - PIN PLUS - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 4.677 4.672 4.695 ; - END - END PLUS - PIN MINUS - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 0.005 7.048 0.023 ; - END - END MINUS -END Cap_50f_2x3 - -MACRO Cap_60f_2x3 - ORIGIN 0 0 ; - FOREIGN Cap_60f_2x3 0 0 ; - SIZE 7.048 BY 4.7 ; - PIN PLUS - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 4.677 7.048 4.695 ; - END - END PLUS - PIN MINUS - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 0.005 7.048 0.023 ; - END - END MINUS -END Cap_60f_2x3 - -MACRO DP_NMOS_75_3x10 - ORIGIN 0 0 ; - FOREIGN DP_NMOS_75_3x10 0 0 ; - SIZE 2.16 BY 1.298 ; - PIN S - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.04 1.152 2.012 1.17 ; - END - PORT - LAYER M2 ; - RECT 0.148 0.576 2.12 0.594 ; - END - PORT - LAYER M2 ; - RECT 0.04 0.256 2.012 0.274 ; - END - END S - PIN VSS - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER M2 ; - RECT 0 0.896 2.16 0.914 ; - END - PORT - LAYER M2 ; - RECT 0 0.832 2.16 0.85 ; - END - PORT - LAYER M2 ; - RECT 0 0 2.16 0.018 ; - END - END VSS - PIN VDD - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER M2 ; - RECT 0 1.28 2.16 1.298 ; - END - PORT - LAYER M2 ; - RECT 0 0.448 2.16 0.466 ; - END - PORT - LAYER M2 ; - RECT 0 0.384 2.16 0.402 ; - END - END VDD - PIN D1 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.148 1.024 1.904 1.042 ; - END - PORT - LAYER M2 ; - RECT 0.256 0.704 2.012 0.722 ; - END - PORT - LAYER M2 ; - RECT 0.148 0.128 1.904 0.146 ; - END - END D1 - PIN D2 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.364 1.088 2.12 1.106 ; - END - PORT - LAYER M2 ; - RECT 0.04 0.64 1.796 0.658 ; - END - PORT - LAYER M2 ; - RECT 0.364 0.192 2.12 0.21 ; - END - END D2 - PIN G1 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.094 0.96 1.85 0.978 ; - END - PORT - LAYER M2 ; - RECT 0.31 0.768 2.066 0.786 ; - END - PORT - LAYER M2 ; - RECT 0.094 0.064 1.85 0.082 ; - END - END G1 - PIN G2 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.31 1.216 2.066 1.234 ; - END - PORT - LAYER M2 ; - RECT 0.094 0.512 1.85 0.53 ; - END - PORT - LAYER M2 ; - RECT 0.31 0.32 2.066 0.338 ; - END - END G2 - OBS - LAYER M1 ; - RECT 0 0 2.16 0.402 ; - RECT 0 0.402 2.16 0.85 ; - RECT 0 0.85 2.16 1.298 ; - END -END DP_NMOS_75_3x10 - -MACRO DiodeConnected_NMOS_5_1x1 - ORIGIN 0 0 ; - FOREIGN DiodeConnected_NMOS_5_1x1 0 0 ; - SIZE 0.216 BY 0.402 ; - PIN VSS - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER M2 ; - RECT 0 0 0.216 0.018 ; - END - END VSS - PIN D - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.094 0.064 0.176 0.082 ; - END - END D - PIN S - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 0.128 0.068 0.146 ; - END - END S - PIN VDD - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER M2 ; - RECT 0 0.384 0.216 0.402 ; - END - END VDD -END DiodeConnected_NMOS_5_1x1 - -MACRO DiodeConnected_PMOS_10_1x2 - ORIGIN 0 0 ; - FOREIGN DiodeConnected_PMOS_10_1x2 0 0 ; - SIZE 0.432 BY 0.402 ; - PIN VSS - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER M2 ; - RECT 0 0 0.432 0.018 ; - END - END VSS - PIN D - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.094 0.064 0.392 0.082 ; - END - END D - PIN S - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 0.128 0.284 0.146 ; - END - END S - PIN VDD - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER M2 ; - RECT 0 0.384 0.432 0.402 ; - END - END VDD -END DiodeConnected_PMOS_10_1x2 - -END LIBRARY -VERSION 5.7 ; -BUSBITCHARS "[]" ; -DIVIDERCHAR "/" ; - -VIA M2_M1_0 - VIARULE M2_M1 ; - CUTSIZE 0.018 0.018 ; - LAYERS M1 V1 M2 ; - CUTSPACING 0.018 0.018 ; - ENCLOSURE 0 0.005 0.005 0 ; - ROWCOL 1 1 ; -END M2_M1_0 - -VIA M2_M1_1 - VIARULE M2_M1 ; - CUTSIZE 0.018 0.018 ; - LAYERS M1 V1 M2 ; - CUTSPACING 0.018 0.018 ; - ENCLOSURE 0 0.005 0.005 0 ; - ROWCOL 1 1 ; -END M2_M1_1 - -MACRO DiodeConnected_PMOS_20_1x4 - ORIGIN 0 0 ; - FOREIGN DiodeConnected_PMOS_20_1x4 0 0 ; - SIZE 0.864 BY 0.402 ; - PIN VSS - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER M2 ; - RECT 0 0 0.864 0.018 ; - END - END VSS - PIN D - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.094 0.064 0.824 0.082 ; - END - END D - PIN S - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 0.128 0.716 0.146 ; - END - END S - PIN VDD - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER M2 ; - RECT 0 0.384 0.864 0.402 ; - END - END VDD -END DiodeConnected_PMOS_20_1x4 - -MACRO SCM_NMOS_50_1x12 - ORIGIN 0 0 ; - FOREIGN SCM_NMOS_50_1x12 0 0 ; - SIZE 2.592 BY 0.402 ; - PIN D1 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 1.228 0.192 1.472 0.21 ; - END - PORT - LAYER M2 ; - RECT 1.444 0.192 1.472 0.21 ; - END - END D1 - PIN VSS - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER M2 ; - RECT 0 0 2.592 0.018 ; - END - END VSS - PIN S - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.04 0.256 2.444 0.274 ; - END - END S - PIN VDD - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER M2 ; - RECT 0 0.384 2.592 0.402 ; - END - END VDD - PIN D2 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.148 0.128 2.552 0.146 ; - END - END D2 - OBS - LAYER M1 ; - RECT 0 0 2.592 0.402 ; - END -END SCM_NMOS_50_1x12 - -MACRO Switch_NMOS_10_1x1 - ORIGIN 0 0 ; - FOREIGN Switch_NMOS_10_1x1 0 0 ; - SIZE 0.432 BY 0.402 ; - PIN S - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.04 0.064 0.284 0.082 ; - END - END S - PIN VSS - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER M2 ; - RECT 0 0 0.432 0.018 ; - END - END VSS - PIN D - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.148 0.192 0.392 0.21 ; - END - END D - PIN G - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.094 0.128 0.338 0.146 ; - END - END G - PIN VDD - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER M2 ; - RECT 0 0.384 0.432 0.402 ; - END - END VDD -END Switch_NMOS_10_1x1 - -MACRO Switch_PMOS_10_1x1 - ORIGIN 0 0 ; - FOREIGN Switch_PMOS_10_1x1 0 0 ; - SIZE 0.432 BY 0.402 ; - PIN S - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.04 0.192 0.284 0.21 ; - END - END S - PIN VSS - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER M2 ; - RECT 0 0 0.432 0.018 ; - END - END VSS - PIN D - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.148 0.064 0.392 0.082 ; - END - END D - PIN G - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.094 0.128 0.338 0.146 ; - END - END G - PIN VDD - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER M2 ; - RECT 0 0.384 0.432 0.402 ; - END - END VDD -END Switch_PMOS_10_1x1 - -END LIBRARY diff --git a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_12_06/README.md b/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_12_06/README.md deleted file mode 100644 index 8c7cb9dc1d..0000000000 --- a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_12_06/README.md +++ /dev/null @@ -1,17 +0,0 @@ -# INPUT for PnR tool -sc_block.v : block level netlist for switched capacitor -   This netlist contains two modules which need to be placed and routed hierarchicaly. -      1.switched_capacitor_filter : top level module , corresponding constraint are there in switched_capacitor_filter.const -      2.cascode_current_mirror_ota : sub module , corresponding constraint are there in cascode_current_mirror_ota.const - -sc.lef : lef file with block dimensions and pin locations - -# BLOCKS used (defined in lef, used in netlist) -1.CMC_NMOS_25_1 : common centroid transistors with gate connection -2.CMC_PMOS_10_1 : common centroid transistors with gate connection -3.CMC_PMOS_15_1 : common centroid transistors with gate connection -4.DP_NMOS_70_1 : Differential pair -5.SCM_NMOS_50 : current mirror -6.Cap_xxf: capacitance -7.Switch_NMOS_10 : transistor building block with 10 fins -8.Switch_PMOS_10 : transistor building block with 10 fins diff --git a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_12_06/Verilog Netlist/sc.v b/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_12_06/Verilog Netlist/sc.v deleted file mode 100644 index dc064a6b04..0000000000 --- a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_12_06/Verilog Netlist/sc.v +++ /dev/null @@ -1,63 +0,0 @@ -// Verilog HDL and netlist files of -// "pcell switched_capacitor_filter schematic" - -// Netlisted models - -// Library - pcell, Cell - switched_capacitor_filter, View - -//schematic -// LAST TIME SAVED: Aug 30 07:08:50 2018 -// NETLIST TIME: Nov 13 07:44:10 2018 -`timescale 1ns / 1ns - - -module switched_capacitor_filter ( Vinp, Vinn, Vbiasp2_ota, Vbiasp1_ota, Vbiasn_ota, phi2, phi1, agnd ); - - -specify - specparam CDS_LIBNAME = "pcell"; - specparam CDS_CELLNAME = "switched_capacitor_filter"; - specparam CDS_VIEWNAME = "schematic"; -endspecify - -//vdc V5 ( .PLUS(cds_globals.vdd_), .MINUS(cds_globals.gnd_)); -//vdc V4 ( .PLUS(Vinp), .MINUS(cds_globals.gnd_)); -//vdc V3 ( .PLUS(Vinn), .MINUS(cds_globals.gnd_)); -//vdc V2 ( .PLUS(Vbiasp2), .MINUS(cds_globals.gnd_)); -//vdc V1 ( .PLUS(Vbiasp1), .MINUS(cds_globals.gnd_)); -//vdc V0 ( .PLUS(Vbiasn), .MINUS(cds_globals.gnd_)); -SCM_NMOS_50_1x12 L1_MM4_MM3 ( .D1(net1_ota), .D2(net6_ota), .S(GND) ); -CMC_NMOS_25_1x10 L1_MM10_MM2 ( .D1(Voutn), .D2(Voutp), .G(Vbiasn_ota), .S1(net10_ota), .S2(net11_ota) ); -CMC_PMOS_15_1x6 L1_MM7_MM6 ( .D1(Voutn), .D2(Voutp), .G(Vbiasp1_ota), .S1(net13_ota), .S2(net12_ota) ); -CMC_PMOS_10_1x4 L1_MM8_MM9 ( .D1(net13_ota), .D2(net12_ota), .G(Vbiasp2_ota), .S(VDD) ); -DP_NMOS_75_3x10 L1_MM1_MM0 ( .D1(net10_ota), .D2(net11_ota), .G1(Vinp_ota), .G2(Vinn_ota), .S(net6_ota) ); -//cascode_current_mirror_ota I0 ( .Voutn(Voutn), .Voutp(Voutp), .Vbiasn(Vbiasn), .Vbiasp1(Vbiasp1), .Vbiasp2(Vbiasp2), .Vinn(net23), .Vinp(net7)); -Cap_60f_2x3 CC8 ( .PLUS(Voutp), .MINUS(GND)); -Cap_60f_2x3 CC9 ( .PLUS(Voutn), .MINUS(GND)); -Cap_60f_2x3 CC2 ( .PLUS(Vinp_ota), .MINUS(Vinp)); -Cap_60f_2x3 CC6 ( .PLUS(net5), .MINUS(net4)); -Cap_60f_2x3 CC0 ( .PLUS(Vinn_ota), .MINUS(Vinn)); -Cap_60f_2x3 CC4 ( .PLUS(net6), .MINUS(net3)); -Cap_32f_1x1 CC3 ( .PLUS(net6), .MINUS(net12)); -Cap_32f_1x1 CC7 ( .PLUS(Vinp_ota), .MINUS(Voutn)); -Cap_32f_1x1 CC1 ( .PLUS(net5), .MINUS(net11)); -Cap_32f_1x1 CC5 ( .PLUS(Vinn_ota), .MINUS(Voutp)); -Switch_NMOS_10_1x1 L0_MM11 ( .S(net12), .G(phi1), .D(agnd)); -Switch_NMOS_10_1x1 L0_MM10 ( .S(net3), .G(phi2), .D(agnd)); -Switch_NMOS_10_1x1 L0_MM9 ( .S(net6), .G(phi2), .D(agnd)); -Switch_NMOS_10_1x1 L0_MM8 ( .S(Voutp), .G(phi2), .D(net12)); -Switch_NMOS_10_1x1 L0_MM7 ( .S(net11), .G(phi2), .D(Voutn)); -Switch_NMOS_10_1x1 L0_MM6 ( .S(agnd), .G(phi1), .D(net11)); -Switch_NMOS_10_1x1 L0_MM5 ( .S(agnd), .G(phi2), .D(net5)); -Switch_NMOS_10_1x1 L0_MM4 ( .S(agnd), .G(phi2), .D(net4)); -Switch_NMOS_10_1x1 L0_MM3 ( .S(net5), .G(phi1), .D(Vinp_ota)); -Switch_NMOS_10_1x1 L0_MM2 ( .S(Vinn), .G(phi1), .D(net4)); -Switch_NMOS_10_1x1 L0_MM1 ( .S(Vinn_ota), .G(phi1), .D(net6)); -Switch_NMOS_10_1x1 L0_MM0 ( .S(net3), .G(phi1), .D(Vinp)); -//vpulse V7 ( .PLUS(phi2), .MINUS(cds_globals.gnd_)); -//vpulse V6 ( .PLUS(phi1), .MINUS(cds_globals.gnd_)); - -endmodule - -`endcelldefine -// End HDL models -// Global nets module diff --git a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_12_10/Circuit Description/Switched_capacitor_filter1.pdf b/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_12_10/Circuit Description/Switched_capacitor_filter1.pdf deleted file mode 100644 index 5f7d00cdab..0000000000 Binary files a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_12_10/Circuit Description/Switched_capacitor_filter1.pdf and /dev/null differ diff --git a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_12_10/Circuit Description/Switched_capacitor_filter_ota.pdf b/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_12_10/Circuit Description/Switched_capacitor_filter_ota.pdf deleted file mode 100644 index e1151dbcae..0000000000 Binary files a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_12_10/Circuit Description/Switched_capacitor_filter_ota.pdf and /dev/null differ diff --git a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_12_10/Constraints/common_mode_feedback.const b/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_12_10/Constraints/common_mode_feedback.const deleted file mode 100644 index bc5de31cdb..0000000000 --- a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_12_10/Constraints/common_mode_feedback.const +++ /dev/null @@ -1,4 +0,0 @@ -MatchBlock(CC10, CC11) -SymmNet( {Va,L0_MM0/S,Va} , {Vb,L0_MM2/D,Vb}) -SymmNet( {net1,L0_MM0/D,L0_MM1/D,CC10/PLUS} , {net2,L0_MM2/S,L0_MM3/S,CC11/MINUS}) - diff --git a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_12_10/Constraints/non_overlapping_clock_generator.const b/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_12_10/Constraints/non_overlapping_clock_generator.const deleted file mode 100644 index 6e1dda57f6..0000000000 --- a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_12_10/Constraints/non_overlapping_clock_generator.const +++ /dev/null @@ -1,9 +0,0 @@ -MatchBlock(L1_INV1, L1_TG1) -MatchBlock(L1_NAND2, L1_NAND1) -MatchBlock(L1_INV2, L1_INV5) -MatchBlock(L1_INV3, L1_INV6) -MatchBlock(L1_INV4, L1_INV7) -MatchBlock(L1_TG1,L1_NAND1) -MatchBlock(L1_INV2,L1_NAND1) -MatchBlock(L1_INV2,L1_INV3) -MatchBlock(L1_INV3,L1_INV4) diff --git a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_12_10/Constraints/switched_capacitor_combination.const b/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_12_10/Constraints/switched_capacitor_combination.const deleted file mode 100644 index 5d4534c6d6..0000000000 --- a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_12_10/Constraints/switched_capacitor_combination.const +++ /dev/null @@ -1,9 +0,0 @@ -CritNet(net3, min) -CritNet(net6, min) -CritNet(net12, min) -ShieldNet(Vin) -ShieldNet(net3) -ShieldNet(net6) -MatchBlock(CC4, CC0) -MatchBlock(CC0, CC3) - diff --git a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_12_10/Constraints/switched_capacitor_filter.const b/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_12_10/Constraints/switched_capacitor_filter.const deleted file mode 100644 index c76babc60e..0000000000 --- a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_12_10/Constraints/switched_capacitor_filter.const +++ /dev/null @@ -1,23 +0,0 @@ -CritNet(Vinp_ota, min) -CritNet(Vinn_ota, min) -CritNet(Vinn, min) -CritNet(Vinp, min) -CritNet(Voutn, min) -CritNet(Voutp, min) -ShieldNet(Vinn) -ShieldNet(Vinp) -SymmNet({Vinn,CC5/MINUS,I2/Vin},{Vinp,CC7/MINUS,I1/Vin}) -SymmNet({Vinn_ota,CC5/PLUS,I0/Vinn,I1/Vin_ota},{Vinp_ota,CC7/PLUS,I0/Vinp,I2/Vin_ota}) -SymmNet({Voutp,CC8/PLUS,I0/Voutp,I1/Vout,I3/Voutp},{Voutn,CC9/PLUS,I0/Voutn,I2/Vout,I3/Voutn}) -MatchBlock(I1, I0) -MatchBlock(I0, I2) -MatchBlock(CC5, I0) -MatchBlock(CC5, CC7) -MatchBlock(CC7, I0) -MatchBlock(CC5, I3) -MatchBlock(CC7, I3) -MatchBlock(CC8, I0) -MatchBlock(CC8, CC9) -MatchBlock(CC9, I0) -MatchBlock(I4, I0) - diff --git a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_12_10/Constraints/telescopic_ota.const b/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_12_10/Constraints/telescopic_ota.const deleted file mode 100644 index d2b88919ad..0000000000 --- a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_12_10/Constraints/telescopic_ota.const +++ /dev/null @@ -1,30 +0,0 @@ -SymmNet( {Vinp,L1_MM1_MM0/G1,Vinp} , {Vinn,L1_MM1_MM0/G2,Vinn}) -SymmNet( {net10,L1_MM1_MM0/D1,L1_MM10_MM2/S1} , {net11,L1_MM1_MM0/D2,L1_MM10_MM2/S2}) -SymmNet( {Voutn,L1_MM10_MM2/D1,L1_MM7_MM6/D1,Voutn} , {Voutp,L1_MM10_MM2/D2,L1_MM7_MM6/D2,Voutp}) -SymmNet( {net13,L1_MM7_MM6/S1,L1_MM8_MM9/D1}, {net12,L1_MM7_MM6/S2,L1_MM8_MM9/D2}) -CritNet(net6, mid) -CritNet(net10, min) -CritNet(net11, min) -CritNet(Voutn, min) -CritNet(Voutp, min) -CritNet(net13, min) -CritNet(net12, min) -MatchBlock(L0_MM16,L0_MM11) -MatchBlock(L0_MM11,L1_MM8_MM9) -MatchBlock(L0_MM14,L1_MM8_MM9) -MatchBlock(L0_MM131,L1_MM7_MM6) -MatchBlock(L0_MM132,L1_MM7_MM6) -MatchBlock(L0_MM17,L1_MM10_MM2) -MatchBlock(L0_MM18,L1_MM10_MM2) -MatchBlock(L0_MM12,L1_MM1_MM0) -MatchBlock(L0_MM15,L1_MM1_MM0) -MatchBlock(L0_MM12,L1_MM4_MM3) -MatchBlock(L0_MM15,L1_MM4_MM3) -MatchBlock(L1_MM4_MM3, L1_MM1_MM0) -MatchBlock(L1_MM10_MM2, L1_MM1_MM0) -MatchBlock(L1_MM10_MM2, L1_MM7_MM6) -MatchBlock(L1_MM7_MM6, L1_MM8_MM9) -SymmBlock ( {L0_MM131,L0_MM132} , {L0_MM17,L0_MM18} , {L0_MM12,L0_MM15} , {L1_MM8_MM9} , {L1_MM7_MM6} , {L1_MM10_MM2} , {L1_MM1_MM0} , {L1_MM4_MM3} ) -AlignBlock("H",L1_MM7_MM6,L0_MM131,L0_MM132) -AlignBlock("H",L1_MM10_MM2,L0_MM17,L0_MM18) -AlignBlock("H",L0_MM11,L1_MM8_MM9) diff --git a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_12_10/LEF/sc.lef b/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_12_10/LEF/sc.lef deleted file mode 100644 index 65cbf4b0f9..0000000000 --- a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_12_10/LEF/sc.lef +++ /dev/null @@ -1,931 +0,0 @@ -VERSION 5.7 ; -BUSBITCHARS "[]" ; -DIVIDERCHAR "/" ; - -MACRO CMC_NMOS_25_1x10 - ORIGIN 0 0 ; - FOREIGN CMC_NMOS_25_1x10 0 0 ; - SIZE 2.16 BY 0.402 ; - PIN S2 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.256 0.32 2.012 0.338 ; - END - END S2 - PIN VSS - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER M2 ; - RECT 0 0 2.16 0.018 ; - END - END VSS - PIN VDD - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 0.384 2.16 0.402 ; - END - END VDD - PIN G - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER M2 ; - RECT 0.094 0.064 2.066 0.082 ; - END - END G - PIN D1 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.148 0.128 1.904 0.146 ; - END - END D1 - PIN D2 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.364 0.192 2.12 0.21 ; - END - END D2 - PIN S1 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.04 0.256 1.796 0.274 ; - END - END S1 - OBS - LAYER M1 ; - RECT 0 0 2.16 0.402 ; - END -END CMC_NMOS_25_1x10 - -MACRO CMC_PMOS_10_1x4 - ORIGIN 0 0 ; - FOREIGN CMC_PMOS_10_1x4 0 0 ; - SIZE 0.864 BY 0.402 ; - PIN S - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.04 0.32 0.716 0.338 ; - END - END S - PIN VDD - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER M2 ; - RECT 0 0.384 0.864 0.402 ; - END - END VDD - PIN VSS - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER M2 ; - RECT 0 0 0.864 0.018 ; - END - END VSS - PIN G - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.094 0.064 0.77 0.082 ; - END - END G - PIN D1 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.148 0.128 0.824 0.146 ; - END - END D1 - PIN D2 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.364 0.192 0.608 0.21 ; - END - END D2 - OBS - LAYER M1 ; - RECT 0 0 0.864 0.402 ; - END -END CMC_PMOS_10_1x4 - -MACRO CMC_PMOS_15_1x6 - ORIGIN 0 0 ; - FOREIGN CMC_PMOS_15_1x6 0 0 ; - SIZE 1.296 BY 0.402 ; - PIN S2 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.256 0.32 1.148 0.338 ; - END - END S2 - PIN VDD - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER M2 ; - RECT 0 0.384 1.296 0.402 ; - END - END VDD - PIN VSS - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER M2 ; - RECT 0 0 1.296 0.018 ; - END - END VSS - PIN G - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.094 0.064 1.202 0.082 ; - END - END G - PIN D1 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.148 0.128 1.04 0.146 ; - END - END D1 - PIN D2 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.364 0.192 1.256 0.21 ; - END - END D2 - PIN S1 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.04 0.256 0.932 0.274 ; - END - END S1 - OBS - LAYER M1 ; - RECT 0 0 1.296 0.402 ; - END -END CMC_PMOS_15_1x6 - -MACRO Cap_32f_1x1 - ORIGIN 0 0 ; - FOREIGN Cap_32f_1x1 0 0 ; - SIZE 4.024 BY 4.06 ; - PIN PLUS - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 4.037 4.024 4.055 ; - END - END PLUS - PIN MINUS - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 0.005 4.024 0.023 ; - END - END MINUS -END Cap_32f_1x1 - -MACRO Cap_50f_2x3 - ORIGIN 0 0 ; - FOREIGN Cap_50f_2x3 0 0 ; - SIZE 7.048 BY 4.7 ; - PIN PLUS - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 4.677 4.672 4.695 ; - END - END PLUS - PIN MINUS - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 0.005 7.048 0.023 ; - END - END MINUS -END Cap_50f_2x3 - -MACRO Cap_60f_2x3 - ORIGIN 0 0 ; - FOREIGN Cap_60f_2x3 0 0 ; - SIZE 7.048 BY 4.7 ; - PIN PLUS - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 4.677 7.048 4.695 ; - END - END PLUS - PIN MINUS - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 0.005 7.048 0.023 ; - END - END MINUS -END Cap_60f_2x3 - -MACRO DP_NMOS_75_3x10 - ORIGIN 0 0 ; - FOREIGN DP_NMOS_75_3x10 0 0 ; - SIZE 2.16 BY 1.298 ; - PIN S - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.04 1.152 2.012 1.17 ; - END - PORT - LAYER M2 ; - RECT 0.148 0.576 2.12 0.594 ; - END - PORT - LAYER M2 ; - RECT 0.04 0.256 2.012 0.274 ; - END - END S - PIN VSS - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER M2 ; - RECT 0 0.896 2.16 0.914 ; - END - PORT - LAYER M2 ; - RECT 0 0.832 2.16 0.85 ; - END - PORT - LAYER M2 ; - RECT 0 0 2.16 0.018 ; - END - END VSS - PIN VDD - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER M2 ; - RECT 0 1.28 2.16 1.298 ; - END - PORT - LAYER M2 ; - RECT 0 0.448 2.16 0.466 ; - END - PORT - LAYER M2 ; - RECT 0 0.384 2.16 0.402 ; - END - END VDD - PIN D1 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.148 1.024 1.904 1.042 ; - END - PORT - LAYER M2 ; - RECT 0.256 0.704 2.012 0.722 ; - END - PORT - LAYER M2 ; - RECT 0.148 0.128 1.904 0.146 ; - END - END D1 - PIN D2 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.364 1.088 2.12 1.106 ; - END - PORT - LAYER M2 ; - RECT 0.04 0.64 1.796 0.658 ; - END - PORT - LAYER M2 ; - RECT 0.364 0.192 2.12 0.21 ; - END - END D2 - PIN G1 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.094 0.96 1.85 0.978 ; - END - PORT - LAYER M2 ; - RECT 0.31 0.768 2.066 0.786 ; - END - PORT - LAYER M2 ; - RECT 0.094 0.064 1.85 0.082 ; - END - END G1 - PIN G2 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.31 1.216 2.066 1.234 ; - END - PORT - LAYER M2 ; - RECT 0.094 0.512 1.85 0.53 ; - END - PORT - LAYER M2 ; - RECT 0.31 0.32 2.066 0.338 ; - END - END G2 - OBS - LAYER M1 ; - RECT 0 0 2.16 0.402 ; - RECT 0 0.402 2.16 0.85 ; - RECT 0 0.85 2.16 1.298 ; - END -END DP_NMOS_75_3x10 - -MACRO DiodeConnected_NMOS_5_1x1 - ORIGIN 0 0 ; - FOREIGN DiodeConnected_NMOS_5_1x1 0 0 ; - SIZE 0.216 BY 0.402 ; - PIN VSS - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER M2 ; - RECT 0 0 0.216 0.018 ; - END - END VSS - PIN D - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.094 0.064 0.176 0.082 ; - END - END D - PIN S - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 0.128 0.068 0.146 ; - END - END S - PIN VDD - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER M2 ; - RECT 0 0.384 0.216 0.402 ; - END - END VDD -END DiodeConnected_NMOS_5_1x1 - -MACRO DiodeConnected_PMOS_10_1x2 - ORIGIN 0 0 ; - FOREIGN DiodeConnected_PMOS_10_1x2 0 0 ; - SIZE 0.432 BY 0.402 ; - PIN VSS - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER M2 ; - RECT 0 0 0.432 0.018 ; - END - END VSS - PIN D - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.094 0.064 0.392 0.082 ; - END - END D - PIN S - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 0.128 0.284 0.146 ; - END - END S - PIN VDD - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER M2 ; - RECT 0 0.384 0.432 0.402 ; - END - END VDD -END DiodeConnected_PMOS_10_1x2 - -END LIBRARY -VERSION 5.7 ; -BUSBITCHARS "[]" ; -DIVIDERCHAR "/" ; - -VIA M2_M1_0 - VIARULE M2_M1 ; - CUTSIZE 0.018 0.018 ; - LAYERS M1 V1 M2 ; - CUTSPACING 0.018 0.018 ; - ENCLOSURE 0 0.005 0.005 0 ; - ROWCOL 1 1 ; -END M2_M1_0 - -VIA M2_M1_1 - VIARULE M2_M1 ; - CUTSIZE 0.018 0.018 ; - LAYERS M1 V1 M2 ; - CUTSPACING 0.018 0.018 ; - ENCLOSURE 0 0.005 0.005 0 ; - ROWCOL 1 1 ; -END M2_M1_1 - -MACRO DiodeConnected_PMOS_20_1x4 - ORIGIN 0 0 ; - FOREIGN DiodeConnected_PMOS_20_1x4 0 0 ; - SIZE 0.864 BY 0.402 ; - PIN VSS - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER M2 ; - RECT 0 0 0.864 0.018 ; - END - END VSS - PIN D - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.094 0.064 0.824 0.082 ; - END - END D - PIN S - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 0.128 0.716 0.146 ; - END - END S - PIN VDD - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER M2 ; - RECT 0 0.384 0.864 0.402 ; - END - END VDD -END DiodeConnected_PMOS_20_1x4 - -MACRO SCM_NMOS_50_1x12 - ORIGIN 0 0 ; - FOREIGN SCM_NMOS_50_1x12 0 0 ; - SIZE 2.592 BY 0.402 ; - PIN D1 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 1.228 0.192 1.472 0.21 ; - END - PORT - LAYER M2 ; - RECT 1.444 0.192 1.472 0.21 ; - END - END D1 - PIN VSS - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER M2 ; - RECT 0 0 2.592 0.018 ; - END - END VSS - PIN S - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.04 0.256 2.444 0.274 ; - END - END S - PIN VDD - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER M2 ; - RECT 0 0.384 2.592 0.402 ; - END - END VDD - PIN D2 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.148 0.128 2.552 0.146 ; - END - END D2 - OBS - LAYER M1 ; - RECT 0 0 2.592 0.402 ; - END -END SCM_NMOS_50_1x12 - -MACRO Switch_NMOS_10_1x1 - ORIGIN 0 0 ; - FOREIGN Switch_NMOS_10_1x1 0 0 ; - SIZE 0.432 BY 0.402 ; - PIN S - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.04 0.064 0.284 0.082 ; - END - END S - PIN VSS - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER M2 ; - RECT 0 0 0.432 0.018 ; - END - END VSS - PIN D - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.148 0.192 0.392 0.21 ; - END - END D - PIN G - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.094 0.128 0.338 0.146 ; - END - END G - PIN VDD - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER M2 ; - RECT 0 0.384 0.432 0.402 ; - END - END VDD - -END Switch_NMOS_10_1x1 - -MACRO Switch_PMOS_10_1x1 - ORIGIN 0 0 ; - FOREIGN Switch_PMOS_10_1x1 0 0 ; - SIZE 0.432 BY 0.402 ; - PIN S - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.04 0.192 0.284 0.21 ; - END - END S - PIN VSS - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER M2 ; - RECT 0 0 0.432 0.018 ; - END - END VSS - PIN D - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.148 0.064 0.392 0.082 ; - END - END D - PIN G - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.094 0.128 0.338 0.146 ; - END - END G - PIN VDD - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER M2 ; - RECT 0 0.384 0.432 0.402 ; - END - END VDD -END Switch_PMOS_10_1x1 - -MACRO Inv_3_1x1 - ORIGIN 0 0 ; - FOREIGN Inv_3_1x1 0 0 ; - SIZE 0.162 BY 0.402 ; - PIN VSS - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER M2 ; - RECT 0 0 0.162 0.018 ; - END - END VSS - PIN VDD - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER M2 ; - RECT 0 0.384 0.162 0.402 ; - END - END VDD - PIN OUT - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M1 ; - RECT 0.099 0.066 0.117 0.336 ; - END - END OUT - PIN IN - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M1 ; - RECT 0.063 0.182 0.081 0.22 ; - END - END IN -END Inv_3_1x1 - -MACRO Inv_21_1x7 - ORIGIN 0 0 ; - FOREIGN Inv_21_1x7 0 0 ; - SIZE 1.134 BY 0.402 ; - PIN VSS - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER M2 ; - RECT 0 0 1.134 0.018 ; - END - END VSS - PIN VDD - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER M2 ; - RECT 0 0.384 1.134 0.402 ; - END - END VDD - PIN IN - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.058 0.192 1.058 0.21 ; - END - END IN - PIN OUT - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.094 0.064 1.094 0.082 ; - END - END OUT -END Inv_21_1x7 - -MACRO NAND_1_1x1 - ORIGIN 0 0 ; - FOREIGN NAND_1_1x1 0 0 ; - SIZE 0.216 BY 0.402 ; - PIN VSS - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER M2 ; - RECT 0 0 0.216 0.018 ; - END - END VSS - PIN VDD - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER M2 ; - RECT 0 0.384 0.216 0.402 ; - END - END VDD - PIN IN_B - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M1 ; - RECT 0.135 0.259 0.153 0.297 ; - END - END IN_B - PIN IN_A - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M1 ; - RECT 0.063 0.182 0.081 0.22 ; - END - END IN_A - PIN OUT - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.094 0.192 0.176 0.21 ; - END - END OUT -END NAND_1_1x1 - -MACRO TG_3_1x1 - ORIGIN 0 0 ; - FOREIGN TG_3_1x1 0 0 ; - SIZE 0.162 BY 0.402 ; - PIN VSS - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER M2 ; - RECT 0 0 0.162 0.018 ; - END - END VSS - PIN VDD - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER M2 ; - RECT 0 0.384 0.162 0.402 ; - END - END VDD - PIN OUT - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M1 ; - RECT 0.099 0.093 0.117 0.309 ; - END - END OUT - PIN IN - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M1 ; - RECT 0.045 0.093 0.063 0.309 ; - END - END IN - PIN IN_P - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M1 ; - RECT 0.0635 0.34 0.0815 0.378 ; - END - END IN_P - PIN IN_N - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M1 ; - RECT 0.0625 0.024 0.0805 0.062 ; - END - END IN_N -END TG_3_1x1 - -MACRO SCM_CMFB_NMOS_50_1x12 - ORIGIN 0 0 ; - FOREIGN SCM_CMFB_NMOS_50_1x12 0 0 ; - SIZE 2.592 BY 0.402 ; - PIN D1 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 1.228 0.192 1.472 0.21 ; - END - PORT - LAYER M2 ; - RECT 1.444 0.192 1.472 0.21 ; - - -END - END D1 - PIN VSS - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER M2 ; - RECT 0 0 2.592 0.018 ; - END - END VSS - PIN S - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.04 0.256 2.444 0.274 ; - END - END S - PIN G2 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.094 0.32 2.498 0.338 ; - END - END G2 - PIN VDD - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER M2 ; - RECT 0 0.384 2.592 0.402 ; - END - END VDD - PIN D2 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0.148 0.128 2.552 0.146 ; - END - END D2 - OBS - LAYER M1 ; - RECT 0 0 2.592 0.402 ; - END -END SCM_CMFB_NMOS_50_1x12 - -MACRO Cap_30f_1x3 - ORIGIN 0 0 ; - FOREIGN Cap_30f_1x3 0 0 ; - SIZE 7.048 BY 2.332 ; - PIN PLUS - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 2.309 7.048 2.327 ; - END - END PLUS - PIN MINUS - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 0.005 7.048 0.023 ; - END - END MINUS -END Cap_30f_1x3 - -END LIBRARY diff --git a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_12_10/Netlist/2019_06_19_SC_Filter.sp b/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_12_10/Netlist/2019_06_19_SC_Filter.sp deleted file mode 100644 index b6c5f7324c..0000000000 --- a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_12_10/Netlist/2019_06_19_SC_Filter.sp +++ /dev/null @@ -1,53 +0,0 @@ -** Generated for: hspiceD -** Generated on: Jun 19 10:29:58 2019 -** Design library name: ALIGN_circuits_ASAP7nm -** Design cell name: switched_capacitor_filter_spice -** Design view name: schematic - - -.TEMP 25.0 -.OPTION INGOLD=2 ARTIST=2 PSF=2 MEASOUT=1 PARHIER=LOCAL PROBE=0 MARCH=2 ACCURACY=1 POST -** Library name: ALIGN_circuits_ASAP7nm -** Cell name: telescopic_ota -** View name: schematic -.subckt telescopic_ota d1 vdd vinn vinp vss vbiasn vbiasnd vbiasp1 vbiasp2 voutn voutp -m9 voutn vbiasn net8 vss nmos_rvt w=270e-9 l=20e-9 nfin=25 -m8 voutp vbiasn net014 vss nmos_rvt w=270e-9 l=20e-9 nfin=25 -m5 D1 D1 vss vss nmos_rvt w=270e-9 l=20e-9 nfin=10 -m4 net10 vbiasnd vss vss nmos_rvt w=270e-9 l=20e-9 nfin=50 -m3 net014 vinn net10 vss nmos_rvt w=270e-9 l=20e-9 nfin=70 -m0 net8 vinp net10 vss nmos_rvt w=270e-9 l=20e-9 nfin=70 -m7 voutp vbiasp2 net012 net012 pmos_rvt w=270e-9 l=20e-9 nfin=15 -m6 voutn vbiasp2 net06 net06 pmos_rvt w=270e-9 l=20e-9 nfin=15 -m2 net012 vbiasp1 vdd vdd pmos_rvt w=270e-9 l=20e-9 nfin=10 -m1 net06 vbiasp1 vdd vdd pmos_rvt w=270e-9 l=20e-9 nfin=10 -.ends telescopic_ota -** End of subcircuit definition. - -** Library name: ALIGN_circuits_ASAP7nm -** Cell name: switched_capacitor_filter_spice -** View name: schematic -m0 voutn phi1 net67 vss nmos_rvt w=270e-9 l=20e-9 nfin=5 -m7 net66 phi1 net63 vss nmos_rvt w=270e-9 l=20e-9 nfin=5 -m6 net72 phi1 vinn vss nmos_rvt w=270e-9 l=20e-9 nfin=5 -m3 agnd phi2 net67 vss nmos_rvt w=270e-9 l=20e-9 nfin=5 -m5 agnd phi2 net63 vss nmos_rvt w=270e-9 l=20e-9 nfin=5 -m4 net72 phi2 agnd vss nmos_rvt w=270e-9 l=20e-9 nfin=5 -m8 net60 phi2 agnd vss nmos_rvt w=270e-9 l=20e-9 nfin=5 -m11 agnd phi2 net68 vss nmos_rvt w=270e-9 l=20e-9 nfin=5 -m9 agnd phi2 net62 vss nmos_rvt w=270e-9 l=20e-9 nfin=5 -m10 net64 phi1 net62 vss nmos_rvt w=270e-9 l=20e-9 nfin=5 -m12 net60 phi1 vinp vss nmos_rvt w=270e-9 l=20e-9 nfin=5 -m14 voutp phi1 net68 vss nmos_rvt w=270e-9 l=20e-9 nfin=5 -i0 id vdd net64 net66 vss vbiasn vbiasnd vbiasp1 vbiasp2 voutn voutp telescopic_ota -c9 voutp vss 60e-15 -c8 voutn vss 60e-15 -c7 net62 net68 30e-15 -c6 net64 voutp 60e-15 -c5 vinn net64 30e-15 -c4 net60 net62 60e-15 -c3 net66 voutn 60e-15 -c2 vinp net66 30e-15 -c1 net63 net67 30e-15 -c0 net72 net63 60e-15 -.END diff --git a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_12_10/README.md b/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_12_10/README.md deleted file mode 100644 index 48d8899d9a..0000000000 --- a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_12_10/README.md +++ /dev/null @@ -1,17 +0,0 @@ -# INPUT for PnR tool -sc_block.v : block level netlist for switched capacitor -   This netlist contains two modules which need to be placed and routed hierarchicaly. -      1.switched_capacitor_filter : top level module , corresponding constraint are there in switched_capacitor_filter.const -      2.telescopic_ota : sub module , corresponding constraint are there in telescopic_ota.const - -sc.lef : lef file with block dimensions and pin locations - -# BLOCKS used (defined in lef, used in netlist) -1.CMC_NMOS_25_1 : common centroid transistors with gate connection -2.CMC_PMOS_10_1 : common centroid transistors with gate connection -3.CMC_PMOS_15_1 : common centroid transistors with gate connection -4.DP_NMOS_70_1 : Differential pair -5.SCM_NMOS_50 : current mirror -6.Cap_xxf: capacitance -7.Switch_NMOS_10 : transistor building block with 10 fins -8.Switch_PMOS_10 : transistor building block with 10 fins diff --git a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_12_10/Testbench/2019_06_19_SC_Filter_testbench.sp b/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_12_10/Testbench/2019_06_19_SC_Filter_testbench.sp deleted file mode 100644 index 46f2959fb2..0000000000 --- a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_12_10/Testbench/2019_06_19_SC_Filter_testbench.sp +++ /dev/null @@ -1,152 +0,0 @@ -** Generated for: hspiceD -** Generated on: Nov 19 16:37:16 2018 -** Design library name: DC_converter -** Design cell name: 2018_11_09_ASAP7_SCFilter -** Design view name: schematic -.GLOBAL vdd! - -.AC DEC 100 1.0 1e11 - -.TRAN 1e-9 50e-6 START=1e-9 - -.OP - -.TEMP 25.0 -.OPTION INGOLD=2 ARTIST=2 PSF=2 MEASOUT=1 PARHIER=LOCAL PROBE=0 MARCH=2 ACCURACY=1 POST -.INCLUDE "/project/analog-group04/Meghna/Design_Work/ASAP7nm/asap7PDK_r1p3/models/hspice/7nm_TT_160803.pm" - -** Library name: DC_converter -** Cell name: 2018_11_09_ASAP7_telescopic_ota -** View name: schematic -.subckt telescopic_ota D1 vdd vinn vinp vss vbiasn vbiasnd vbiasp1 vbiasp2 voutn voutp -m9 voutn vbiasn net8 vss nmos_rvt w=270e-9 l=20e-9 nfin=25 -m8 voutp vbiasn net014 vss nmos_rvt w=270e-9 l=20e-9 nfin=25 -m5 D1 D1 vss vss nmos_rvt w=270e-9 l=20e-9 nfin=10 -m4 net10 vbiasnd vss vss nmos_rvt w=270e-9 l=20e-9 nfin=50 -m3 net014 vinn net10 vss nmos_rvt w=270e-9 l=20e-9 nfin=70 -m0 net8 vinp net10 vss nmos_rvt w=270e-9 l=20e-9 nfin=70 -m7 voutp vbiasp2 net012 net012 pmos_rvt w=270e-9 l=20e-9 nfin=15 -m6 voutn vbiasp2 net06 net06 pmos_rvt w=270e-9 l=20e-9 nfin=15 -m2 net012 vbiasp1 vdd vdd pmos_rvt w=270e-9 l=20e-9 nfin=10 -m1 net06 vbiasp1 vdd vdd pmos_rvt w=270e-9 l=20e-9 nfin=10 -.ends telescopic_ota -** End of subcircuit definition. - - -** Library name: asap7ssc7p5t -** Cell name: INVx1_ASAP7_75t_R -** View name: schematic -.subckt INVx1_ASAP7_75t_R a y vdd vss -m0 y a vss vss nmos_rvt w=81e-9 l=20e-9 nfin=3 -m1 y a vdd vdd pmos_rvt w=81e-9 l=20e-9 nfin=3 -.ends INVx1_ASAP7_75t_R -** End of subcircuit definition. - -** Library name: asap7ssc7p5t -** Cell name: INVx1_ASAP7_75t_R_21 -** View name: schematic -.subckt INVx1_ASAP7_75t_R_21 a y vdd vss -m0 y a vss vss nmos_rvt w=81e-9 l=20e-9 nfin=21 -m1 y a vdd vdd pmos_rvt w=81e-9 l=20e-9 nfin=21 -.ends INVx1_ASAP7_75t_R_21 -** End of subcircuit definition. - -** Library name: DC_converter -** Cell name: 2018_12_03_ASAP7_transmission_gate -** View name: schematic -.subckt DC_converter_2018_12_03_ASAP7_transmission_gate a y vdd vss -m0 y vdd a 0 nmos_rvt w=81e-9 l=20e-9 nfin=3 -m1 y vss a a pmos_rvt w=81e-9 l=20e-9 nfin=3 -.ends DC_converter_2018_12_03_ASAP7_transmission_gate -** End of subcircuit definition. - -** Library name: DC_converter -** Cell name: 2018_11_09_ASAP7_NAND_gate -** View name: schematic -.subckt DC_converter_2018_11_09_ASAP7_NAND_gate_schematic a b out vdd vss -m2 out a net22 vss nmos_rvt w=54e-9 l=20e-9 nfin=2 -m3 net22 b vss vss nmos_rvt w=54e-9 l=20e-9 nfin=2 -m0 out a vdd vdd pmos_rvt w=27e-9 l=20e-9 nfin=1 -m1 out b vdd vdd pmos_rvt w=27e-9 l=20e-9 nfin=1 -.ends DC_converter_2018_11_09_ASAP7_NAND_gate_schematic -** End of subcircuit definition. - -** Library name: DC_converter -** Cell name: 2018_11_09_ASAP7_non_overlapping_clock_generator -** View name: schematic -.subckt DC_converter_2018_11_09_ASAP7_non_overlapping_clock_generator_schematic clk d_vdd d_gnd phi1 phi2 -xi6 clk net9 d_vdd d_gnd INVx1_ASAP7_75t_R -xi6_tg clk net9_tg d_dd d_gnd DC_converter_2018_12_03_ASAP7_transmission_gate -xi5 net12 phi2 d_vdd d_gnd INVx1_ASAP7_75t_R_21 -xi4 net17 net12 d_vdd d_gnd INVx1_ASAP7_75t_R -xi3 net8 phi1 d_vdd d_gnd INVx1_ASAP7_75t_R_21 -xi2 net15 net8 d_vdd d_gnd INVx1_ASAP7_75t_R -xi1 net16 net15 d_vdd d_gnd INVx1_ASAP7_75t_R -xi0 net18 net17 d_vdd d_gnd INVx1_ASAP7_75t_R -xi8 net9 net8 net18 d_vdd d_gnd DC_converter_2018_11_09_ASAP7_NAND_gate_schematic -xi7 net12 net9_tg net16 d_vdd d_gnd DC_converter_2018_11_09_ASAP7_NAND_gate_schematic -.ends DC_converter_2018_11_09_ASAP7_non_overlapping_clock_generator_schematic -** End of subcircuit definition. - - -** Library name: DC_converter -** Cell name: 2018_11_09_ASAP7_cmfb -** View name: schematic -.subckt DC_converter_2018_11_09_ASAP7_cmfb_schematic va vb vbias vcm vg phi1 phi2 -c3 net10 vg 20e-15 -c2 vg net8 20e-15 -m4 vbias phi2 vg 0 nmos_rvt w=27e-9 l=20e-9 nfin=50 -m3 vcm phi2 net10 0 nmos_rvt w=27e-9 l=20e-9 nfin=50 -m2 vb phi1 net10 0 nmos_rvt w=27e-9 l=20e-9 nfin=50 -m1 net8 phi2 vcm 0 nmos_rvt w=27e-9 l=20e-9 nfin=50 -m0 net8 phi1 va 0 nmos_rvt w=27e-9 l=20e-9 nfin=50 -.ends DC_converter_2018_11_09_ASAP7_cmfb_schematic -** End of subcircuit definition. - - -** Library name: DC_converter -** Cell name: 2018_11_09_ASAP7_SCFilter -** View name: schematic -i5 vdd! id DC=40e-6 -m0 voutn phi1 net67 vss nmos_rvt w=270e-9 l=20e-9 nfin=5 -m7 net66 phi1 net63 vss nmos_rvt w=270e-9 l=20e-9 nfin=5 -m6 net72 phi1 vinn vss nmos_rvt w=270e-9 l=20e-9 nfin=5 -m3 agnd phi2 net67 vss nmos_rvt w=270e-9 l=20e-9 nfin=5 -m5 agnd phi2 net63 vss nmos_rvt w=270e-9 l=20e-9 nfin=5 -m4 net72 phi2 agnd vss nmos_rvt w=270e-9 l=20e-9 nfin=5 -m8 net60 phi2 agnd vss nmos_rvt w=270e-9 l=20e-9 nfin=5 -m11 agnd phi2 net68 vss nmos_rvt w=270e-9 l=20e-9 nfin=5 -m9 agnd phi2 net62 vss nmos_rvt w=270e-9 l=20e-9 nfin=5 -m10 net64 phi1 net62 vss nmos_rvt w=270e-9 l=20e-9 nfin=5 -m12 net60 phi1 vinp vss nmos_rvt w=270e-9 l=20e-9 nfin=5 -m14 voutp phi1 net68 vss nmos_rvt w=270e-9 l=20e-9 nfin=5 -xi0 id vdd net64 net66 vss vbiasn id vbiasp1 vbiasp2 voutn voutp telescopic_ota -c9 voutp vss 60e-15 -c8 voutn vss 60e-15 -c7 net62 net68 30e-15 -c6 net64 voutp 60e-15 -c5 vinn net64 30e-15 -c4 net60 net62 60e-15 -c3 net66 voutn 60e-15 -c2 vinp net66 30e-15 -c1 net63 net67 30e-15 -c0 net72 net63 60e-15 -xi3 clk vdd! 0 phi1 phi2 DC_converter_2018_11_09_ASAP7_non_overlapping_clock_generator_schematic -v0 clk 0 PULSE 0 1 0 0 0 115e-9 250e-9 -v11 vdd! 0 DC=1 -v7 agnd 0 DC=550e-3 -v6 vcm 0 DC=550e-3 -v5 vbias_cm 0 DC=375e-3 -v2 vinp 0 SIN 550e-3 10e-3 50e+3 0 0 0 -v1 vinn 0 SIN 550e-3 10e-3 50e+3 0 0 180 -v3 vbiasn 0 DC=700e-3 -v4 vbiasp2 0 DC=300e-3 -v10 vbiasp1 0 DC=490e-3 -v8 vss 0 DC=0 -v9 vdd 0 DC=1 -xi13 voutn voutp id vcm vg phi1 phi2 DC_converter_2018_11_09_ASAP7_cmfb_schematic -**xi13 voutn voutp vbias_cm vcm vg phi1 phi2 DC_converter_2018_11_09_ASAP7_cmfb_schematic -.probe vdiff1=par('v(voutn)-v(voutp)') -.probe vdiff=par('v(vinn)-v(vinp)') -**.probe hb voutn -.END diff --git a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_12_10/Verilog Netlist/__Previews/sc_block.vPreview b/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_12_10/Verilog Netlist/__Previews/sc_block.vPreview deleted file mode 100644 index 713d50a611..0000000000 --- a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_12_10/Verilog Netlist/__Previews/sc_block.vPreview +++ /dev/null @@ -1,14 +0,0 @@ -[Preview] -LargeImageOriginalSize=2832000 -LargeImageWidth=708 -LargeImageHeight=1000 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2ECF4DB0F78A36DBDF394D8C95B4671E6499893A2F66CDBD80636B45E53EB54EC8CF027DA7525926C73AB503B2A914E16379225F26557DC31AC3C0EEF09B675E47451F14D4399E4E3E9DF0CCB72C6BB19E39E9C1B5AC54F646618BE901DAD662688A342B79D77BFC10341E07EC977B8A105BDC4480B77DA8DB8BD95EBDAAE2710097A7C32C469F780CE43E7CF68FACBD429DD312ABB6E7A9F6CA85B6D5D84E76F64AA0EF75A12BD6B3B4890B56DBDAA4EDC8588959E7AE8F8C59369B9C6FA7F80C106F849C1A0AEC233E3534D523BB2BA1EE3BB3516B2ADB96ACA37EFA25E0FA0D4DD9FF38C9D48BD0B44642B7E6886887FAD19D5C4FDD747723BC4E6DF7BC2FDD89E3CDA0E3710C4D2589BE3419B87D2108F27EE2169F0E90FB5C8827175958B0DDC3FBCA84147B598C45317AE186CDCFC0E790B9C5A7734A07086A0F833D130F4FDAF2C0C796858588327DF979B6E30ECF7393811B5EF630F841C1A76AC56BF6884F679323BD361EF28E9127CB4CD439D711C447DDC9F88B9321EB860363E8DDC52CC92EDE25B2BF2EAB57C9628058CD721DDD6B833DFC654FFD81787F5EF916655D582FB0BCC9F6B0AC07AFB2DACE2BEA423FF6F0F9ABF181C76B56C5A783F7AACCEC88EDD82EB5DF60FE048FDBCC8F83ADB315B96DFD2DD71395ED06B6E0E72C6665842433B40D856E2AF359A43655259F56A6037FEF6452B6748F225EB35897556D4BD6513FFD1230C8781C3C9E4A92E685C7D7F1AB3BD53BF2207497BC0B656BF5AD3BB77BE01B88E93B3FD8BE8D0882BC1FC8F6B0EC0793FB5C781F17E386C178105D9867BFEF176AB631727266C58A45C1AF01E09B5A2E6A8EBD7724FB51C4291DE0E21598D368F6A3B23D5C2B44ADBCF373E02313E376C6E878CEE7F62D4473F66FC9420C0E273BD5E9796E327003D2E17159979210BBE1A14D1FD7A735E693B3EC6145FC615196E08387EFCD31FAAC7C2AC66C383FF54135F68936FE41E33503F0FD3EBD1826E1C5B432D600D48F990036B1CA2E68C271C1F6F41BAF99CBFA938F3F61FA95ED61590F5E65E5C0B782F4E7B3A459D17DDFE3C4F86C66E0F6302BE31DBBAD0EB64666D6EE1FE67630D856C56437561DD48BE8C5AE5D62C6DCEBC6CBF663BB89E92F65F3D6DAB007DB456B0E11B3A1A6FE6C5D07F96814D76D793E0A7BD8A8D4582C9558625ED9B6641DF5D32F0183B487E7A19FA3CF06BF7F3474CB8A11EE47775EF554D41DF49F4BB1A82FDD7DFDF5FD03E9CEED1EE84732B40E1DC53EDD0882BCFBB8F98779EC7AB9CFADD2FE6E752DC5FABBD4DAAA65D380CD9A486FD0E349A269513239719DDA24A6EF64B35CA77D7088DD13D3B4EE1C4D17FFB02A1D3E7F786CFC024D2341B47084945613EC7A38373AB944EEDCFE17128F4449E8D275DB394D4BD3E3111263B1C2D6AC74C0D791D0622419A5D0B486C7A7D91804FE85D1C9B065A78AEBA29D9EE726033764FB0AFC99FBFB4D6687151E3D647E1DB045225F7FEDCB3F7C6D7A9ECA2BF85A1ED5D8779FA635287B18C6CAA1A1313A46EA44A7F21D1B1A52CEAD86B12C1A9AF69D67B98E821ED6EF76C774BFF6309775F34D93CAF7A6CD1E56E9C1ADAC1C98333D47EB6955CFF6CC673C8AF9124E78F98755F3254237BB6BEBE66F77631542BD884C4C92D87C82242371B2910859E79CFA11E0C1F62EB37BB5983D1E612C4DEDE14892B5BBE9CFD7C8D375F35E88A5767DE2026D1F21360775239D20A2FFAF9F6FEE41011BB692D75CE3C5883AEAB75F8239B9E7468695FD8F53BD77CC33D5C139DAD660EE307CE31839374126478759DBF3A3BBD09573BE75076D3C16D27CE9AE59EDCEFD1DF47C09B0B74FD1FFC5F70D04411027C43111FC76F9B436B067FB992BD064F35B35D26E810DDE26F5668BF6BDFE63FC1E364EFEE141CA404E077CBBD98439CE831D76F3FC396647D5A8DD7EFAF488E7FC6160EEF63C5BBF057358AF8CCDB9C6631551D9C330E6F0EFABA6EFC8BF2D16C4DE33209E97602F8ADF07BCF2ACB20B625F2ED99EE5956F51D6F037ACD509DF38DF734ED44390B2C279399FFDD8C341D7D33921B67D2DBDA99C5F2DAEA7E3DFDBF9B9706ED7B23582BE271D16FDACC90A0AD8C3F5A259B7568DBAB26D0D4A4783F40F3BF12EEBEE28F48D20C8EF1FF07F8E0C8F5AF3D652CB2B3DDFFE0E1267D5AF2D98DED049243ACFE6A23D585E22F3D3EF973D0CB6ADE8878E2623A4B29D65E746AF2D13EDC259F61B7C9EA7CE5C24FAF235F637BCBF843A3E77F8579C7B00328D27A3F45971726568DC973DBCB55524F77FD853CE15DC4E9B65D0D2FED6D355EBD46E348A81EC3D58D7582B9AEB1A617EC14ACC3DCF7C7F09F05F8527477BD6CDC37A4C9089F99EE7BD9E4E943590A4F93977E6147B86AB1E5CCA5AD8D2D97B09ACE9837916DC7EEC473E1CF029863E85F56CFDCF8B14DB3EF3D5655794CF8B5219C0B77328F38496677286FE00640A757689FE0DDF24BC6CAAA388D70C4C5F9E21871D9B1BCA1E4B70FF674CD9B606A123C0C91EE66DF528ECE1A388D7DCAFEE8E42DF08822040BFE318DFE3E924C766386CDE3519986BC52B44DFEAF5A3563A7B8CD5ABFEF7056B501B50F52C37D8FE7A99DE7DF7FA2D0FEC09C5F63A3BE431D3A9ACB09716CCE336F75B6BFABAC70FD02E8F625E24D87565BDE87A8DB8DF9A5B7E0FDB1E86F7B620FBD61D3687A923DE560721533FBA3B6C7BB81FDD9D347D2308822008822008822008820C9A27851229C31EF812FFD48F667DC8AB665B997E598ACDF2AE94E75DD5C3FB8493ACFBAD7308EA0E411004411004191CE59CCEECBBE76C0E0EEE6BFB2E81BA4310C489D72D4A59BD2FADDB3904414E2E7F9B86357A873B5FFAD96E8BBCCC055F0BF87BE0FB9BCEEB3C9F579AE4657E5179EEDB9915F26B75F350F2843A3AB8EEBE0F2D068EEFEC760F8CA1AFDE91B5230882D0F63C9F726CCFAA73D0C69FE965EB3BD80B58F7D479D7FEB54DDFC1E319DB77B217B9B875EF73A3C68EBD34EC7DC4EB66CBBAEF6DBD42CA9982D58F342A752B9DDFDADD31FE37CA939CC1CEFD5AB3EFB723A6F35B270EF43FAB4D760C9E0B65E0BFE11CA4F7C4E1DC5B5AA627991C3BFF5A4A07CE953BE7E43C3CD32BEC398D628EBC15F601767A9E9B0C9CE06562E974F62665798AE7D8B1DF9A559B4EF835CF3B327D25E801AE7B695079663256BEFDD41FB12E305D74F6DE075ED65BECD8EB8AC1F658F07A963C3F036404F58F97F3755927FFEC3C53960DBFF719BBC73D2DD53C10FE3CB35EE9DD7CBB3C4794B525DB52D5F441E532AE7A90F32096C7949B79ED2B8F3CC8BCA6E9FC78E9A2EFEB9FEB55F24AB7CB52D6E9DB7AEFBE1C8F225BE43761DF70B7F625D7F9DF24FD886DC5AFDFAE51AEDBE6AB9872CF9097BB25F6EF73613DA65BBFF49AE921439ED17AFFAC50B47C87AC1E64B6BAED4B78DEF7B4ECAF1B3BD67D727D7BA4E5A9CC7A7D090DD8E7E4CCD94073077E6DF5EA486CAB4F687EDF36D5CF1375A4D20F6F5F6EFD5257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036EA2F68DAE833D8C28C6737EE829836EAABA87DB4BE48EB7939F2211D1BEFA0C7A144165EF79369329E17747C5FEF9845CDB18F3097D8425FF36DD4DF6C45F86194FD777B508549958A8D85D2B237694D4F343EBCB699837A5849DA4CB1DE3D6E7CD8AC31957CDF2BDDFDCD0DB8D739C8CA4298A70B98F578F7FD8BE2F8709694DBB8C556929E721EE6E85C6B71AE27B6968345F5E81DFCDA864E2C4C98C5F161BD7E4C1C1F9E8DAD89E3C342F8C7CDD3B55699A7B32DAC93DFEC585A5AC2FC6A1EB27BB770F1C2998A7C2CE7D6BD3E78478D8F9FA793CC230F0ECAABFA236AB730DF4CF523C78F1CC7766E0DFEF90896025E92061FD652CBE2B1C768AA6AF75EF3748A3DE6E9E4A45E48ED3E76F1963877F338BBE9F3FDBC77124ABD838D7F4E90F69527ED53A7D654D8ADB24C887355E548E7D9A5E3C3D2BA5472FE6E9D1BEA6967DFEF6B3DC83F2C8E71D3F158C1F6AFEBBE81CE6844686E8A95B1606BB96DADFD242FB78ACFE6FEE81A34F2A1AAE9A463E351FF4445DB90B687F230343D9E4816B10963497909F35D341DC3BA11A8140350EDBE2F4AD3B995A3FAAE15E2F346E19A5F45EEA1EF89EA92747CD8E589C1A1D642AD1C61F393E5F374D5D2E65FDA40C7ED2BE81D52A0B0B50A397DAF74376D6E5F18119F9BF515CAD326C59F2A6042DD59F445B96D5CFABABACEE345F143D34BECB72605D74B3C82EB259EAF5EA2DCB697592F613058715F46FA93B9D527CAD3E7A997A0483550DF57BDC48727BEC28CCB81DA9AEB6C9EEEEC9767A11CE8C1783885DFFDD33B7087E6A126759CEA87E9B8C4A88D6AD54BEF234AE742D5F6B2BABA06ADA6A8F3A6731E745C62DCE5647A091AA69A7FA5FA61FB50F19E4EE7E9F63A4F4877E3D5ABB0FA42F8DD6BBF42D46D64E9BEFCF1FB6868D660D13FC6F4C356EB08FCA4CF244D4F357ABB7B4A6CA3F7A58676E26F162770F1F23568EC334C3FAC912B44FDF030793E10F4C30A3DD5072C88CFE77A72DFA63E6C403322CE57D17189D9393F7B66A5CF98568392FD5EAE9770790248C6A355DBAC007D268B9278E8F329CD533A2EE1F47BD97D938E4B08C7F4DCBE43CC7153BB6BBEBACCE6E96ACF9FC3742485B6CE6EB4DFA6FD890DF13836E5AC6AB7AA6F80FD2EB59B8E4B54B3BB5C2F41ED169E810F62379D43F593677DFF54F19935B1FB3C9D594B317F3DA6E93F547B90EA87A57529BD54FA1C2BD4B99D42B1BF40F51313FA21362E3133330BAFB3D8DF8826E8B8F8B858C682ADB46E0FF6B58BF1F57595D6BD839491543F2C6D0FD2F304FD70F3ED76512F21D4733A4FE61AF792E7F5DCEE989013B96CAA422F613099609B4DA0909E67797A98BA4491EA878575EF689E76B776E1F2B57A5CBB79135AADBCA42E096913F4245E3F9D570955E82582F38BC864B760D229F7ADE7CADD7885EF0B8B31365EF6B4FEF3652291C922B55AA9C9A5651B5F8EEE19A67C0D8BA739EFA07577AFF450681B7A9AB2A17DE3F5D41A3B968E31D378F7B2219178FC3D99FA1DEA6F0E920661FC507A4CC7CDCAC7EE9F25E5760BE382DFA5DDD5584BD16B179E38FC6149EDE6C1415992D4C5B5D4F32B9F8A741EB29EB3F1E15DBD05CDD3EFAA2E1D043AF6EC24F79F9DEDED7DEBF97799BFCF8B83CED373BD44759E4623F143B5BBA22EBD04F6BCCC98EDE315DA3ACEF707E9FCB030D74B350BC29C6C6C315C1186F6B36818619EF349F412F4F9A29A5EF6A07A09E95A5AE573C5696287342DE9B5EAF757618E5BB049E8BF52BB13BB5A01A946427A2CC4D1DBD3CB3EE93880A09190EA01B6B777448D8430CF2ED500508DC4563643C2A7C8F3AB07C1D99992F3AAF55BA2BB65527C96F4307D82302E216824A4F3C3FBCD6B4BFBCFEC7961D7EEE5D534292B1B7B6695EA254AEC2E6C95684304BB055DADD4EE72ED8360370D6F27D729B77B3F8D4486F8688FD7C7CAA15C2F41ED16341206CFF26375078FAB4B82ADB46DD8CD76510741FB61347FF25BC53C167410F498EA0184B1156939D0F41CA41CE81A6D82BE80DA478FA9DD423E4AF5054239D0F16107C9D3422ECBCE49AC24595BCBE5F38F346CBB9A227A9CDF5C2FD1939443F51B42BADD9ED91FCCBE5D2F92F23913E1BB75621EDD77AE569C1F49ACC34DCE13E6289F442FB19ADB865D375C71FE41F512D2B8A59A0F5687E4CA92F9E6C12159D5F0D2396E3A0F2D68242CDE28BAAE7FC98EA51A89602A57A297A01A0BC3FD56E4C979745E4C3A3727A6CD62173512E5F6081A89F8D212060687D12597A1E576FDBE76D379C373672FB23917E91AF5D2793A3A37279D1F6679B0C7BCB674FE9DDA2D68243CDE69E207B6611C5697E82576B69645BB997D657392E5EBE4B75659275F6AB7C1E6825AAD2CB1BB5A5DA2760B1A89B9D00AF1E10928D51A6C7CBB51A297A0760B73E66C1D9A03E80EF6AB4B525BA53A88A6964E188D3A3876DF0B94EA20A4FA026939B0B5861E530EC29AC5E2FB67DA11766C5117DF8B94CE6B49D3D6D1DEC77CB0C96811D797176C12D2CC745DC671AC2E45981FA6FFEDA52FA0FA0D21DD7AD73C7C56C50BF753AF3AD27A4FE77AE91C253DD62A8731EA0D231BAF7C4F687266110B3EB758CE87D54B500606072AE33DA05E421AB754F341BFD37772A9BE61BFEB50A473DC52940A1554BA51E68FA41A8960245CA29710F65038881F6EAFE287A51A89D5D52C547A1DFA3B9AF7B55BD8B7C3A1D7EEEB870FBB778460B7A0915822FD738B518D994957855E42BA77C4E3FCF041F62BB159464AECAE5697A8DD824622B296836EA80F0A59F1FE2AD54B50BB9F6EDF8ED2BA54BE4F86A083D86F9F8CFE7EA5A82F78367B78EC3CDAC343E287A569BBDBD223FAE1FE7E05725B59B11D4BEB12ED5FCB7A6562FF76BF3D3C8474F3B5E39F3FD2F96161AE973E7FD2E7243A16BC489ECF42FED2F5C9E8DA5ED9B525C864C5723EAC5E22975B67FB21D1B50BCAC31C542F21DD7B4CAAF9189B9E87BAB3014DE47EBEE833317FAE73CC219FAE7C575298E396FE46D7A8BF7EE93C66E369F4DEBE029B3F2E6A246CFE84782C68247ABB8BCFBDC2B804D54848F500C2B804D50AD0E74EA98640BA6FC72A79167592F0F9ADFDEF3F6C2D715226E376335B53828E4B08FA04A95EA27C7EF87108760B1A099BDD0E93CD44EE2F1A4C4732257A8947766F976843A476B3F448ECF604171170DB2BECCEB1E77B5789DD55D794A0764BB42176F20CBE1C298E0348F512D4EE27D54894D72561DC8CDA5A6C1B01510741EF3D769B99BD9F51AEF990EA0B0E5B0E14BAA79DA02FA0EBA8452351A683E8ED1E16F505C27D4C2887197F80F4CD9DCC171B497FD8E522D7CD16C739843A47FBDA740ED538B9848D98675F3D09D56F08E9A6BE3B16DAFF5D63CE8B81BE7B23B49DC3EA2584793FEA4B1E779DA7D14B48DFC1DE2B8EC3CE71EF175EAA91D84B0FB09F86400AF53B07B55BFA0E9C30CEF8BCE78799DDBB63D707B19BFA80D4013412D4EEA7D34850BB9FAD46E2B075848D0F8BFA82EFAE1CC4EB074B7DA6B4CED1F7FB84B1EBFDF424AF82BEE05583EB259E0EAE97387C58AE97381C5C2FF1FDE687A097109E65CBAFC5F5125C2FF1B8BA24D87A18BD84506F6999BC4C7A095A97A676DB17B591EB255E1ECAC787E95E028DADADAC4E7817D6D07CE94C459891A945345FBF8A31AB997D7F92FD38E657736C3EA83CEE83EEC7211DD393EE2942FFEB971B61550EB26761E95E02E5D712F650A0C7749F03610F0E4F348B960B9FB163E91E1CC2F8303DA6E3C3740D0679671BF35F74FF0B610F0EE97E1313DE80B807076D47C21E15D4CF087B70CC4D7BD1D6791F3AB30537AE5E2E39AFDC0FD37679ECC313ACEDF9A6E7D95ED274FF8B07E1B8B81F07DD8343BAFF0065AF7D1384FD1D04BB853D38867516584C164C5AAD25FB71EC90B629D84DC348F71E11ECA67E7831912DB15BBAB786D46EA5710C3AB5BCC4EE6A7B7050BB853D38C69CC45FDAD4500E0D21B5B551B21F07B55BD883239DDF79ECBE168FAB4B82ADB46D5CBE744DDC67C3E19C80C562C2D26E7F5FD86783E91DE426B1CE49CB81A6E720E5201D1F76B866D9B16F6C94E58F74FF0A693950BD8495D48571BB0DF50D4DCC0FD3BD2CA81F96D625EA8785B65ABE5F8914BA3F8890EEE6213B7CA6BEAAE7719E1DAFAA5E82D6B3F2BD04A470BD44A5DD5C2FF1747A09764F1E1C14EBDCCBA697286FEF5C2FF172F02AEB25A23E1392D93C4E9D3852D576AE97A8B49BEB259E5E2F619B0C8975EE65D24BD0E395E5E547EB1871BDC4F79EEF835E4260315C39C62DC0F5124F6137D74BEC8950E75E36BD04BDEF096D95EB25BE5FECA797789EF3F9D27D3FA4EBB23F0D875D47A41A8F6B97745CDB60326233B5FC44F14BF3F430764BDB4EF239EC0B7E50BB23F3D34F6DF761EA5285DD4FB98E56E100B6BECCE570D0B44979DE6B4171F6873E930D0CF48BE31223262D0C3607F3B5744FC03183A64A596EC260B06171AE72FF793A0F40E3CBA453501ACC48AC246026CFAAB48D0AD791DE83699F7940AE824E39083B79168BECA6A77CCF0C36EEA677B0F9375A5FE42A03AB530E53F17D4F368EB6BB06E1D47C84DC2F2AE700290AC97362679F8A8D01D3E340280197AE38163720D7C06CB522BF99853F9C84463E88E06CD1B7086319C27E0803832AA4E241360F45D34DE7E61EC49661325BA157F7B17507E51A23B38FFA07F7D41CD4BB7B7E4F7A033090FB9BD36A62735C347CF99E67146939087B711AD543585D4DB2793A59FF20EBEF489F25EBDB86919CAFBE3760B9DD89D02C3B1E26654AE7E6D69663189DF08AC74238FA0C2CB5DB336213D32DB5BBA7F32E6BD752BB179792E25EE752BB69FE1CC46E97DB079BCD8039BF8FBDD72C1CD3FFA46B4652BB654D5F57B55B7877F8717589D611610D4B697B980E2E606CC482F4DA43F60CA05669D95C230D332FE9833E4939186D6318B315C780A749FDA5E312F43E4EF3677060407C0F59280769DAE8DEABCB0FD7C47943216D76B6462DC9C3A95992CEE238C67EE324D23523EFDFBF8FC216DF53E9BBE4B0EB4B50DD503EB705D940F5F78585F00B4BCBD00C2BB1BCB450719DF2F3A56B4AEC75DE5EFB0F087B47D03D33E87F1D5DDD18F52DA1905EAC884358EF9F226D07744D0A614D09E91E1ED2F525E83E24C29A14C2BC58539B465C235C48B75E6F60E3D2EA817B15E9A6EB10C49319B69780B0A6847978605FBBA5E5209D1793CED3D1FFA46B02D03D1D829E91AAF195DB2DACC1E099F48A6B4A48D797A0FF096B1948ED16D6982FB7BBBDAD724E52BA87C293D8EDF1F8C43525A4EB4B508DC4B3DECB82D611E9DE1AC29E10E57B6B086B64B0F346FCC8A7179EA81C66C319F89D5A689D7E64A3B3E4DEA52D5D5342FF686DF7F2F52E84B6235DEF42BAB70B3D8FAE7761B116FB25E5EB8E4891AE3571B3A587AF29F11D23B4037A8FFDE25C0DBAEEDE62E38C75E7CF43393A03B7B65283E927CF908ADEEADA4C21BE41BD0B6D5D6D70E9074B7EAF76FE5EF3B952A46D4747DA8E6AA0B8FF804AE7C06A7A55DCEBFDD4F95A1287B1EA9EB4C29EE1E5507D05DD8322B73A2FEEE16121F705C10F5B4617585BEF374CB3364AE72AA94EACA6A691F961BA566ED7BD623B365AEDA4BF6745CB8D3AD63769523858BA85F5B5E99EBA740E6865350BBDC90AFFC4D89E76979783A013EB6B6F16756BB72F17B559D2F67F50A8DD542741FB9323A30EA691482C2DC2E70F89C7F4BCD53C6DFF1D2576533F4CD3576EF7D7172E30ED5B89DD92B5BB0F6237CDB712BB9D6E9C3E7E02BDC44752BD84702CD82DF8E183B2575D12EA082D63697BA0CF419DDDFDE459C680C47CA064AE9186A17D01E3EE7DE5B0E56034F9893F8E2196DB46D06A2CD14864D319E687E91E0DD27290A62DF7D04FDA801926830E1EBBBD624F81FE4135D49AE29CF841FDB07264166DB5675F883FFA2142C7259AEE36EE8E171C2C0CDDFF7BD46C22F5F77EC57F0FA231A8D5955A43AA7D686BBB51F13B7D466C6A6D874BDBCDBEAFACAE91E7D4F6AAE7518DA5A1AF993D4B7E59771BF130E92F917EE1EDA63636CF7FABA583FD37EE9C81893C536F57192714F62194FEE69A4F90EBF7B17DE6655DEDB8DBDACDF6F048C416E09E4F42D6D90CE76851EF2E7DF783D2DE6D617E38B753BA17BC14E9FEF1CEC9EAE748FDD9E3A03E6AA8F3515B6A6F2EF6BBA5DAFB8320D83D60F220EAB3C236E67AA4910884C463E17CE19D15C16EBA6FE1CE53DA4D6D69B85EF3547558BAC7E641D8AB2EDDDFD5DED13A222DE36A4CC536904F15C7CE428BABE41EA3435BD38D272A073A86231B1AC2D0908CAD4D79AFB1896924687ABA7B87D1DC74171AF5236D91B41C1E97364AC780022A55B12F247DAFA43C0D7BEDB1C9E170381C0E87EB25CAE17A89FDEDE67A09AE97E01C8E27595F82BE9B40DF1FA07B0A96FF27BCBF4EF512D48F52BD046D53EC9DFBDDEB94EB2584F529E87FD235294AAEB97B9E7DF7DDF8F275008AEB2214E30D86E3E439B3BAFF928E4B04828BE27BF3744D0A614D097A1D8FB3387F5FBEA684745CA2B89E4380E95D85F513A86E20BB95C798CB018B5EC9E6BBA5EFF7C79219CC783D240F0B8FD69408042BD66628B75D2807E97A0EC27B1CC2FA12D2E7E1FABBF791CF2C55CD8372BB85F6E77F1015D79490AE2F2184139E8705BBE93A16D2B53404BB87E57D156B646CE60B6CFFCE72BB85FC799CDDABA98CB8A684747D09FA9F745C82DAFDB835251E5797847189F2F640D72A9BB0DBD8BB1BF43C618D0C56E7A209241351313D872D07699DA5FBC1096B4A08F953A297D85DEF42485BB5F52E68DAA4EB5D08EFA41C745CC2ED9EE46B4A7CC7BC4A7A09DA770FF9A631241B21EDBFB2BE71BD04D74BEC5797843A7218BDC4EA16B9372B7A61319B9FA81C9EB75E42BAF70DD74BBCBCBC6A7A899E5E05AC4A3ABF54F9AE10D74B54DACDF5124FA797987E98C79DBA2F30E11A79A27278DE7A09D61677D7CBE07A89979357512F71E3464BD5E75C0AD74B54DACDF5124FA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F53D44E7C72F20CB60B39D8ACD6128D45DFBD1BF8F4D32FF0D77FF22312DFB7ECBF0B477E8DD5C4125AEE6BF0FEC79FA3BDEE539C3E750B9F7F720A172E5CC4A4AABD240D7AAD413C16D66DB78C2E60672B8670348EF6AEFBD8C995EE1346D7791FEC1FC2EA5CB16F2C5D7FFCD4F5068CE8B4C86E64F1E1F15A7C7DF52BF84DC3C5BD1A0654D0AB7470CCADA2EF6E3DDA1AAEC13C19C6A8660037BBE46C1F84867B5D50F4F6B0F0D26B4AFBE4D27DFDCA892E6FC06223F716E2571732FF81E87818EBB96D6CE7F3306AE7493E17900E4670B7C54BE28AC0A09C83CA1822368488FD11B606AE511BC295263F76D229F65F497EED7E3718A2E4FEF4EF4867722C6EE939C96C1EF2BE83AF23CFE1705E1C741DF873A4CF38D47213329D836927EACE9D277E26811E8555D44E2C4493387FF61C8CCADE128D4581F4532FD63661A0EB168BAFF6462386870631D4DE8CD18979A6CB48C5E7517FA313972E9E456D6D2DF2D944491A541A1DF3F15E8F5BF4C33AED08F131390C107FE8F5CC93DF4AF78B14F6FF51ECCE1D4AFD70BF518FF9C52896426174135FE4B65BA1900DA2A1B91FB30EBDB857C3F5B6FB701BE5C40FC73174E76B7C74BE99F961BA5F4D94848F90F0D26BEEE78747BCEB50AB4388792308C736603545E11A8DB2FF1C632B18948750D8D8C4DDE629980CE41E53F837CC2DAC93E3452457B29069239069E6896F2D8E098DB992B019E87E3CDBA8B9EA64FE9AFADACDFC7F40AB2C9E43FDB5D910867ED8CFE21EE8F56368A0B85EF81AF1FBF7BBAAEFB1C2E17038E5D0FD222C2603BC2E1B4C5627DB475AD833C3E67461B89FEEADF0C80F0BFB7ED07D3B647DBD88C7E2E23E24745CA27F60003A1287CFE38566A00FA148021ABDB664AF06BA6746635B270AE49E301558C282CF058B73064B8B01169EFA5ADF78F5FD21ABA176A470FB961B5EEBDC9EE724D3799835F387CE9F50B8741F1CB7BBFADED1572F3B70ED1A1F3BE770381C0E87C37952B85EE2BB83BE33633647D978838DB099DE7A6671D3B1E8BB8D9348278BE3DB775BA7C5E37DC36DFE3B0CA63042730FC5B4999F41DAD873C06E5CD3EE38BB8ED91687C7157EAA78399C5785EFAB5E421A4639E663EFF4D13D2A05ED04F5D7369D064DADED45ED8342F59DE9253A07E6108F65D1DAEA432EFFEF30191EC04848A5FE05AD77A7303A9B617A096998D8F2BFC06A8B6072AC38A63C36F610B2D6E27EAFA3E3718C8D44905EDB442C994313F1B19150AA443B115DFD96692CEE364D22BFF9AFB8593F012BF1A9C1D904BA3B66C5631AA653B60855DF144B8F6C601AF76541969E09DF436889AF540FF84AD226D57CAC25D6611F7FC8AEBB9EDAC06C200D0B49F762E061897E23BFBD0D8D7A0E7AE26F63A1D2B1747A1D9B2D8CD62617961FFE0BF1C961F8BD312425E9A1BE9FDA4DF5244BD1145CC1FF0F9DC46E7ACD095FAAC4569D6909EA5D3D89343D42189A57E56544F524A9B0E785B73F0E87F27DD54B48C3D07DCF9BBEBA806CBAD8BF12E6ECE85C9BF4F8BBD24B0C0CD331E06DA66BB02F7C8BADE832C61EFC2B361EC4C87F01512F210DA3637372F4B3A885D00C07A1312FA1B0B585BA2B4E688C11CC8C15C30CF5F91FE583F1D13EC35463D172BBF8AC30D05B7CCF71D4BA54724C3FA5D7A7E9A171D0EF1672AFA063EFEAE1D2E7A172CD87F4BAD2744BF51BF4B7DADB53B0A8FC15F943AF433F95E43A034341D64FEEEBF0627B6B534C0FFD9FDA2DE849D2E4FBC8AEDDB144AEC456A99E449A1E699872A89EC4A55357FD8FC3F9AE0925B238FED9717C73E633362EF19B5FFF0A9F1E3D8179EF08BEFEA61967CE7C81C482072A83135F92FE70E395736C5CE2D807EFE146CD196C65134C2F5177FE18A8EFF9E0540D4E1F3B82C6AFBE607A89E39F9F26FE438D0F487FF8AD7FFC157EF3F6DB580B4F95A441F0A974DE4DF0C3460BE993E5D3686FBD479E652750BE87BC348CE88793C53628D54E488F0706B5B0A9E44C2F41C705FAFA8760940F30BD84ACE92B1CAD6D2DF5C3E94CC935F7F3C3A1D8B798994922135B435BF71CE90B86E0342D30FF683191FEB035CCFA9FD76F4EA2BF770E85EC464978DA1F1E1925FD61F712EBF30E754FC1319B86DB10808AF4F5D4DA45E4529B48ADFF1BEEDE9E84554D7DCF7F883E8BC23416FA79E62F6F5C77C26A58607DE09B4D5EF198EA2D7A75716CC41EB2B8AED7BBA0199861E9A1FD5403F17BB2CED27E22ED0F6B950FD04CECCAA7D676F3B578DD00ED7F3A48FF737E15CBA97F8399F8C79E7BC57546A87F345A63882D96F64785FEF09D9BE3985B4CC3A45D80C71E21E9C98BE961E189DD544F120EACC217D9404F23E9FB3B63D8223688B66EFE3B6A2E91E7226794DD23A4E911C2087935E55E8167778E73796B1B6DB5675F78FBE3705E160EAB97280F63F791F6AE91C34AFA37745C826A27628B415157418FA93EEF45EB259E35D4A776DF3BFCDA4A81C8BF20B7B6FEC4D79D26CFFBCED1C57DCFA1F7393A2EF15DE443B99E642FB89E84C3793A5EB5793A0E87C3A946439F0DEFFDFCCF1EAB97F8F97B67D0D770F285A7F765E5D265D781F4090725995C7D667171389C970FAA97F8F8FDDFE3A3777EC9E6E9FEF6CF7F82A3C74EA2BFE32EDEFDDD474C2F31A697A3E6467B895EE2E83B6FE0FDB77E8B3EB9126FFDF2E7F8939FFC1481C018FEECE7EFE1177FF5674C2FF1CEC7E771F4C469BCF7ABFF8ABFFDBB2378FDEFFE116FBCF99BE23E1E923438A67CA2F6A1A9A59BE925B4C36AC436B6995E62A053869D7CE9586DB7C90759DB65DC6B68407A3381DA4B35E27B1C35976AA1D719A153AA71BDA616F75426C85B5B70FEEC796C6E6DE1EBB36751DF708BE9256AAE37C0AEEC60611A7B35585FB03D759E76B4CF307D82491940B6B083DE7BD3C5F525E6D730AC0D89DA077F689DA47B44D43ED063AA7D288FAF79C80E9FA9EF85D7150E87F37C70CCAFE2A77FFC87A83B7D1C0AE722DEFFD5CFD03DA0404DCD05FCCFFFCBFF86FFFD3FFD2114CD5FE1F32FEB60D42971EB9B4B38527307CD973EC36FDFFF04E3B621FCC55FBF853FFA5FFF27125F1E1F9CBF81777EFE3368655D6893D9F07FFCE18FD07DED33FCE69DF3F8E5DFFF0A6FBCF126660CA5BA35A3C6F8E878779ECEE6086367238C119B1D0A851C3B85520D2BBD67A4836664D769BFB350321F477D6B47BF020F261D6C6E6E40358C4995119D243DAD5D5D70ABBB60D61B71E16A3B3AEED4B2B9B913248C57A3DD37AFE87BDFA74E9D62AC847C7B9E77B7C58742EE5F613246B0BCF5EF983286E05DD880CBB78A73E746D1DA3D87195B719E4B3ACFA62F5B474280BEA36C92F5BCF0BAC2E1709E0FDFD7F525043F2C7C97FA61BA3E843B92C18331333E3A5683446689F9E1F05A0E17489FB8908DA24FA68391F8E77F7EF73DE687E99A142EE324DB6F6FAFBC3AE8FA1243EA074C9F109A2EDA29AC2F91DBD8C4986B856900E8FA12C57457F7C36CAD8821F27DFB5FB91FE67038CF9D7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8F2F84643C26E259960A0AE2C9145AADB1AF92DDE142AB5917B12DE3C9043C0E274E8F87760EECEBDBAC28A3B6FDC1C930CE65B521E25C26E8995030F09DF65F42E24DC2A78C63DCB17FADD166C3EDCF3FC3D6D60ECC7A3DC2E1180E0C4638ED4E2453499AFF4E584D86513CCBD9D93944FCDEA9777029E25BBA6C3018CCA8A6C6F635368B75EAF7B93DD3C0712E93413B36D677F1F2C5D15B1F1709896F8A72318F527B38778F09D51BC49C54E18D2B57D6BBAEB07B9D443257C1497FB886D9AF37E077BDF5719090F84D717CD89B2A2524247E7DB4AB2DF42AF951A9D6277446045735882ECD23B9BD8D7EBB8B8C4E8B98661F49CD26D2AE08EA1E330ADE008AC4AB65BD091CB7C7FE16914DADB8E676854004F9833DC4355AF89E3E47C9ED40DA601CB56DD53B082DAF216372A16037A0954BC3F77886EE9D89FB47DD1E820B8BE8110D39770027CD616C974A34818C7E680F5AF07A30189CA19D08E2B0DE44F0C92334724551D6F375515F578A68C7DC28F8822879C7B165A23B7B68112F9AB3BB508F469030FB70D4A821653C40339D78EBFF2389770B399B132F4F8F4725D71522452437E660BD370BFB175FD21AB0C27AE721143BAD85AD45B1BEBC8F9F20EF0C4021392AE770C1F5E9BF8DDE19DA31886B6E975A9B87F197B7E0F8E213986E3F44626516693DAFA793517BEBEDCF11DDD844C91F422D1E4323114335E01EDD8FAC0DEDD78B8110DA99E11CAFA5F248D97C38199CD07A0AE2B45B8772B08FA3DE31420BCFD1A9B444797CF27258DF3944D668429EDAE65D635BF976A18482DB8DACD58E82C78DC34613AD901B2992F926D79D84C44D707A4A6740B33E2ADF363D57A17B1E6FAC5D28E3C5F1584FD156F238393E45C947EBEAB033AAEFD51B5325E34C5C0FFBD72D14C6FD3F3943375FA0FE9FE1A85EA5F21483761B836E1F47B5EAB7D21F89DF4EB4F2A5A9725C5F4499E6683D9140239DC321CDAB7EA34A7B7E0D1D25336AC7D7BD6A09F5649AE676019D7C8ECE978498DFBD733FC117672FE93D31C1B7750A793493091CB55A38A67384DB754A2554CFF5E3BDEA783D1FD61AD4BE886EB98C5A348A5EAB83E0D327E0F8997CFFA8D3C761B924D61397EA737C3D683545F9E2B88FC1E100A7B4D6F87C3A3DEAA353ACE0E5D929ADADB6388F99F6C3621E957094D6D1D0EF89F716A68DAFF9FCE2F6E55004A7BD2E5ABF868FB0C4EF0678CF2E791CA352ADEFF74F91B35A880FF223F0F401BAB516B216B3B897B54CFBADD67C2E1CF64E70DA2EC1F77C0D81E74FE17AB080C37C7CD4A6148AA11E0B23B4B281E4AE0681E52D74B249D18ECF90ACC54ABFEF454AF081C3F5C2733A30BF88BC83F830A783E6B30F85781EADE0587798D4EA8947F3120F17C3D960783E896BC79057CC5AADE8116D25FBC1A8BE53AE111FB8804ABA884E268A56A38F56D843F5B467D42BA37737E9ECE36BF5B99C3B8CC131FDE68E0E2FBA326EADC4D5284753C4E7944725D71D934C92DCD912BC5078618ED613C91E34D78B3E377C0B6B7879328C5750F40749BEBA4F67570519ED0EC22BAB88ED3B90D0EE23B5BD39FA0D211785C3C839FD422E52CC26A449DE4FEC9BC5DFC97D231AA904AD2DD6699C8D9E0BEF1E10DFD5A633A520CE9A969213E715DFE3732F636379A787E8F61EADE7A19E9FAF139A0DE211EBB46E96CEF9BC2AEA993CB207063A7BCBC81A8C747E9DD0F9D3A0BED5A9DE8466AE888263BCA754A31971AD38BC28B8ECA8640B62CFC83B3D68A6A49E42E232DE84BE9CD75EEEC0F0CAFBF55C19DD4CEC46EFEA7C836F5FBF0BE8C8F8EDEF145EA52FCF87B3082F2EA21EF420B1B146FBBF16399B15F13D13DAE910221B5AC43737E8DA2CE4A784C1827EB570E56F9CD239E27DF804ED4C1A29D3015AA53C82B38FD14C27115C5CC761A522F4E12F063DC4B7396FE7F07CEA36FBC899F4C8BB7D083E9FC36175D88EDB336D93E7D824CAF138C95B212489D630F17539BB1BC9ED0D14020134334971BE94E88C4CD1D9189A9B43607143E8FFD4E7B34E27BA446354B38BCCBE8E7E7381E4BDA6289B4A55D05E4FA550B0DB51763B115DDF24B96CB81F2576F711251EB4950C10DF3B4F6769098A6E53E8F023CB0B2807C2C8F273A982A81FD17C5E5FF004D0484447B437CA2DF44B6379356BF5A0958E23A677D1B81705ED15BF1B96FB8B50B46B578EC7218D636C7D0DAD540479AB1E6592170BC4BB57FD3ED197108D2DD31C595A87E7D10C4EFA4DD127961BC30BF3623C4BD4F6E5D9C995EF979846CE6A9D2A47F5168B90610A24BF14E3659A5BFB6814AB88AF2FD2DC8C21ADDD42A3D422D9C6486DADA2BDFA6C359A10BA09F53AB6A3257E2F8A52308612CDC13CB56D2B1921BBBCA0FF1FCB2617E962B9A7427C56C14FCF799CA25DF6DC4E293B61AFD46B7684EE80E3708975586D22AD3F403DABD01C99453591455AA7A5B55012BC25CB4505B70DE5609C64C367E21B5A25E81BD34EED99C682D345729353F0A2B558409495445CD0DEAD9468CEEB89EF8BD31C7C3CD22D160234D7B7D7E93C8E8B6F022FA82EB4CCDF1788F75C5E412D1943D6E6C271FF58D41FB5CFF58D95AAA8CFF933C8EBD6C499CEB45F1C13965D156AD7A9D670D22808DAEBB4FEA25B3A648DFB53E3DFAF8D65C1A4DE4CF26B44C8C3D55000E1F52D74E9FFC37D49E80E04CD956000CEC7CFD12FE7459F4E8F8F91331AC578E69C5E1C55A5AEF326789DBE7CD0E96070D817F2CB9BFEED5EA32D74666DA1737BFDFEC7BA466ED748A5DFC8EF772ADFDEF7011EB76FF5FFD6FBF573DAABDF0DDE761F242424242424242424242424247E3751CF16717672342AD57AD6DBB25EB95B2CA0954AA2533F1436AAF58C8282D584ACD58B763A0285DAB45209546329F4AA65D46249740B79E4CC4EE4CD26F1AE76B58DD48E069530B577B9D0291791B7DA50F6B851F68770586B22A5D3A1536908FD38DBD0BDED719190F8757195BEBC10CA20B6B502E79D07F03FBE8776BD83927547DCCB9AAD68961BA838694D4433486CAF21BCB64DEB48817F7E05B1D5795A4F2E441697447BD61B1A7FF539B207465AA36EE4DD5614ED4EC43637E1BCF70865AF0D59DBD0B737B8BC8DCA845DB984C4BB864EAD25EC8CD492EB7AADAEB05DE533496DD7AFD5848D4FD135F4A59DB465E8B52FEBD2CBC1CBDF945E75BF9A2ECAEF851212121212121212121212EF342AA1EB65A03709F6EB633BBCFE05FD5E2D9112B6B2DFE45DECBBC8EFAA85659E3189EF0EAFD297AB886EEFA2160AA15DAE089BED6676A83FCFB942682502427FCEA5DA3E63B20AFD79DAE6413DE4117A75B63F2FF9C318745A28F803686432A845E8F9645CE8CBDBC5BAD09F1FE6863E45C7276728FABD68E5F248EC9991DC37A060B3A395CD23B6A511BEEF6CEFDC2E1491D5EB842EBFE273116D0A6AF110AAE9023A4A6A4453DE4DBF918DA39ACA091DBF4A33EBF8DB4A76A4E34F1F9871DC19FAE7B2CF14DBBBB2CE52A5B91CA47707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- diff --git a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_12_10/Verilog Netlist/debug.log b/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_12_10/Verilog Netlist/debug.log deleted file mode 100644 index 8fa3f63624..0000000000 --- a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_12_10/Verilog Netlist/debug.log +++ /dev/null @@ -1 +0,0 @@ -[0617/134102:ERROR:dns_config_service_win.cc(750)] DNS config watch failed. diff --git a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_12_10/Verilog Netlist/sc_block.v b/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_12_10/Verilog Netlist/sc_block.v deleted file mode 100644 index 905ea996b3..0000000000 --- a/DesignDatabase/Testcases/Switched Capacitor Filter/switched_capacitor_filter_2018_12_10/Verilog Netlist/sc_block.v +++ /dev/null @@ -1,196 +0,0 @@ -// Verilog HDL and netlist files of -// "pcell switched_capacitor_filter schematic" - -// Netlisted models - -// Library - pcell, Cell - cascode_current_mirror_ota, View - schematic -// LAST TIME SAVED: Aug 30 07:09:12 2018 -// NETLIST TIME: Nov 13 07:44:10 2018 -`timescale 1ns / 1ns - - -module telescopic_ota ( Voutn, Voutp, Vinn, Vinp, Id, Vg ); - -output Voutn, Voutp; - -input Vinn, Vinp, Id, Vg; - - -specify - specparam CDS_LIBNAME = "pcell"; - specparam CDS_CELLNAME = "telescopic_ota"; - specparam CDS_VIEWNAME = "schematic"; -endspecify - -SCM_CMFB_NMOS_50_1x12 L1_MM4_MM3 ( .D1(Id), .G2(Vg), .D2(net6), .S(cds_globals.gnd_) ); -CMC_NMOS_25_1x10 L1_MM10_MM2 ( .D1(Voutn), .D2(Voutp), .G(Vbiasn), .S1(net10), .S2(net11) ); -CMC_PMOS_15_1x6 L1_MM7_MM6 ( .D1(Voutn), .D2(Voutp), .G(Vbiasp1), .S1(net13), .S2(net12) ); -CMC_PMOS_10_1x4 L1_MM8_MM9 ( .D1(net13), .D2(net12), .G(Vbiasp2), .S(cds_globals.vdd_) ); -DP_NMOS_75_3x10 L1_MM1_MM0 ( .D1(net10), .D2(net11), .G1(Vinp), .G2(Vinn), .S(net6) ); -//idc I3 ( .PLUS(cds_globals.vdd_), .MINUS(net1)); -//bias transistors -DiodeConnected_NMOS_5_1x1 L0_MM17 ( .D(Vbiasn), .S(net6) ); - -DiodeConnected_PMOS_10_1x2 L0_MM11 ( .D(Vbiasp1), .S(cds_globals.vdd_) ); - -//DiodeConnected_PMOS_20_1x4 L0_MM13 ( .D(net_vbiasp), .S(net1_vbiasp) ); -DiodeConnected_PMOS_10_1x2 L0_MM131 ( .D(Vbiasp), .S(net1_vbiasp) ); -DiodeConnected_PMOS_10_1x2 L0_MM132 ( .D(Vbiasp), .S(net1_vbiasp) ); -DiodeConnected_PMOS_20_1x4 L0_MM14 ( .D(net1_vbiasp), .S(cds_globals.vdd_); - -Switch_NMOS_10_1x1 L0_MM12 ( .D(Vbiasp1), .G(Id), .S(cds_globals.gnd_) ); -Switch_NMOS_10_1x1 L0_MM15 ( .D(Vbiasp), .G(Id), .S(cds_globals.gnd_) ); -Switch_PMOS_10_1x1 L0_MM16 ( .D(Vbiasn), .G(net_vbiasp), .S(cds_globals.vdd_); - -//dummy transistors -DiodeConnected_NMOS_5_1x1 L0_MM18 ( .D(cds_globals.gnd_), .S(cds_globals.gnd_) ); - -endmodule - - -module non_overlapping_clock_generator ( digital_vdd, digital_vss, clk, phi1, phi2 ); - -output phi1, phi2; - -input digital_vdd, digital_vss, clk; - -specify - specparam CDS_LIBNAME = "pcell"; - specparam CDS_CELLNAME = "non_overlapping_clock_generator"; - specparam CDS_VIEWNAME = "schematic"; -endspecify - -Inv_3_1x1 L1_INV1 (.VDD(digital_vdd), .VSS(digital_vss), .IN(clk), .OUT(net5) ); -Inv_3_1x1 L1_INV2 (.VDD(digital_vdd), .VSS(digital_vss), .IN(net2), .OUT(net3) ); -Inv_3_1x1 L1_INV3 (.VDD(digital_vdd), .VSS(digital_vss), .IN(net3), .OUT(net4) ); -Inv_3_1x1 L1_INV5 (.VDD(digital_vdd), .VSS(digital_vss), .IN(net6), .OUT(net7) ); -Inv_3_1x1 L1_INV6 (.VDD(digital_vdd), .VSS(digital_vss), .IN(net7), .OUT(net8) ); -Inv_21_1x7 L1_INV4 (.VDD(digital_vdd), .VSS(digital_vss), .IN(net4), .OUT(phi1) ); -Inv_21_1x7 L1_INV7 (.VDD(digital_vdd), .VSS(digital_vss), .IN(net8), .OUT(phi2) ); -NAND_1_1x1 L1_NAND1 (.VDD(digital_vdd), .VSS(digital_vss), .IN_A(net1), .IN_B(net8), .OUT(net2) ); -NAND_1_1x1 L1_NAND2 (.VDD(digital_vdd), .VSS(digital_vss), .IN_A(net5), .IN_B(net4), .OUT(net6) ); -TG_3_1x1 L1_TG1 (.VDD(digital_vdd), .VSS(digital_vss), .IN(clk), .OUT(net1) ); - -endmodule - - -module common_mode_feedback ( Vg, Va, Vb, phi1, phi2, Vbias_in, Vcm_in ); - -output Vg; - -input Va, Vb, phi1, phi2, Vbias_in, Vcm_in; - -specify - specparam CDS_LIBNAME = "pcell"; - specparam CDS_CELLNAME = "common_mode_feedback"; - specparam CDS_VIEWNAME = "schematic"; -endspecify - -Switch_NMOS_10_1x1 L0_MM0 ( .S(Va), .G(phi1), .D(net1)); -Switch_NMOS_10_1x1 L0_MM1 ( .S(Vcm_in), .G(phi2), .D(net1)); -Switch_NMOS_10_1x1 L0_MM2 ( .S(net2), .G(phi1), .D(Vb)); -Switch_NMOS_10_1x1 L0_MM3 ( .S(net2), .G(phi2), .D(Vcm_in)); -Switch_NMOS_10_1x1 L0_MM4 ( .S(Vg), .G(phi2), .D(Vbias_in)); -Cap_30f_1x3 CC10 ( .PLUS(net1), .MINUS(Vg)); -Cap_30f_1x3 CC11 ( .PLUS(Vg), .MINUS(net2)); - -endmodule - -// Library - pcell, Cell - switched_capacitor_filter, View - -//schematic -// LAST TIME SAVED: Aug 30 07:08:50 2018 -// NETLIST TIME: Nov 13 07:44:10 2018 -`timescale 1ns / 1ns - -module switched_capacitor_combination ( Vout, Vin_ota, Vin, phi2, phi1, agnd ); - -output Vout, Vin_ota; - -input Vin, phi2, phi1, agnd; - -specify - specparam CDS_LIBNAME = "pcell"; - specparam CDS_CELLNAME = "switched_capacitor_combination"; - specparam CDS_VIEWNAME = "schematic"; -endspecify - -Switch_NMOS_10_1x1 L0_MM0 ( .S(net3), .G(phi1), .D(Vin)); -Switch_NMOS_10_1x1 L0_MM10 ( .S(net3), .G(phi2), .D(agnd)); -Cap_60f_2x3 CC4 ( .PLUS(net6), .MINUS(net3)); -Switch_NMOS_10_1x1 L0_MM9 ( .S(net6), .G(phi2), .D(agnd)); -Cap_30f_1x3 CC3 ( .PLUS(net6), .MINUS(net12)); -Switch_NMOS_10_1x1 L0_MM11 ( .S(net12), .G(phi1), .D(agnd)); -Switch_NMOS_10_1x1 L0_MM8 ( .S(Vout), .G(phi2), .D(net12)); -Switch_NMOS_10_1x1 L0_MM1 ( .S(Vin_ota), .G(phi1), .D(net6)); -Cap_60f_2x3 CC0 ( .PLUS(Vin_ota), .MINUS(Vout)); - -endmodule - -module switched_capacitor_filter ( Voutn, Voutp, Vinp, Vinn, Id, agnd, clk ); - - -specify - specparam CDS_LIBNAME = "pcell"; - specparam CDS_CELLNAME = "switched_capacitor_filter"; - specparam CDS_VIEWNAME = "schematic"; -endspecify - -//vdc V5 ( .PLUS(cds_globals.vdd_), .MINUS(cds_globals.gnd_)); -//vdc V4 ( .PLUS(Vinp), .MINUS(cds_globals.gnd_)); -//vdc V3 ( .PLUS(Vinn), .MINUS(cds_globals.gnd_)); -//vdc V2 ( .PLUS(Vbiasp2), .MINUS(cds_globals.gnd_)); -//vdc V1 ( .PLUS(Vbiasp1), .MINUS(cds_globals.gnd_)); -//vdc V0 ( .PLUS(Vbiasn), .MINUS(cds_globals.gnd_)); -//cascode_current_mirror_ota I0 ( .Voutn(Voutn), .Voutp(Voutp), .Vbiasn(Vbiasn), .Vbiasp1(Vbiasp1), .Vbiasp2(Vbiasp2), .Vinn(Vinn_ota), .Vinp(Vinp_ota)); -telescopic_ota I0 ( .Voutn(Voutn), .Voutp(Voutp), .Vinn(Vinn), .Vinp(Vinp), .Id(Id), .Vg(Vg)); -switched_capacitor_combination I1 ( .Vout(Voutp), .Vin_ota(Vinn_ota), .Vin(Vinp), .phi2(phi2), .phi1(phi1), .agnd(agnd)); -switched_capacitor_combination I2 ( .Vout(Voutn), .Vin_ota(Vinp_ota), .Vin(Vinn), .phi2(phi2), .phi1(phi1), .agnd(agnd)); -common_mode_feedback I3 ( .Vg(Vg), .Va(Voutp), .Vb(Voutn), .phi1(phi1), .phi2(phi2), .Vbias_in(Id), .Vcm_in(agnd)); -non_overlapping_clock_generator I4 ( .digital_vdd(cds_globals.vdd_), .digital_vss(cds_globals.gnd_), .clk(clk), .phi1(phi1), .phi2(phi2)); -Cap_30f_1x3 CC5 ( .PLUS(Vinn_ota), .MINUS(Vinn)); -Cap_30f_1x3 CC7 ( .PLUS(Vinp_ota), .MINUS(Vinp)); -Cap_60f_2x3 CC8 ( .PLUS(Voutp), .MINUS(cds_globals.gnd_)); -Cap_60f_2x3 CC9 ( .PLUS(Voutn), .MINUS(cds_globals.gnd_)); - - - -//Cap_60f_2x3 CC7 ( .PLUS(net7), .MINUS(Vinp)); -//Cap_60f_2x3 CC6 ( .PLUS(net5), .MINUS(net4)); -//Cap_60f_2x3 CC5 ( .PLUS(net23), .MINUS(Vinn)); -//Cap_60f_2x3 CC4 ( .PLUS(net6), .MINUS(net3)); -//Cap_32f_1x1 CC3 ( .PLUS(net6), .MINUS(net12)); -//Cap_32f_1x1 CC2 ( .PLUS(net7), .MINUS(Voutn)); -//Cap_32f_1x1 CC1 ( .PLUS(net5), .MINUS(net11)); -//Cap_32f_1x1 CC0 ( .PLUS(net23), .MINUS(Voutp)); -//Switch_NMOS_10_1x1 L0_MM11 ( .S(net12), .G(phi1), .D(cds_globals.gnd_)); -//Switch_NMOS_10_1x1 L0_MM10 ( .S(net3), .G(phi2), .D(cds_globals.gnd_)); -//Switch_NMOS_10_1x1 L0_MM9 ( .S(net6), .G(phi2), .D(cds_globals.gnd_)); -//Switch_NMOS_10_1x1 L0_MM8 ( .S(Voutp), .G(phi2), .D(net12)); -//Switch_NMOS_10_1x1 L0_MM7 ( .S(net11), .G(phi2), .D(Voutn)); -//Switch_NMOS_10_1x1 L0_MM6 ( .S(cds_globals.gnd_), .G(phi1), .D(net11)); -//Switch_NMOS_10_1x1 L0_MM5 ( .S(cds_globals.gnd_), .G(phi2), .D(net5)); -//Switch_NMOS_10_1x1 L0_MM4 ( .S(cds_globals.gnd_), .G(phi2), .D(net4)); -//Switch_NMOS_10_1x1 L0_MM3 ( .S(net5), .G(phi1), .D(net7)); -//Switch_NMOS_10_1x1 L0_MM2 ( .S(Vinn), .G(phi1), .D(net4)); -//Switch_NMOS_10_1x1 L0_MM1 ( .S(net23), .G(phi1), .D(net6)); -//Switch_NMOS_10_1x1 L0_MM0 ( .S(net3), .G(phi1), .D(Vinp)); -//vpulse V7 ( .PLUS(phi2), .MINUS(cds_globals.gnd_)); -//vpulse V6 ( .PLUS(phi1), .MINUS(cds_globals.gnd_)); - -endmodule - - -// End HDL models -// Global nets module - -`celldefine -module cds_globals; - - -supply0 gnd_; - -supply1 vdd_; - - -endmodule -`endcelldefine diff --git a/DesignDatabase/Testcases/USC/Amplifier/Amplifier_1/Constraints/Amp_diff_norm_rvt.const b/DesignDatabase/Testcases/USC/Amplifier/Amplifier_1/Constraints/Amp_diff_norm_rvt.const deleted file mode 100644 index a13cde5db5..0000000000 --- a/DesignDatabase/Testcases/USC/Amplifier/Amplifier_1/Constraints/Amp_diff_norm_rvt.const +++ /dev/null @@ -1,5 +0,0 @@ -CritNet(net39, mid) -MatchBlock(MN3_MN0, MN1_MN2) -SymmBlock( {RR0, RR9} , MN1_MN2 ) -CritNet(ON, min) -CritNet(OP, min) diff --git a/DesignDatabase/Testcases/USC/Amplifier/Amplifier_1/Constraints/IBS_norm_rvt.const b/DesignDatabase/Testcases/USC/Amplifier/Amplifier_1/Constraints/IBS_norm_rvt.const deleted file mode 100644 index 8db4f7e7c7..0000000000 --- a/DesignDatabase/Testcases/USC/Amplifier/Amplifier_1/Constraints/IBS_norm_rvt.const +++ /dev/null @@ -1 +0,0 @@ -MatchBlock(MP0_MP1_MP2, MN1_MN2) diff --git a/DesignDatabase/Testcases/USC/Amplifier/Amplifier_1/Constraints/SCM_BANK.const b/DesignDatabase/Testcases/USC/Amplifier/Amplifier_1/Constraints/SCM_BANK.const deleted file mode 100644 index 2eb0f760d7..0000000000 --- a/DesignDatabase/Testcases/USC/Amplifier/Amplifier_1/Constraints/SCM_BANK.const +++ /dev/null @@ -1,2 +0,0 @@ -MatchBlock(MP0,MP1) -MatchBlock(MP0,MP2) diff --git a/DesignDatabase/Testcases/USC/Amplifier/Amplifier_1/LEF/BS_AMP.lef b/DesignDatabase/Testcases/USC/Amplifier/Amplifier_1/LEF/BS_AMP.lef deleted file mode 100644 index 06c2ea9d9a..0000000000 --- a/DesignDatabase/Testcases/USC/Amplifier/Amplifier_1/LEF/BS_AMP.lef +++ /dev/null @@ -1,240 +0,0 @@ -VERSION 5.7 ; -BUSBITCHARS "[]" ; -DIVIDERCHAR "/" ; - -MACRO res_3p83 - ORIGIN 0 0 ; - FOREIGN res_3p83 0 0 ; - SIZE 2.034 BY 1 ; - PIN LEFT - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M1 ; - RECT 0 0 0.018 0.018 ; - END - END LEFT - PIN RIGHT - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M1 ; - RECT 2.016 0 2.034 0.018 ; - END - END RIGHT - OBS - LAYER M1 ; - RECT 0.018 0.018 2.016 1 ; - END -END res_3p83 - -MACRO res_3K - ORIGIN 0 0 ; - FOREIGN res_3K 0 0 ; - SIZE 1.602 BY 1 ; - PIN LEFT - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M1 ; - RECT 0 0 0.018 0.018 ; - END - END LEFT - PIN RIGHT - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M1 ; - RECT 1.584 0 1.602 0.018 ; - END - END RIGHT - OBS - LAYER M1 ; - RECT 0.018 0.018 1.584 1 ; - END -END res_3K - -MACRO DP_NMOS_2x2_4x3 - ORIGIN 0 0 ; - FOREIGN DP_NMOS_2x2_4x3 0 0 ; - SIZE 0.864 BY 0.864 ; - PIN S - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 0.064 0.864 0.082 ; - END - END S - PIN D1 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 0.192 0.864 0.210 ; - END - END D1 - - PIN D2 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 0.128 0.864 0.146 ; - END - END D2 - -PIN G1 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 0 0.864 0.018 ; - END - END G1 - -PIN G2 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 0.256 0.864 0.274 ; - END - END G2 - - -END DP_NMOS_2x2_4x3 - -MACRO SCM_NMOS_4x4_4x3 - ORIGIN 0 0 ; - FOREIGN SCM_NMOS_4x4_4x3 0 0 ; - SIZE 0.864 BY 1.728 ; - PIN S - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 0.064 0.864 0.082 ; - END - END S - PIN D1 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 0.192 0.864 0.210 ; - END - END D1 - - PIN D2 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 0.128 0.864 0.146 ; - END - END D2 - - -END SCM_NMOS_4x4_4x3 - -MACRO Switch_PMOS_4_4x3 - ORIGIN 0 0 ; - FOREIGN Switch_PMOS_4_4x3 0 0 ; - SIZE 0.864 BY 0.864 ; - PIN S - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 0.064 0.864 0.082 ; - END - END S - - PIN D - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 0.128 0.864 0.146 ; - END - END D - - PIN G - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 0 0.864 0.018 ; - END - END D - - -END Switch_PMOS_4_4x3 - -MACRO Switch_PMOS_1_4x3 - ORIGIN 0 0 ; - FOREIGN Switch_PMOS_1_4x3 0 0 ; - SIZE 0.432 BY 0.432 ; - PIN S - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 0.064 0.432 0.082 ; - END - END S - - PIN D - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 0.128 0.432 0.146 ; - END - END D - - PIN G - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 0 0.432 0.018 ; - END - END D - - -END Switch_PMOS_1_4x3 - -MACRO SCM_NMOS_1x4_4x3 - ORIGIN 0 0 ; - FOREIGN SCM_NMOS_1x4_4x3 0 0 ; - SIZE 1.08 BY 0.432 ; - PIN S - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 0.064 1.08 0.082 ; - END - END S - PIN D1 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 0.192 1.08 0.210 ; - END - END D1 - - PIN D2 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 0.128 1.08 0.146 ; - END - END D2 - - -END SCM_NMOS_1x4_4x3 diff --git a/DesignDatabase/Testcases/USC/Amplifier/Amplifier_1/Netlist/netlist_BS_AMP.sp b/DesignDatabase/Testcases/USC/Amplifier/Amplifier_1/Netlist/netlist_BS_AMP.sp deleted file mode 100644 index 1f10e5055b..0000000000 --- a/DesignDatabase/Testcases/USC/Amplifier/Amplifier_1/Netlist/netlist_BS_AMP.sp +++ /dev/null @@ -1,222 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: UM_GF14 -* Top Cell Name: TB_IBS_norm -* View Name: schematic -* Netlisted on: Jan 4 14:34:06 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM wireopt=9 - -*.GLOBAL gnd! - -*.PIN gnd! - -************************************************************************ -* Library Name: UM_GF14 -* Cell Name: IBS_norm_rvt -* View Name: schematic -************************************************************************ - -.SUBCKT IBS_norm_rvt IBS_IN IBSn_OUT IBSp_OUT VDD VSS -*.PININFO IBS_IN:B IBSn_OUT:B IBSp_OUT:B VDD:B VSS:B -MN2 IBSn_OUT net7 VSS VSS nfet m=4 l=14n nf=4 nfin=3 fpitch=48n cpp=78n -+ ngcon=1 p_la=0 plorient=0 -MN1 net7 net7 VSS VSS nfet m=1 l=14n nf=4 nfin=3 fpitch=48n cpp=78n ngcon=1 -+ p_la=0 plorient=0 -MP2 IBSp_OUT IBS_IN VDD VDD pfet m=4 l=16n nf=4 nfin=3 fpitch=48n cpp=78n -+ ngcon=1 p_la=0 plorient=0 -MP1 IBS_IN IBS_IN VDD VDD pfet m=1 l=14n nf=4 nfin=3 fpitch=48n cpp=78n -+ ngcon=1 p_la=0 plorient=0 -MP0 net7 IBS_IN VDD VDD pfet m=1 l=14n nf=4 nfin=3 fpitch=48n cpp=78n ngcon=1 -+ p_la=0 plorient=0 -.ENDS - -************************************************************************ -* Library Name: UM_GF14 -* Cell Name: IBS_norm_lvt -* View Name: schematic -************************************************************************ - -.SUBCKT IBS_norm_lvt IBS_IN IBSn_OUT IBSp_OUT VDD VSS -*.PININFO IBS_IN:B IBSn_OUT:B IBSp_OUT:B VDD:B VSS:B -MN1 net7 net7 VSS VSS lvtnfet m=1 l=14n nf=3 nfin=3 fpitch=48n cpp=78n ngcon=1 -+ p_la=0 plorient=0 -MN0 IBSn_OUT net7 VSS VSS lvtnfet m=4 l=14n nf=3 nfin=3 fpitch=48n cpp=78n -+ ngcon=1 p_la=0 plorient=0 -MP2 IBSp_OUT IBS_IN VDD VDD lvtpfet m=4 l=14n nf=3 nfin=3 fpitch=48n cpp=78n -+ ngcon=1 p_la=0 plorient=0 -MP1 IBS_IN IBS_IN VDD VDD lvtpfet m=1 l=14n nf=3 nfin=3 fpitch=48n cpp=78n -+ ngcon=1 p_la=0 plorient=0 -MP0 net7 IBS_IN VDD VDD lvtpfet m=1 l=14n nf=3 nfin=3 fpitch=48n cpp=78n -+ ngcon=1 p_la=0 plorient=0 -.ENDS - -************************************************************************ -* Library Name: UM_GF14 -* Cell Name: IBS_norm_hvt -* View Name: schematic -************************************************************************ - -.SUBCKT IBS_norm_hvt IBS_IN IBSn_OUT IBSp_OUT VDD VSS -*.PININFO IBS_IN:B IBSn_OUT:B IBSp_OUT:B VDD:B VSS:B -MN1 net7 net7 VSS VSS hvtnfet m=1 l=14n nf=4 nfin=3 fpitch=48n cpp=78n ngcon=1 -+ p_la=0 plorient=0 -MN0 IBSn_OUT net7 VSS VSS hvtnfet m=4 l=14n nf=4 nfin=3 fpitch=48n cpp=78n -+ ngcon=1 p_la=0 plorient=0 -MP2 IBSp_OUT IBS_IN VDD VDD hvtpfet m=4 l=16n nf=4 nfin=3 fpitch=48n cpp=78n -+ ngcon=1 p_la=0 plorient=0 -MP1 IBS_IN IBS_IN VDD VDD hvtpfet m=1 l=14n nf=4 nfin=3 fpitch=48n cpp=78n -+ ngcon=1 p_la=0 plorient=0 -MP0 net7 IBS_IN VDD VDD hvtpfet m=1 l=16n nf=4 nfin=3 fpitch=48n cpp=78n -+ ngcon=1 p_la=0 plorient=0 -.ENDS - -************************************************************************ -* Library Name: UM_GF14 -* Cell Name: IBS_norm_slvt -* View Name: schematic -************************************************************************ - -.SUBCKT IBS_norm_slvt IBS_IN IBSn_OUT IBSp_OUT VDD VSS -*.PININFO IBS_IN:B IBSn_OUT:B IBSp_OUT:B VDD:B VSS:B -MN1 net7 net7 VSS VSS slvtnfet m=1 l=14n nf=3 nfin=3 fpitch=48n cpp=78n -+ ngcon=1 p_la=0 plorient=0 -MN0 IBSn_OUT net7 VSS VSS slvtnfet m=4 l=14n nf=3 nfin=3 fpitch=48n cpp=78n -+ ngcon=1 p_la=0 plorient=0 -MP2 IBSp_OUT IBS_IN VDD VDD slvtpfet m=4 l=14n nf=3 nfin=3 fpitch=48n cpp=78n -+ ngcon=1 p_la=0 plorient=0 -MP1 IBS_IN IBS_IN VDD VDD slvtpfet m=1 l=14n nf=3 nfin=3 fpitch=48n cpp=78n -+ ngcon=1 p_la=0 plorient=0 -MP0 net7 IBS_IN VDD VDD slvtpfet m=1 l=14n nf=3 nfin=3 fpitch=48n cpp=78n -+ ngcon=1 p_la=0 plorient=0 -.ENDS - -************************************************************************ -* Library Name: UM_GF14 -* Cell Name: Amp_diff_norm_rvt -* View Name: schematic -************************************************************************ - -.SUBCKT Amp_diff_norm_rvt IBSn IN IP ON OP VDD VSS -*.PININFO IBSn:B IN:B IP:B ON:B OP:B VDD:B VSS:B -RR9 OP VDD $SUB=VDD $[rmres] m=1 l=1u w=280n r=3.83529K sbar=2 pbar=1 -+ orientation=1 r_cut=0 -RR0 ON VDD $SUB=VDD $[rmres] m=1 l=1u w=280n r=3.83529K sbar=2 pbar=1 -+ orientation=1 r_cut=0 -MN3 IBSn IBSn VSS VSS nfet m=4 l=14n nf=4 nfin=3 fpitch=48n cpp=78n ngcon=1 -+ p_la=0 plorient=0 -MN2 OP IN net39 VSS nfet m=2 l=14n nf=4 nfin=3 fpitch=48n cpp=78n ngcon=1 -+ p_la=0 plorient=0 -MN1 ON IP net39 VSS nfet m=2 l=14n nf=4 nfin=3 fpitch=48n cpp=78n ngcon=1 -+ p_la=0 plorient=0 -MN0 net39 IBSn VSS VSS nfet m=4 l=14n nf=4 nfin=3 fpitch=48n cpp=78n ngcon=1 -+ p_la=0 plorient=0 -.ENDS - -************************************************************************ -* Library Name: UM_GF14 -* Cell Name: Amp_diff_norm_lvt -* View Name: schematic -************************************************************************ - -.SUBCKT Amp_diff_norm_lvt IBSn IN IP ON OP VDD VSS -*.PININFO IBSn:B IN:B IP:B ON:B OP:B VDD:B VSS:B -RR9 OP VDD $SUB=VDD $[rmres] m=1 l=1u w=280n r=3.83529K sbar=2 pbar=1 -+ orientation=1 r_cut=0 -RR0 ON VDD $SUB=VDD $[rmres] m=1 l=1u w=280n r=3.83529K sbar=2 pbar=1 -+ orientation=1 r_cut=0 -MN3 IBSn IBSn VSS VSS lvtnfet m=4 l=14n nf=2 nfin=3 fpitch=48n cpp=78n ngcon=1 -+ p_la=0 plorient=0 -MN2 OP IN net39 VSS lvtnfet m=2 l=14n nf=2 nfin=3 fpitch=48n cpp=78n ngcon=1 -+ p_la=0 plorient=0 -MN1 ON IP net39 VSS lvtnfet m=2 l=14n nf=2 nfin=3 fpitch=48n cpp=78n ngcon=1 -+ p_la=0 plorient=0 -MN0 net39 IBSn VSS VSS lvtnfet m=4 l=14n nf=2 nfin=3 fpitch=48n cpp=78n -+ ngcon=1 p_la=0 plorient=0 -.ENDS - -************************************************************************ -* Library Name: UM_GF14 -* Cell Name: Amp_diff_norm_hvt -* View Name: schematic -************************************************************************ - -.SUBCKT Amp_diff_norm_hvt IBSn IN IP ON OP VDD VSS -*.PININFO IBSn:B IN:B IP:B ON:B OP:B VDD:B VSS:B -MN3 IBSn IBSn VSS VSS hvtnfet m=4 l=14n nf=4 nfin=3 fpitch=48n cpp=78n ngcon=1 -+ p_la=0 plorient=0 -MN2 OP IN net39 VSS hvtnfet m=2 l=14n nf=4 nfin=3 fpitch=48n cpp=78n ngcon=1 -+ p_la=0 plorient=0 -MN1 ON IP net39 VSS hvtnfet m=2 l=14n nf=4 nfin=3 fpitch=48n cpp=78n ngcon=1 -+ p_la=0 plorient=0 -MN0 net39 IBSn VSS VSS hvtnfet m=4 l=14n nf=4 nfin=3 fpitch=48n cpp=78n -+ ngcon=1 p_la=0 plorient=0 -RR9 OP VDD $SUB=VDD $[rmres] m=1 l=1u w=280n r=3.83529K sbar=2 pbar=1 -+ orientation=1 r_cut=0 -RR0 ON VDD $SUB=VDD $[rmres] m=1 l=1u w=280n r=3.83529K sbar=2 pbar=1 -+ orientation=1 r_cut=0 -.ENDS - -************************************************************************ -* Library Name: UM_GF14 -* Cell Name: Amp_diff_norm_slvt -* View Name: schematic -************************************************************************ - -.SUBCKT Amp_diff_norm_slvt IBSn IN IP ON OP VDD VSS -*.PININFO IBSn:B IN:B IP:B ON:B OP:B VDD:B VSS:B -RR9 OP VDD $SUB=VDD $[rmres] m=1 l=1u w=280n r=3.83529K sbar=2 pbar=1 -+ orientation=1 r_cut=0 -RR0 ON VDD $SUB=VDD $[rmres] m=1 l=1u w=280n r=3.83529K sbar=2 pbar=1 -+ orientation=1 r_cut=0 -MN3 IBSn IBSn VSS VSS slvtnfet m=4 l=14n nf=2 nfin=3 fpitch=48n cpp=78n -+ ngcon=1 p_la=0 plorient=0 -MN2 OP IN net39 VSS slvtnfet m=2 l=14n nf=2 nfin=3 fpitch=48n cpp=78n ngcon=1 -+ p_la=0 plorient=0 -MN1 ON IP net39 VSS slvtnfet m=2 l=14n nf=2 nfin=3 fpitch=48n cpp=78n ngcon=1 -+ p_la=0 plorient=0 -MN0 net39 IBSn VSS VSS slvtnfet m=4 l=14n nf=2 nfin=3 fpitch=48n cpp=78n -+ ngcon=1 p_la=0 plorient=0 -.ENDS - -************************************************************************ -* Library Name: UM_GF14 -* Cell Name: TB_IBS_norm -* View Name: schematic -************************************************************************ - -.SUBCKT TB_IBS_norm VDD -*.PININFO VDD:B -XI34 net021 net038 net022 VDD gnd! -XI6 net013 net06 net032 VDD gnd! -XI44 net065 net059 net035 VDD gnd! -XI9 net011 net07 net012 VDD gnd! -RR8 net014 gnd! 3K $[RP] -RR7 net012 gnd! 3K $[RP] -RR6 net032 gnd! 3K $[RP] -RR5 net031 gnd! 3K $[RP] -RR1 VDD net05 3K $[RP] -RR4 VDD net08 3K $[RP] -RR2 VDD net06 3K $[RP] -RR3 VDD net07 3K $[RP] -XI22 net046 net042 net018 VDD gnd! -XI3 net015 net05 net031 VDD gnd! -XI47 net033 net061 net034 VDD gnd! -XI13 net010 net08 net014 VDD gnd! -XI37 net022 net019 net020 rON rOP VDD gnd! -XI51 net035 net066 net029 lON lOP VDD gnd! -XI30 net018 net030 net028 hON hOP VDD gnd! -XI43 net034 net062 net063 sON sOP VDD gnd! -.ENDS - diff --git a/DesignDatabase/Testcases/USC/Amplifier/Amplifier_1/Verilog Netlist/netlist_BS_AMP_part1.v b/DesignDatabase/Testcases/USC/Amplifier/Amplifier_1/Verilog Netlist/netlist_BS_AMP_part1.v deleted file mode 100644 index 07ad48837e..0000000000 --- a/DesignDatabase/Testcases/USC/Amplifier/Amplifier_1/Verilog Netlist/netlist_BS_AMP_part1.v +++ /dev/null @@ -1,51 +0,0 @@ -//Verilog block level netlist file for netlist_BS_AMP -//Generated by UMN for ALIGN project - -module netlist_BS_AMP ( VDD ); -input VDD; -Amp_diff_norm_rvt I37 ( .IBSn(net022), .IN(net019), .IP(net020), .ON(rON), .OP(rOP), .VDD(VDD), .VSS(gnd!) ); -IBS_norm_rvt I34 ( .IBS_IN(net021), .IBSn_OUT(net038), .IBSp_OUT(net022), .VDD(VDD), .VSS(gnd!) ); -IBS_norm_rvt I6 ( .IBS_IN(net013), .IBSn_OUT(net06), .IBSp_OUT(net032), .VDD(VDD), .VSS(gnd!) ); -res_3K RR1 ( .LEFT(net038), .RIGHT(VDD) ); -res_3K RR2 ( .LEFT(net022), .RIGHT(gnd!) ); - -endmodule - -module SCM_BANK ( IBS_IN, IBSp_OUT, VDD, net7 ); -input IBS_IN, IBSp_OUT, VDD, net7; - -Switch_PMOS_1_4x3 MP0 ( .D(net7), .G(IBS_IN), .S(VDD) ); -Switch_PMOS_1_4x3 MP1 ( .D(IBS_IN), .G(IBS_IN), .S(VDD) ); -Switch_PMOS_4_4x3 MP2 ( .D(IBS_IN), .G(IBSp_OUT), .S(VDD) ); - -endmodule - -module IBS_norm_rvt ( IBS_IN, IBSn_OUT, IBSp_OUT, VDD, VSS ); -input IBS_IN, IBSn_OUT, IBSp_OUT, VDD, VSS; - -SCM_BANK MP0_MP1_MP2 ( .IBS_IN(IBS_IN), .IBSp_OUT(IBSp_OUT), .VDD(VDD), .net7(net7) ); -SCM_NMOS_1x4_4x3 MN1_MN2 ( .D1(net7), .D2(IBSn_OUT), .S(VSS) ); - -endmodule - -module Amp_diff_norm_rvt ( IBSn, IN, IP, ON, OP, VDD, VSS ); -input IBSn, IN, IP, ON, OP, VDD, VSS; - -res_3p83 RR0 ( .LEFT(ON), .RIGHT(VDD) ); -res_3p83 RR9 ( .RIGHT(OP), .LEFT(VDD) ); -SCM_NMOS_4x4_4x3 MN3_MN0 ( .D1(IBSn), .D2(net39), .S(VSS) ); -DP_NMOS_2x2_4x3 MN1_MN2 ( .D1(ON), .G1(IP), .S(net39), .D2(OP), .G2(IN) ); - -endmodule - - -// End HDL models -// Global nets module -`celldefine -module cds_globals; - -supply0 VDD; -supply1 VSS; - -endmodule -`endcelldefine diff --git a/DesignDatabase/Testcases/USC/Amplifier/Amplifier_2/Constraints/Amp_diff_norm_rvt.const b/DesignDatabase/Testcases/USC/Amplifier/Amplifier_2/Constraints/Amp_diff_norm_rvt.const deleted file mode 100644 index a13cde5db5..0000000000 --- a/DesignDatabase/Testcases/USC/Amplifier/Amplifier_2/Constraints/Amp_diff_norm_rvt.const +++ /dev/null @@ -1,5 +0,0 @@ -CritNet(net39, mid) -MatchBlock(MN3_MN0, MN1_MN2) -SymmBlock( {RR0, RR9} , MN1_MN2 ) -CritNet(ON, min) -CritNet(OP, min) diff --git a/DesignDatabase/Testcases/USC/Amplifier/Amplifier_2/Constraints/IBS_norm_rvt.const b/DesignDatabase/Testcases/USC/Amplifier/Amplifier_2/Constraints/IBS_norm_rvt.const deleted file mode 100644 index 8db4f7e7c7..0000000000 --- a/DesignDatabase/Testcases/USC/Amplifier/Amplifier_2/Constraints/IBS_norm_rvt.const +++ /dev/null @@ -1 +0,0 @@ -MatchBlock(MP0_MP1_MP2, MN1_MN2) diff --git a/DesignDatabase/Testcases/USC/Amplifier/Amplifier_2/Constraints/SCM_BANK.const b/DesignDatabase/Testcases/USC/Amplifier/Amplifier_2/Constraints/SCM_BANK.const deleted file mode 100644 index 2eb0f760d7..0000000000 --- a/DesignDatabase/Testcases/USC/Amplifier/Amplifier_2/Constraints/SCM_BANK.const +++ /dev/null @@ -1,2 +0,0 @@ -MatchBlock(MP0,MP1) -MatchBlock(MP0,MP2) diff --git a/DesignDatabase/Testcases/USC/Amplifier/Amplifier_2/Constraints/netlist_BS_AMP_part1.const b/DesignDatabase/Testcases/USC/Amplifier/Amplifier_2/Constraints/netlist_BS_AMP_part1.const deleted file mode 100644 index a13cde5db5..0000000000 --- a/DesignDatabase/Testcases/USC/Amplifier/Amplifier_2/Constraints/netlist_BS_AMP_part1.const +++ /dev/null @@ -1,5 +0,0 @@ -CritNet(net39, mid) -MatchBlock(MN3_MN0, MN1_MN2) -SymmBlock( {RR0, RR9} , MN1_MN2 ) -CritNet(ON, min) -CritNet(OP, min) diff --git a/DesignDatabase/Testcases/USC/Amplifier/Amplifier_2/LEF/BS_AMP.lef b/DesignDatabase/Testcases/USC/Amplifier/Amplifier_2/LEF/BS_AMP.lef deleted file mode 100644 index 06c2ea9d9a..0000000000 --- a/DesignDatabase/Testcases/USC/Amplifier/Amplifier_2/LEF/BS_AMP.lef +++ /dev/null @@ -1,240 +0,0 @@ -VERSION 5.7 ; -BUSBITCHARS "[]" ; -DIVIDERCHAR "/" ; - -MACRO res_3p83 - ORIGIN 0 0 ; - FOREIGN res_3p83 0 0 ; - SIZE 2.034 BY 1 ; - PIN LEFT - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M1 ; - RECT 0 0 0.018 0.018 ; - END - END LEFT - PIN RIGHT - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M1 ; - RECT 2.016 0 2.034 0.018 ; - END - END RIGHT - OBS - LAYER M1 ; - RECT 0.018 0.018 2.016 1 ; - END -END res_3p83 - -MACRO res_3K - ORIGIN 0 0 ; - FOREIGN res_3K 0 0 ; - SIZE 1.602 BY 1 ; - PIN LEFT - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M1 ; - RECT 0 0 0.018 0.018 ; - END - END LEFT - PIN RIGHT - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M1 ; - RECT 1.584 0 1.602 0.018 ; - END - END RIGHT - OBS - LAYER M1 ; - RECT 0.018 0.018 1.584 1 ; - END -END res_3K - -MACRO DP_NMOS_2x2_4x3 - ORIGIN 0 0 ; - FOREIGN DP_NMOS_2x2_4x3 0 0 ; - SIZE 0.864 BY 0.864 ; - PIN S - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 0.064 0.864 0.082 ; - END - END S - PIN D1 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 0.192 0.864 0.210 ; - END - END D1 - - PIN D2 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 0.128 0.864 0.146 ; - END - END D2 - -PIN G1 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 0 0.864 0.018 ; - END - END G1 - -PIN G2 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 0.256 0.864 0.274 ; - END - END G2 - - -END DP_NMOS_2x2_4x3 - -MACRO SCM_NMOS_4x4_4x3 - ORIGIN 0 0 ; - FOREIGN SCM_NMOS_4x4_4x3 0 0 ; - SIZE 0.864 BY 1.728 ; - PIN S - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 0.064 0.864 0.082 ; - END - END S - PIN D1 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 0.192 0.864 0.210 ; - END - END D1 - - PIN D2 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 0.128 0.864 0.146 ; - END - END D2 - - -END SCM_NMOS_4x4_4x3 - -MACRO Switch_PMOS_4_4x3 - ORIGIN 0 0 ; - FOREIGN Switch_PMOS_4_4x3 0 0 ; - SIZE 0.864 BY 0.864 ; - PIN S - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 0.064 0.864 0.082 ; - END - END S - - PIN D - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 0.128 0.864 0.146 ; - END - END D - - PIN G - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 0 0.864 0.018 ; - END - END D - - -END Switch_PMOS_4_4x3 - -MACRO Switch_PMOS_1_4x3 - ORIGIN 0 0 ; - FOREIGN Switch_PMOS_1_4x3 0 0 ; - SIZE 0.432 BY 0.432 ; - PIN S - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 0.064 0.432 0.082 ; - END - END S - - PIN D - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 0.128 0.432 0.146 ; - END - END D - - PIN G - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 0 0.432 0.018 ; - END - END D - - -END Switch_PMOS_1_4x3 - -MACRO SCM_NMOS_1x4_4x3 - ORIGIN 0 0 ; - FOREIGN SCM_NMOS_1x4_4x3 0 0 ; - SIZE 1.08 BY 0.432 ; - PIN S - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 0.064 1.08 0.082 ; - END - END S - PIN D1 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 0.192 1.08 0.210 ; - END - END D1 - - PIN D2 - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 0.128 1.08 0.146 ; - END - END D2 - - -END SCM_NMOS_1x4_4x3 diff --git a/DesignDatabase/Testcases/USC/Amplifier/Amplifier_2/Netlist/netlist_BS_AMP.sp b/DesignDatabase/Testcases/USC/Amplifier/Amplifier_2/Netlist/netlist_BS_AMP.sp deleted file mode 100644 index 1f10e5055b..0000000000 --- a/DesignDatabase/Testcases/USC/Amplifier/Amplifier_2/Netlist/netlist_BS_AMP.sp +++ /dev/null @@ -1,222 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: UM_GF14 -* Top Cell Name: TB_IBS_norm -* View Name: schematic -* Netlisted on: Jan 4 14:34:06 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM wireopt=9 - -*.GLOBAL gnd! - -*.PIN gnd! - -************************************************************************ -* Library Name: UM_GF14 -* Cell Name: IBS_norm_rvt -* View Name: schematic -************************************************************************ - -.SUBCKT IBS_norm_rvt IBS_IN IBSn_OUT IBSp_OUT VDD VSS -*.PININFO IBS_IN:B IBSn_OUT:B IBSp_OUT:B VDD:B VSS:B -MN2 IBSn_OUT net7 VSS VSS nfet m=4 l=14n nf=4 nfin=3 fpitch=48n cpp=78n -+ ngcon=1 p_la=0 plorient=0 -MN1 net7 net7 VSS VSS nfet m=1 l=14n nf=4 nfin=3 fpitch=48n cpp=78n ngcon=1 -+ p_la=0 plorient=0 -MP2 IBSp_OUT IBS_IN VDD VDD pfet m=4 l=16n nf=4 nfin=3 fpitch=48n cpp=78n -+ ngcon=1 p_la=0 plorient=0 -MP1 IBS_IN IBS_IN VDD VDD pfet m=1 l=14n nf=4 nfin=3 fpitch=48n cpp=78n -+ ngcon=1 p_la=0 plorient=0 -MP0 net7 IBS_IN VDD VDD pfet m=1 l=14n nf=4 nfin=3 fpitch=48n cpp=78n ngcon=1 -+ p_la=0 plorient=0 -.ENDS - -************************************************************************ -* Library Name: UM_GF14 -* Cell Name: IBS_norm_lvt -* View Name: schematic -************************************************************************ - -.SUBCKT IBS_norm_lvt IBS_IN IBSn_OUT IBSp_OUT VDD VSS -*.PININFO IBS_IN:B IBSn_OUT:B IBSp_OUT:B VDD:B VSS:B -MN1 net7 net7 VSS VSS lvtnfet m=1 l=14n nf=3 nfin=3 fpitch=48n cpp=78n ngcon=1 -+ p_la=0 plorient=0 -MN0 IBSn_OUT net7 VSS VSS lvtnfet m=4 l=14n nf=3 nfin=3 fpitch=48n cpp=78n -+ ngcon=1 p_la=0 plorient=0 -MP2 IBSp_OUT IBS_IN VDD VDD lvtpfet m=4 l=14n nf=3 nfin=3 fpitch=48n cpp=78n -+ ngcon=1 p_la=0 plorient=0 -MP1 IBS_IN IBS_IN VDD VDD lvtpfet m=1 l=14n nf=3 nfin=3 fpitch=48n cpp=78n -+ ngcon=1 p_la=0 plorient=0 -MP0 net7 IBS_IN VDD VDD lvtpfet m=1 l=14n nf=3 nfin=3 fpitch=48n cpp=78n -+ ngcon=1 p_la=0 plorient=0 -.ENDS - -************************************************************************ -* Library Name: UM_GF14 -* Cell Name: IBS_norm_hvt -* View Name: schematic -************************************************************************ - -.SUBCKT IBS_norm_hvt IBS_IN IBSn_OUT IBSp_OUT VDD VSS -*.PININFO IBS_IN:B IBSn_OUT:B IBSp_OUT:B VDD:B VSS:B -MN1 net7 net7 VSS VSS hvtnfet m=1 l=14n nf=4 nfin=3 fpitch=48n cpp=78n ngcon=1 -+ p_la=0 plorient=0 -MN0 IBSn_OUT net7 VSS VSS hvtnfet m=4 l=14n nf=4 nfin=3 fpitch=48n cpp=78n -+ ngcon=1 p_la=0 plorient=0 -MP2 IBSp_OUT IBS_IN VDD VDD hvtpfet m=4 l=16n nf=4 nfin=3 fpitch=48n cpp=78n -+ ngcon=1 p_la=0 plorient=0 -MP1 IBS_IN IBS_IN VDD VDD hvtpfet m=1 l=14n nf=4 nfin=3 fpitch=48n cpp=78n -+ ngcon=1 p_la=0 plorient=0 -MP0 net7 IBS_IN VDD VDD hvtpfet m=1 l=16n nf=4 nfin=3 fpitch=48n cpp=78n -+ ngcon=1 p_la=0 plorient=0 -.ENDS - -************************************************************************ -* Library Name: UM_GF14 -* Cell Name: IBS_norm_slvt -* View Name: schematic -************************************************************************ - -.SUBCKT IBS_norm_slvt IBS_IN IBSn_OUT IBSp_OUT VDD VSS -*.PININFO IBS_IN:B IBSn_OUT:B IBSp_OUT:B VDD:B VSS:B -MN1 net7 net7 VSS VSS slvtnfet m=1 l=14n nf=3 nfin=3 fpitch=48n cpp=78n -+ ngcon=1 p_la=0 plorient=0 -MN0 IBSn_OUT net7 VSS VSS slvtnfet m=4 l=14n nf=3 nfin=3 fpitch=48n cpp=78n -+ ngcon=1 p_la=0 plorient=0 -MP2 IBSp_OUT IBS_IN VDD VDD slvtpfet m=4 l=14n nf=3 nfin=3 fpitch=48n cpp=78n -+ ngcon=1 p_la=0 plorient=0 -MP1 IBS_IN IBS_IN VDD VDD slvtpfet m=1 l=14n nf=3 nfin=3 fpitch=48n cpp=78n -+ ngcon=1 p_la=0 plorient=0 -MP0 net7 IBS_IN VDD VDD slvtpfet m=1 l=14n nf=3 nfin=3 fpitch=48n cpp=78n -+ ngcon=1 p_la=0 plorient=0 -.ENDS - -************************************************************************ -* Library Name: UM_GF14 -* Cell Name: Amp_diff_norm_rvt -* View Name: schematic -************************************************************************ - -.SUBCKT Amp_diff_norm_rvt IBSn IN IP ON OP VDD VSS -*.PININFO IBSn:B IN:B IP:B ON:B OP:B VDD:B VSS:B -RR9 OP VDD $SUB=VDD $[rmres] m=1 l=1u w=280n r=3.83529K sbar=2 pbar=1 -+ orientation=1 r_cut=0 -RR0 ON VDD $SUB=VDD $[rmres] m=1 l=1u w=280n r=3.83529K sbar=2 pbar=1 -+ orientation=1 r_cut=0 -MN3 IBSn IBSn VSS VSS nfet m=4 l=14n nf=4 nfin=3 fpitch=48n cpp=78n ngcon=1 -+ p_la=0 plorient=0 -MN2 OP IN net39 VSS nfet m=2 l=14n nf=4 nfin=3 fpitch=48n cpp=78n ngcon=1 -+ p_la=0 plorient=0 -MN1 ON IP net39 VSS nfet m=2 l=14n nf=4 nfin=3 fpitch=48n cpp=78n ngcon=1 -+ p_la=0 plorient=0 -MN0 net39 IBSn VSS VSS nfet m=4 l=14n nf=4 nfin=3 fpitch=48n cpp=78n ngcon=1 -+ p_la=0 plorient=0 -.ENDS - -************************************************************************ -* Library Name: UM_GF14 -* Cell Name: Amp_diff_norm_lvt -* View Name: schematic -************************************************************************ - -.SUBCKT Amp_diff_norm_lvt IBSn IN IP ON OP VDD VSS -*.PININFO IBSn:B IN:B IP:B ON:B OP:B VDD:B VSS:B -RR9 OP VDD $SUB=VDD $[rmres] m=1 l=1u w=280n r=3.83529K sbar=2 pbar=1 -+ orientation=1 r_cut=0 -RR0 ON VDD $SUB=VDD $[rmres] m=1 l=1u w=280n r=3.83529K sbar=2 pbar=1 -+ orientation=1 r_cut=0 -MN3 IBSn IBSn VSS VSS lvtnfet m=4 l=14n nf=2 nfin=3 fpitch=48n cpp=78n ngcon=1 -+ p_la=0 plorient=0 -MN2 OP IN net39 VSS lvtnfet m=2 l=14n nf=2 nfin=3 fpitch=48n cpp=78n ngcon=1 -+ p_la=0 plorient=0 -MN1 ON IP net39 VSS lvtnfet m=2 l=14n nf=2 nfin=3 fpitch=48n cpp=78n ngcon=1 -+ p_la=0 plorient=0 -MN0 net39 IBSn VSS VSS lvtnfet m=4 l=14n nf=2 nfin=3 fpitch=48n cpp=78n -+ ngcon=1 p_la=0 plorient=0 -.ENDS - -************************************************************************ -* Library Name: UM_GF14 -* Cell Name: Amp_diff_norm_hvt -* View Name: schematic -************************************************************************ - -.SUBCKT Amp_diff_norm_hvt IBSn IN IP ON OP VDD VSS -*.PININFO IBSn:B IN:B IP:B ON:B OP:B VDD:B VSS:B -MN3 IBSn IBSn VSS VSS hvtnfet m=4 l=14n nf=4 nfin=3 fpitch=48n cpp=78n ngcon=1 -+ p_la=0 plorient=0 -MN2 OP IN net39 VSS hvtnfet m=2 l=14n nf=4 nfin=3 fpitch=48n cpp=78n ngcon=1 -+ p_la=0 plorient=0 -MN1 ON IP net39 VSS hvtnfet m=2 l=14n nf=4 nfin=3 fpitch=48n cpp=78n ngcon=1 -+ p_la=0 plorient=0 -MN0 net39 IBSn VSS VSS hvtnfet m=4 l=14n nf=4 nfin=3 fpitch=48n cpp=78n -+ ngcon=1 p_la=0 plorient=0 -RR9 OP VDD $SUB=VDD $[rmres] m=1 l=1u w=280n r=3.83529K sbar=2 pbar=1 -+ orientation=1 r_cut=0 -RR0 ON VDD $SUB=VDD $[rmres] m=1 l=1u w=280n r=3.83529K sbar=2 pbar=1 -+ orientation=1 r_cut=0 -.ENDS - -************************************************************************ -* Library Name: UM_GF14 -* Cell Name: Amp_diff_norm_slvt -* View Name: schematic -************************************************************************ - -.SUBCKT Amp_diff_norm_slvt IBSn IN IP ON OP VDD VSS -*.PININFO IBSn:B IN:B IP:B ON:B OP:B VDD:B VSS:B -RR9 OP VDD $SUB=VDD $[rmres] m=1 l=1u w=280n r=3.83529K sbar=2 pbar=1 -+ orientation=1 r_cut=0 -RR0 ON VDD $SUB=VDD $[rmres] m=1 l=1u w=280n r=3.83529K sbar=2 pbar=1 -+ orientation=1 r_cut=0 -MN3 IBSn IBSn VSS VSS slvtnfet m=4 l=14n nf=2 nfin=3 fpitch=48n cpp=78n -+ ngcon=1 p_la=0 plorient=0 -MN2 OP IN net39 VSS slvtnfet m=2 l=14n nf=2 nfin=3 fpitch=48n cpp=78n ngcon=1 -+ p_la=0 plorient=0 -MN1 ON IP net39 VSS slvtnfet m=2 l=14n nf=2 nfin=3 fpitch=48n cpp=78n ngcon=1 -+ p_la=0 plorient=0 -MN0 net39 IBSn VSS VSS slvtnfet m=4 l=14n nf=2 nfin=3 fpitch=48n cpp=78n -+ ngcon=1 p_la=0 plorient=0 -.ENDS - -************************************************************************ -* Library Name: UM_GF14 -* Cell Name: TB_IBS_norm -* View Name: schematic -************************************************************************ - -.SUBCKT TB_IBS_norm VDD -*.PININFO VDD:B -XI34 net021 net038 net022 VDD gnd! -XI6 net013 net06 net032 VDD gnd! -XI44 net065 net059 net035 VDD gnd! -XI9 net011 net07 net012 VDD gnd! -RR8 net014 gnd! 3K $[RP] -RR7 net012 gnd! 3K $[RP] -RR6 net032 gnd! 3K $[RP] -RR5 net031 gnd! 3K $[RP] -RR1 VDD net05 3K $[RP] -RR4 VDD net08 3K $[RP] -RR2 VDD net06 3K $[RP] -RR3 VDD net07 3K $[RP] -XI22 net046 net042 net018 VDD gnd! -XI3 net015 net05 net031 VDD gnd! -XI47 net033 net061 net034 VDD gnd! -XI13 net010 net08 net014 VDD gnd! -XI37 net022 net019 net020 rON rOP VDD gnd! -XI51 net035 net066 net029 lON lOP VDD gnd! -XI30 net018 net030 net028 hON hOP VDD gnd! -XI43 net034 net062 net063 sON sOP VDD gnd! -.ENDS - diff --git a/DesignDatabase/Testcases/USC/Amplifier/Amplifier_2/Verilog Netlist/netlist_BS_AMP_part1.v b/DesignDatabase/Testcases/USC/Amplifier/Amplifier_2/Verilog Netlist/netlist_BS_AMP_part1.v deleted file mode 100644 index 49dada29af..0000000000 --- a/DesignDatabase/Testcases/USC/Amplifier/Amplifier_2/Verilog Netlist/netlist_BS_AMP_part1.v +++ /dev/null @@ -1,44 +0,0 @@ -//Verilog block level netlist file for netlist_BS_AMP -//Generated by UMN for ALIGN project - -module netlist_BS_AMP ( VDD ); -input VDD; -res_3p83 RR0 ( .LEFT(ON), .RIGHT(VDD) ); -res_3p83 RR9 ( .RIGHT(OP), .LEFT(VDD) ); -SCM_NMOS_4x4_4x3 MN3_MN0 ( .D1(net06), .D2(net39), .S(VSS) ); -DP_NMOS_2x2_4x3 MN1_MN2 ( .D1(ON), .G1(IP), .S(net39), .D2(OP), .G2(IN) ); -IBS_norm_rvt I34 ( .IBS_IN(net021), .IBSn_OUT(net038), .IBSp_OUT(net022), .VDD(VDD), .VSS(gnd!) ); -IBS_norm_rvt I6 ( .IBS_IN(net013), .IBSn_OUT(net06), .IBSp_OUT(net032), .VDD(VDD), .VSS(gnd!) ); -res_3K RR1 ( .LEFT(net038), .RIGHT(VDD) ); -res_3K RR2 ( .LEFT(net022), .RIGHT(gnd!) ); - -endmodule - -module SCM_BANK ( IBS_IN, IBSp_OUT, VDD, net7 ); -input IBS_IN, IBSp_OUT, VDD, net7; - -Switch_PMOS_1_4x3 MP0 ( .D(net7), .G(IBS_IN), .S(VDD) ); -Switch_PMOS_1_4x3 MP1 ( .D(IBS_IN), .G(IBS_IN), .S(VDD) ); -Switch_PMOS_4_4x3 MP2 ( .D(IBS_IN), .G(IBSp_OUT), .S(VDD) ); - -endmodule - -module IBS_norm_rvt ( IBS_IN, IBSn_OUT, IBSp_OUT, VDD, VSS ); -input IBS_IN, IBSn_OUT, IBSp_OUT, VDD, VSS; - -SCM_BANK MP0_MP1_MP2 ( .IBS_IN(IBS_IN), .IBSp_OUT(IBSp_OUT), .VDD(VDD), .net7(net7) ); -SCM_NMOS_1x4_4x3 MN1_MN2 ( .D1(net7), .D2(IBSn_OUT), .S(VSS) ); - -endmodule - - -// End HDL models -// Global nets module -`celldefine -module cds_globals; - -supply0 VDD; -supply1 VSS; - -endmodule -`endcelldefine diff --git a/DesignDatabase/Testcases/USC/Amplifier/README.md b/DesignDatabase/Testcases/USC/Amplifier/README.md deleted file mode 100644 index c5ddc76b8a..0000000000 --- a/DesignDatabase/Testcases/USC/Amplifier/README.md +++ /dev/null @@ -1,5 +0,0 @@ -Contains the BS amplifier circuit from the University of Southern California. - -Amplifier_1 : Contains the files for the amplifier circuit which includes the amplifier and current mirror bank stage (verilog netlist, .lef, constraints). The spice netlist contains annotated hierarchy. - -Amplifier_2 : Contains the files for the amplifier circuit which includes the amplifier and current mirror bank stage (verilog netlist, .lef, constraints). The hierarchy in the input netlist has been removed. \ No newline at end of file diff --git a/DesignDatabase/Testcases/USC/README.md b/DesignDatabase/Testcases/USC/README.md deleted file mode 100644 index 9b79df40d5..0000000000 --- a/DesignDatabase/Testcases/USC/README.md +++ /dev/null @@ -1,5 +0,0 @@ -This folder contains circuits that have been tried on the tool provided by the University of Southern California - -Amplifier : Contains the modules required by the tool (eg. netlist, constraints, LEF) for the Amplifier circuit - -Track and hold : Contains the modules required by the tool (eg. netlist, constraints, LEF) for the track and hold circuit diff --git a/DesignDatabase/Testcases/USC/Track and hold/README.md b/DesignDatabase/Testcases/USC/Track and hold/README.md deleted file mode 100644 index f462820dab..0000000000 --- a/DesignDatabase/Testcases/USC/Track and hold/README.md +++ /dev/null @@ -1,9 +0,0 @@ -This folder contains the track and hold circuit provided by the University of Southern California - -track_and_hold_1 : Contains files for the track and hold circuit (spice netlist, verilog netlist, .lef, constraints and the final placement results). - -track_and_hold_2 : Contains files for the track and hold circuit (spice netlist, verilog netlist, .lef, constraints and the final placement results). This contains capacitors with different aspect ratios compared to version track_and_hold_1. - -track_and_hold_3 : Contains files for the track and hold circuit (verilog netlist, .lef , and constraints). Additional hierarchy is created to ease placement and routing. - - diff --git a/DesignDatabase/Testcases/USC/Track and hold/track_and_hold_1/Constraints/track_hold.const b/DesignDatabase/Testcases/USC/Track and hold/track_and_hold_1/Constraints/track_hold.const deleted file mode 100644 index f0453b3d42..0000000000 --- a/DesignDatabase/Testcases/USC/Track and hold/track_and_hold_1/Constraints/track_hold.const +++ /dev/null @@ -1,9 +0,0 @@ -MatchBlock(CC0, CC1) -MatchBlock(CC1, CC2) -MatchBlock(CC2, CC3) -MatchBlock(CC4, CC5) -MatchBlock(CC5, CC6) -MatchBlock(CC6, CC7) -CritNet(OP, min) -CritNet(ON, min) -SymmBlock ( {MN0,MN2} , {MN1,MP0} , {CC0,CC4} , {CC1,CC5} , {CC2,CC6} , {CC3,CC7} ) \ No newline at end of file diff --git a/DesignDatabase/Testcases/USC/Track and hold/track_and_hold_1/LEF/track_hold.lef b/DesignDatabase/Testcases/USC/Track and hold/track_and_hold_1/LEF/track_hold.lef deleted file mode 100644 index c5ef5f26b9..0000000000 --- a/DesignDatabase/Testcases/USC/Track and hold/track_and_hold_1/LEF/track_hold.lef +++ /dev/null @@ -1,168 +0,0 @@ -VERSION 5.7 ; -BUSBITCHARS "[]" ; -DIVIDERCHAR "/" ; - -MACRO Cap_30f_1x3 - ORIGIN 0 0 ; - FOREIGN Cap_30f_1x3 0 0 ; - SIZE 6.75 BY 2.214 ; - PIN PLUS - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 2.196 6.75 2.214 ; - END - END PLUS - PIN MINUS - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 0 6.75 0.018 ; - END - END MINUS - OBS - LAYER M1 ; - RECT 0 0 6.75 2.214 ; - END - OBS - LAYER M2 ; - RECT 0.018 0.018 6.732 2.196 ; - END - OBS - LAYER M3 ; - RECT 0 0 6.75 2.214 ; - END -END Cap_30f_1x3 - -MACRO Cap_30f_3x1 - ORIGIN 0 0 ; - FOREIGN Cap_30f_3x1 0 0 ; - SIZE 2.214 BY 6.75 ; - PIN PLUS - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 0 0.018 6.75 ; - END - END PLUS - PIN MINUS - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 2.196 0 2.214 6.75 ; - END - END MINUS - OBS - LAYER M1 ; - RECT 0 0 2.214 6.75 ; - END - OBS - LAYER M2 ; - RECT 0.018 0.018 2.196 6.732 ; - END - OBS - LAYER M3 ; - RECT 0 0 2.214 6.75 ; - END -END Cap_30f_3x1 - -MACRO Cap_30f_1x1 - ORIGIN 0 0 ; - FOREIGN Cap_30f_1x1 0 0 ; - SIZE 3.87 BY 3.87 ; - PIN PLUS - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 3.852 3.87 3.87 ; - END - END PLUS - PIN MINUS - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 0 3.87 0.018 ; - END - END MINUS - OBS - LAYER M1 ; - RECT 0 0 3.87 3.87 ; - END - OBS - LAYER M2 ; - RECT 0.018 0.018 3.852 3.852 ; - END - OBS - LAYER M3 ; - RECT 0 0 3.87 3.87 ; - END -END Cap_30f_1x1 - -MACRO Switch_NMOS_16x8 - ORIGIN 0 0 ; - FOREIGN Switch_NMOS_16x8 0 0 ; - SIZE 0.864 BY 1.296 ; - PIN S - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 0.064 0.864 0.082 ; - END - END S - PIN D - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 0.128 0.864 0.146 ; - END - END D - PIN G - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 0 0.864 0.018 ; - END - END G - -END Switch_NMOS_16x8 - -MACRO Switch_PMOS_16x8 - ORIGIN 0 0 ; - FOREIGN Switch_PMOS_16x8 0 0 ; - SIZE 0.864 BY 1.296 ; - PIN S - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 0.064 0.864 0.082 ; - END - END S - PIN D - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 0.128 0.864 0.146 ; - END - END D - PIN G - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 0 0.864 0.018 ; - END - END G - -END Switch_PMOS_16x8 - diff --git a/DesignDatabase/Testcases/USC/Track and hold/track_and_hold_1/Netlist/netlist_TH.sp b/DesignDatabase/Testcases/USC/Track and hold/track_and_hold_1/Netlist/netlist_TH.sp deleted file mode 100644 index 7d09fa1568..0000000000 --- a/DesignDatabase/Testcases/USC/Track and hold/track_and_hold_1/Netlist/netlist_TH.sp +++ /dev/null @@ -1,48 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: UM_GF14 -* Top Cell Name: TH -* View Name: schematic -* Netlisted on: Jan 4 14:33:35 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM wireopt=9 - - - -************************************************************************ -* Library Name: UM_GF14 -* Cell Name: TH -* View Name: schematic -************************************************************************ - -.SUBCKT TH CN CP IN IP ON OP VCM VDD VSS -*.PININFO CN:B CP:B IN:B IP:B ON:B OP:B VCM:B VDD:B VSS:B -MP0 IN CN ON VDD slvtpfet m=4 l=14n nf=16 nfin=8 fpitch=48n cpp=78n ngcon=1 -+ p_la=0 plorient=0 -MN1 IP CN OP VDD slvtpfet m=4 l=14n nf=16 nfin=8 fpitch=48n cpp=78n ngcon=1 -+ p_la=0 plorient=0 -MN2 ON CP IN VSS slvtnfet m=4 l=14n nf=16 nfin=8 fpitch=48n cpp=78n ngcon=1 -+ p_la=0 plorient=0 -MN0 OP CP IP VSS slvtnfet m=4 l=14n nf=16 nfin=8 fpitch=48n cpp=78n ngcon=1 -+ p_la=0 plorient=0 -CC7 ON VCM $[vncap] $SUB=VSS m=1 w=3.555u l=7.165u botlev=15 toplev=17 volt=2.5 -CC6 ON VCM $[vncap] $SUB=VSS m=1 w=3.555u l=7.165u botlev=15 toplev=17 volt=2.5 -CC5 ON VCM $[vncap] $SUB=VSS m=1 w=3.555u l=7.165u botlev=15 toplev=17 volt=2.5 -CC4 ON VCM $[vncap] $SUB=VSS m=1 w=3.555u l=7.165u botlev=15 toplev=17 volt=2.5 -CC3 OP VCM $[vncap] $SUB=VSS m=1 w=3.555u l=7.165u botlev=15 toplev=17 volt=2.5 -CC2 OP VCM $[vncap] $SUB=VSS m=1 w=3.555u l=7.165u botlev=15 toplev=17 volt=2.5 -CC1 OP VCM $[vncap] $SUB=VSS m=1 w=3.555u l=7.165u botlev=15 toplev=17 volt=2.5 -CC0 OP VCM $[vncap] $SUB=VSS m=1 w=3.555u l=7.165u botlev=15 toplev=17 volt=2.5 -.ENDS - diff --git a/DesignDatabase/Testcases/USC/Track and hold/track_and_hold_1/Results/PlacementResult.png b/DesignDatabase/Testcases/USC/Track and hold/track_and_hold_1/Results/PlacementResult.png deleted file mode 100644 index f2f1fa36f2..0000000000 Binary files a/DesignDatabase/Testcases/USC/Track and hold/track_and_hold_1/Results/PlacementResult.png and /dev/null differ diff --git a/DesignDatabase/Testcases/USC/Track and hold/track_and_hold_1/Results/mydesign_dr_globalrouting_lef_test.json b/DesignDatabase/Testcases/USC/Track and hold/track_and_hold_1/Results/mydesign_dr_globalrouting_lef_test.json deleted file mode 100644 index 7b82af8692..0000000000 --- a/DesignDatabase/Testcases/USC/Track and hold/track_and_hold_1/Results/mydesign_dr_globalrouting_lef_test.json +++ /dev/null @@ -1,1972 +0,0 @@ -{ - "terminals": [ - { - "layer": "metal1", - "rect": [ - 0, - 0, - 18, - 990 - ], - "netName": "m1" - }, - { - "layer": "metal3", - "rect": [ - 0, - 0, - 18, - 990 - ], - "netName": "m3" - }, - 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"rect": [ - 0, - 972, - 18, - 990 - ], - "netName": "v1" - }, - { - "layer": "via2", - "rect": [ - 0, - 972, - 18, - 990 - ], - "netName": "v2" - } - ], - "globalRoutes": [], - "bbox": [ - 0, - 0, - 990, - 990 - ], - "globalRouteGrid": [] -} diff --git a/DesignDatabase/Testcases/USC/Track and hold/track_and_hold_1/Verilog Netlist/track_hold.v b/DesignDatabase/Testcases/USC/Track and hold/track_and_hold_1/Verilog Netlist/track_hold.v deleted file mode 100644 index 4c6de84204..0000000000 --- a/DesignDatabase/Testcases/USC/Track and hold/track_and_hold_1/Verilog Netlist/track_hold.v +++ /dev/null @@ -1,31 +0,0 @@ -//Verilog block level netlist file for netlist_TH -//Generated by UMN for ALIGN project - - -module top ( CN, CP, IN, IP, ON, OP, VCM, VDD, VSS ); -Cap_30f_1x3 CC0 ( .MINUS(VCM), .PLUS(OP) ); -Cap_30f_1x3 CC1 ( .MINUS(VCM), .PLUS(OP) ); -Cap_30f_1x3 CC2 ( .MINUS(VCM), .PLUS(OP) ); -Cap_30f_1x3 CC3 ( .MINUS(VCM), .PLUS(OP) ); -Cap_30f_1x3 CC4 ( .MINUS(VCM), .PLUS(ON) ); -Cap_30f_1x3 CC5 ( .MINUS(VCM), .PLUS(ON) ); -Cap_30f_1x3 CC6 ( .MINUS(VCM), .PLUS(ON) ); -Cap_30f_1x3 CC7 ( .MINUS(VCM), .PLUS(ON) ); -Switch_NMOS_16x8 MN0 ( .D(OP), .G(CP), .S(IP) ); -Switch_PMOS_16x8 MN1 ( .D(IP), .G(CN), .S(OP) ); -Switch_NMOS_16x8 MN2 ( .D(ON), .G(CP), .S(IN) ); -Switch_PMOS_16x8 MP0 ( .D(IN), .G(CN), .S(ON) ); - -endmodule - - -// End HDL models -// Global nets module -`celldefine -module cds_globals; - -supply0 VDD; -supply1 VSS; - -endmodule -`endcelldefine diff --git a/DesignDatabase/Testcases/USC/Track and hold/track_and_hold_2/Constraints/track_hold.const b/DesignDatabase/Testcases/USC/Track and hold/track_and_hold_2/Constraints/track_hold.const deleted file mode 100644 index f0453b3d42..0000000000 --- a/DesignDatabase/Testcases/USC/Track and hold/track_and_hold_2/Constraints/track_hold.const +++ /dev/null @@ -1,9 +0,0 @@ -MatchBlock(CC0, CC1) -MatchBlock(CC1, CC2) -MatchBlock(CC2, CC3) -MatchBlock(CC4, CC5) -MatchBlock(CC5, CC6) -MatchBlock(CC6, CC7) -CritNet(OP, min) -CritNet(ON, min) -SymmBlock ( {MN0,MN2} , {MN1,MP0} , {CC0,CC4} , {CC1,CC5} , {CC2,CC6} , {CC3,CC7} ) \ No newline at end of file diff --git a/DesignDatabase/Testcases/USC/Track and hold/track_and_hold_2/LEF/track_hold.lef b/DesignDatabase/Testcases/USC/Track and hold/track_and_hold_2/LEF/track_hold.lef deleted file mode 100644 index c5ef5f26b9..0000000000 --- a/DesignDatabase/Testcases/USC/Track and hold/track_and_hold_2/LEF/track_hold.lef +++ /dev/null @@ -1,168 +0,0 @@ -VERSION 5.7 ; -BUSBITCHARS "[]" ; -DIVIDERCHAR "/" ; - -MACRO Cap_30f_1x3 - ORIGIN 0 0 ; - FOREIGN Cap_30f_1x3 0 0 ; - SIZE 6.75 BY 2.214 ; - PIN PLUS - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 2.196 6.75 2.214 ; - END - END PLUS - PIN MINUS - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 0 6.75 0.018 ; - END - END MINUS - OBS - LAYER M1 ; - RECT 0 0 6.75 2.214 ; - END - OBS - LAYER M2 ; - RECT 0.018 0.018 6.732 2.196 ; - END - OBS - LAYER M3 ; - RECT 0 0 6.75 2.214 ; - END -END Cap_30f_1x3 - -MACRO Cap_30f_3x1 - ORIGIN 0 0 ; - FOREIGN Cap_30f_3x1 0 0 ; - SIZE 2.214 BY 6.75 ; - PIN PLUS - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 0 0.018 6.75 ; - END - END PLUS - PIN MINUS - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 2.196 0 2.214 6.75 ; - END - END MINUS - OBS - LAYER M1 ; - RECT 0 0 2.214 6.75 ; - END - OBS - LAYER M2 ; - RECT 0.018 0.018 2.196 6.732 ; - END - OBS - LAYER M3 ; - RECT 0 0 2.214 6.75 ; - END -END Cap_30f_3x1 - -MACRO Cap_30f_1x1 - ORIGIN 0 0 ; - FOREIGN Cap_30f_1x1 0 0 ; - SIZE 3.87 BY 3.87 ; - PIN PLUS - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 3.852 3.87 3.87 ; - END - END PLUS - PIN MINUS - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 0 3.87 0.018 ; - END - END MINUS - OBS - LAYER M1 ; - RECT 0 0 3.87 3.87 ; - END - OBS - LAYER M2 ; - RECT 0.018 0.018 3.852 3.852 ; - END - OBS - LAYER M3 ; - RECT 0 0 3.87 3.87 ; - END -END Cap_30f_1x1 - -MACRO Switch_NMOS_16x8 - ORIGIN 0 0 ; - FOREIGN Switch_NMOS_16x8 0 0 ; - SIZE 0.864 BY 1.296 ; - PIN S - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 0.064 0.864 0.082 ; - END - END S - PIN D - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 0.128 0.864 0.146 ; - END - END D - PIN G - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 0 0.864 0.018 ; - END - END G - -END Switch_NMOS_16x8 - -MACRO Switch_PMOS_16x8 - ORIGIN 0 0 ; - FOREIGN Switch_PMOS_16x8 0 0 ; - SIZE 0.864 BY 1.296 ; - PIN S - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 0.064 0.864 0.082 ; - END - END S - PIN D - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 0.128 0.864 0.146 ; - END - END D - PIN G - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 0 0.864 0.018 ; - END - END G - -END Switch_PMOS_16x8 - diff --git a/DesignDatabase/Testcases/USC/Track and hold/track_and_hold_2/Netlist/netlist_TH.sp b/DesignDatabase/Testcases/USC/Track and hold/track_and_hold_2/Netlist/netlist_TH.sp deleted file mode 100644 index 7d09fa1568..0000000000 --- a/DesignDatabase/Testcases/USC/Track and hold/track_and_hold_2/Netlist/netlist_TH.sp +++ /dev/null @@ -1,48 +0,0 @@ -************************************************************************ -* auCdl Netlist: -* -* Library Name: UM_GF14 -* Top Cell Name: TH -* View Name: schematic -* Netlisted on: Jan 4 14:33:35 2019 -************************************************************************ - -*.BIPOLAR -*.RESI = 2000 -*.RESVAL -*.CAPVAL -*.DIOPERI -*.DIOAREA -*.EQUATION -*.SCALE METER -*.MEGA -.PARAM wireopt=9 - - - -************************************************************************ -* Library Name: UM_GF14 -* Cell Name: TH -* View Name: schematic -************************************************************************ - -.SUBCKT TH CN CP IN IP ON OP VCM VDD VSS -*.PININFO CN:B CP:B IN:B IP:B ON:B OP:B VCM:B VDD:B VSS:B -MP0 IN CN ON VDD slvtpfet m=4 l=14n nf=16 nfin=8 fpitch=48n cpp=78n ngcon=1 -+ p_la=0 plorient=0 -MN1 IP CN OP VDD slvtpfet m=4 l=14n nf=16 nfin=8 fpitch=48n cpp=78n ngcon=1 -+ p_la=0 plorient=0 -MN2 ON CP IN VSS slvtnfet m=4 l=14n nf=16 nfin=8 fpitch=48n cpp=78n ngcon=1 -+ p_la=0 plorient=0 -MN0 OP CP IP VSS slvtnfet m=4 l=14n nf=16 nfin=8 fpitch=48n cpp=78n ngcon=1 -+ p_la=0 plorient=0 -CC7 ON VCM $[vncap] $SUB=VSS m=1 w=3.555u l=7.165u botlev=15 toplev=17 volt=2.5 -CC6 ON VCM $[vncap] $SUB=VSS m=1 w=3.555u l=7.165u botlev=15 toplev=17 volt=2.5 -CC5 ON VCM $[vncap] $SUB=VSS m=1 w=3.555u l=7.165u botlev=15 toplev=17 volt=2.5 -CC4 ON VCM $[vncap] $SUB=VSS m=1 w=3.555u l=7.165u botlev=15 toplev=17 volt=2.5 -CC3 OP VCM $[vncap] $SUB=VSS m=1 w=3.555u l=7.165u botlev=15 toplev=17 volt=2.5 -CC2 OP VCM $[vncap] $SUB=VSS m=1 w=3.555u l=7.165u botlev=15 toplev=17 volt=2.5 -CC1 OP VCM $[vncap] $SUB=VSS m=1 w=3.555u l=7.165u botlev=15 toplev=17 volt=2.5 -CC0 OP VCM $[vncap] $SUB=VSS m=1 w=3.555u l=7.165u botlev=15 toplev=17 volt=2.5 -.ENDS - diff --git a/DesignDatabase/Testcases/USC/Track and hold/track_and_hold_2/Results/PlacementResult.png b/DesignDatabase/Testcases/USC/Track and hold/track_and_hold_2/Results/PlacementResult.png deleted file mode 100644 index f2f1fa36f2..0000000000 Binary files a/DesignDatabase/Testcases/USC/Track and hold/track_and_hold_2/Results/PlacementResult.png and /dev/null differ diff --git a/DesignDatabase/Testcases/USC/Track and hold/track_and_hold_2/Results/mydesign_dr_globalrouting_lef_test.json b/DesignDatabase/Testcases/USC/Track and hold/track_and_hold_2/Results/mydesign_dr_globalrouting_lef_test.json deleted file mode 100644 index 7b82af8692..0000000000 --- a/DesignDatabase/Testcases/USC/Track and hold/track_and_hold_2/Results/mydesign_dr_globalrouting_lef_test.json +++ /dev/null @@ -1,1972 +0,0 @@ -{ - "terminals": [ - { - "layer": "metal1", - "rect": [ - 0, - 0, - 18, - 990 - ], - "netName": "m1" - }, - { - "layer": "metal3", - "rect": [ - 0, - 0, - 18, - 990 - ], - "netName": "m3" - }, - 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18, - 702 - ], - "netName": "v2" - }, - { - "layer": "metal2", - "rect": [ - 0, - 720, - 990, - 738 - ], - "netName": "m2" - }, - { - "layer": "via1", - "rect": [ - 972, - 720, - 990, - 738 - ], - "netName": "v1" - }, - { - "layer": "via2", - "rect": [ - 972, - 720, - 990, - 738 - ], - "netName": "v2" - }, - { - "layer": "metal2", - "rect": [ - 0, - 756, - 990, - 774 - ], - "netName": "m2" - }, - { - "layer": "via1", - "rect": [ - 0, - 756, - 18, - 774 - ], - "netName": "v1" - }, - { - "layer": "via2", - "rect": [ - 0, - 756, - 18, - 774 - ], - "netName": "v2" - }, - { - "layer": "metal2", - "rect": [ - 0, - 792, - 990, - 810 - ], - "netName": "m2" - }, - { - "layer": "via1", - "rect": [ - 972, - 792, - 990, - 810 - ], - "netName": "v1" - }, - { - "layer": "via2", - "rect": [ - 972, - 792, - 990, - 810 - ], - "netName": "v2" - }, - { - "layer": "metal2", - "rect": [ - 0, - 828, - 990, - 846 - ], - "netName": "m2" - }, - { - "layer": "via1", - "rect": [ - 0, - 828, - 18, - 846 - ], - "netName": "v1" - }, - { - "layer": "via2", - "rect": [ - 0, - 828, - 18, - 846 - ], - "netName": "v2" - }, - { - "layer": "metal2", - "rect": [ - 0, - 864, - 990, - 882 - ], - "netName": "m2" - }, - { - "layer": "via1", - "rect": [ - 972, - 864, - 990, - 882 - ], - "netName": "v1" - }, - { - "layer": "via2", - "rect": [ - 972, - 864, - 990, - 882 - ], - "netName": "v2" - }, - { - "layer": "metal2", - "rect": [ - 0, - 900, - 990, - 918 - ], - "netName": "m2" - }, - { - "layer": "via1", - "rect": [ - 0, - 900, - 18, - 918 - ], - "netName": "v1" - }, - { - "layer": "via2", - "rect": [ - 0, - 900, - 18, - 918 - ], - "netName": "v2" - }, - { - "layer": "metal2", - "rect": [ - 0, - 936, - 990, - 954 - ], - "netName": "m2" - }, - { - "layer": "via1", - "rect": [ - 972, - 936, - 990, - 954 - ], - "netName": "v1" - }, - { - "layer": "via2", - "rect": [ - 972, - 936, - 990, - 954 - ], - "netName": "v2" - }, - { - "layer": "metal2", - "rect": [ - 0, - 972, - 990, - 990 - ], - "netName": "m2" - }, - { - "layer": "via1", - "rect": [ - 0, - 972, - 18, - 990 - ], - "netName": "v1" - }, - { - "layer": "via2", - "rect": [ - 0, - 972, - 18, - 990 - ], - "netName": "v2" - } - ], - "globalRoutes": [], - "bbox": [ - 0, - 0, - 990, - 990 - ], - "globalRouteGrid": [] -} diff --git a/DesignDatabase/Testcases/USC/Track and hold/track_and_hold_2/Verilog Netlist/track_hold.v b/DesignDatabase/Testcases/USC/Track and hold/track_and_hold_2/Verilog Netlist/track_hold.v deleted file mode 100644 index f595efd9bf..0000000000 --- a/DesignDatabase/Testcases/USC/Track and hold/track_and_hold_2/Verilog Netlist/track_hold.v +++ /dev/null @@ -1,31 +0,0 @@ -//Verilog block level netlist file for netlist_TH -//Generated by UMN for ALIGN project - - -module top ( CN, CP, IN, IP, ON, OP, VCM, VDD, VSS ); -Cap_30f_1x1 CC0 ( .MINUS(VCM), .PLUS(OP) ); -Cap_30f_1x1 CC1 ( .MINUS(VCM), .PLUS(OP) ); -Cap_30f_1x1 CC2 ( .MINUS(VCM), .PLUS(OP) ); -Cap_30f_1x1 CC3 ( .MINUS(VCM), .PLUS(OP) ); -Cap_30f_1x1 CC4 ( .MINUS(VCM), .PLUS(ON) ); -Cap_30f_1x1 CC5 ( .MINUS(VCM), .PLUS(ON) ); -Cap_30f_1x1 CC6 ( .MINUS(VCM), .PLUS(ON) ); -Cap_30f_1x1 CC7 ( .MINUS(VCM), .PLUS(ON) ); -Switch_NMOS_16x8 MN0 ( .D(OP), .G(CP), .S(IP) ); -Switch_PMOS_16x8 MN1 ( .D(IP), .G(CN), .S(OP) ); -Switch_NMOS_16x8 MN2 ( .D(ON), .G(CP), .S(IN) ); -Switch_PMOS_16x8 MP0 ( .D(IN), .G(CN), .S(ON) ); - -endmodule - - -// End HDL models -// Global nets module -`celldefine -module cds_globals; - -supply0 VDD; -supply1 VSS; - -endmodule -`endcelldefine diff --git a/DesignDatabase/Testcases/USC/Track and hold/track_and_hold_3/Constraints/track_hold.const b/DesignDatabase/Testcases/USC/Track and hold/track_and_hold_3/Constraints/track_hold.const deleted file mode 100644 index 1e3f2694ae..0000000000 --- a/DesignDatabase/Testcases/USC/Track and hold/track_and_hold_3/Constraints/track_hold.const +++ /dev/null @@ -1 +0,0 @@ -SymmBlock ( {I0,I1} ) diff --git a/DesignDatabase/Testcases/USC/Track and hold/track_and_hold_3/LEF/track_hold.lef b/DesignDatabase/Testcases/USC/Track and hold/track_and_hold_3/LEF/track_hold.lef deleted file mode 100644 index 4a0ff1b7aa..0000000000 --- a/DesignDatabase/Testcases/USC/Track and hold/track_and_hold_3/LEF/track_hold.lef +++ /dev/null @@ -1,126 +0,0 @@ -VERSION 5.7 ; -BUSBITCHARS "[]" ; -DIVIDERCHAR "/" ; - -MACRO Cap_30f_1x3 - ORIGIN 0 0 ; - FOREIGN Cap_30f_1x3 0 0 ; - SIZE 6.75 BY 2.214 ; - PIN PLUS - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 2.196 6.75 2.214 ; - END - END PLUS - PIN MINUS - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 0 6.75 0.018 ; - END - END MINUS - OBS - LAYER M1 ; - RECT 0 0 6.75 2.214 ; - LAYER M2 ; - RECT 0.018 0.018 6.732 2.196 ; - LAYER M3 ; - RECT 0 0 6.75 2.214 ; - END -END Cap_30f_1x3 - -MACRO Cap_30f_3x1 - ORIGIN 0 0 ; - FOREIGN Cap_30f_3x1 0 0 ; - SIZE 2.214 BY 6.75 ; - PIN PLUS - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 0 0.018 6.75 ; - END - END PLUS - PIN MINUS - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 2.196 0 2.214 6.75 ; - END - END MINUS - OBS - LAYER M1 ; - RECT 0 0 2.214 6.75 ; - LAYER M2 ; - RECT 0.018 0.018 2.196 6.732 ; - LAYER M3 ; - RECT 0 0 2.214 6.75 ; - END -END Cap_30f_3x1 - -MACRO Switch_NMOS_16x8 - ORIGIN 0 0 ; - FOREIGN Switch_NMOS_16x8 0 0 ; - SIZE 0.864 BY 1.296 ; - PIN S - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 0.064 0.864 0.082 ; - END - END S - PIN D - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 0.128 0.864 0.146 ; - END - END D - PIN G - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 0 0.864 0.018 ; - END - END G - -END Switch_NMOS_16x8 - -MACRO Switch_PMOS_16x8 - ORIGIN 0 0 ; - FOREIGN Switch_PMOS_16x8 0 0 ; - SIZE 0.864 BY 1.296 ; - PIN S - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 0.064 0.864 0.082 ; - END - END S - PIN D - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 0.128 0.864 0.146 ; - END - END D - PIN G - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 0 0.864 0.018 ; - END - END G - -END Switch_PMOS_16x8 - diff --git a/DesignDatabase/Testcases/USC/Track and hold/track_and_hold_3/Verilog Netlist/track_hold.v b/DesignDatabase/Testcases/USC/Track and hold/track_and_hold_3/Verilog Netlist/track_hold.v deleted file mode 100644 index cc59b889c6..0000000000 --- a/DesignDatabase/Testcases/USC/Track and hold/track_and_hold_3/Verilog Netlist/track_hold.v +++ /dev/null @@ -1,30 +0,0 @@ -//Verilog block level netlist file for netlist_TH -//Generated by UMN for ALIGN project - -module track_and_hold_single_ended ( CN, CP, IN, ON, VCM, VDD, VSS ); -Cap_30f_1x3 CC0 ( .MINUS(VCM), .PLUS(OP) ); -Cap_30f_1x3 CC1 ( .MINUS(VCM), .PLUS(OP) ); -Cap_30f_1x3 CC2 ( .MINUS(VCM), .PLUS(OP) ); -Cap_30f_1x3 CC3 ( .MINUS(VCM), .PLUS(OP) ); -Switch_NMOS_16x8 MN0 ( .D(OP), .G(CP), .S(IP) ); -Switch_PMOS_16x8 MN1 ( .D(IP), .G(CN), .S(OP) ); - -endmodule - -module top ( CN, CP, IN, IP, ON, OP, VCM, VDD, VSS ); -track_and_hold_single_ended I0( CN, CP, IN, ON, VCM, VDD, VSS ); -track_and_hold_single_ended I1( CN, CP, IP, OP, VCM, VDD, VSS ); - -endmodule - - -// End HDL models -// Global nets module -`celldefine -module cds_globals; - -supply0 VDD; -supply1 VSS; - -endmodule -`endcelldefine diff --git a/DesignDatabase/Testcases/UVA/Tristate_buffer/README.md b/DesignDatabase/Testcases/UVA/Tristate_buffer/README.md deleted file mode 100644 index 0c2a72a367..0000000000 --- a/DesignDatabase/Testcases/UVA/Tristate_buffer/README.md +++ /dev/null @@ -1,3 +0,0 @@ -Contains the tri-state buffer circuit provided by the University of Virginia. - -tristate_buffer_1 : Contains the file for the tristate buffer (verilog netlist, .lef). \ No newline at end of file diff --git a/DesignDatabase/Testcases/UVA/Tristate_buffer/tristate_buffer_1/LEF/Tri_state.lef b/DesignDatabase/Testcases/UVA/Tristate_buffer/tristate_buffer_1/LEF/Tri_state.lef deleted file mode 100644 index 2776d80037..0000000000 --- a/DesignDatabase/Testcases/UVA/Tristate_buffer/tristate_buffer_1/LEF/Tri_state.lef +++ /dev/null @@ -1,67 +0,0 @@ -VERSION 5.7 ; -BUSBITCHARS "[]" ; -DIVIDERCHAR "/" ; -MACRO Switch_PMOS_10_1x1 - ORIGIN 0 0 ; - FOREIGN Switch_PMOS_10_1x1 0 0 ; - SIZE 0.432 BY 0.378 ; - PIN S - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 0.064 0.432 0.082 ; - END - END S - - PIN D - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 0.128 0.432 0.146 ; - END - END D - - PIN G - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 0 0.432 0.018 ; - END - END D -END Switch_PMOS_10_1x1 - -MACRO Switch_NMOS_10_1x1 - ORIGIN 0 0 ; - FOREIGN Switch_NMOS_10_1x1 0 0 ; - SIZE 0.432 BY 0.378 ; - PIN S - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 0.064 0.432 0.082 ; - END - END S - - PIN D - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 0.128 0.432 0.146 ; - END - END D - - PIN G - DIRECTION INOUT ; - USE SIGNAL ; - PORT - LAYER M2 ; - RECT 0 0 0.432 0.018 ; - END - END D -END Switch_NMOS_10_1x1 - diff --git a/DesignDatabase/Testcases/UVA/Tristate_buffer/tristate_buffer_1/Netlist/Tristate_buffer.cdl b/DesignDatabase/Testcases/UVA/Tristate_buffer/tristate_buffer_1/Netlist/Tristate_buffer.cdl deleted file mode 100644 index 8ec5129ddc..0000000000 --- a/DesignDatabase/Testcases/UVA/Tristate_buffer/tristate_buffer_1/Netlist/Tristate_buffer.cdl +++ /dev/null @@ -1,13 +0,0 @@ -.PARAM wdef=60n -.PARAM minl=20n - -.subckt Tristate_buffer vin vout enable VDD VSS - -M5 inv_out enable VSS VSS nfet l=minl w=wdef nfin=20 -M1 vout vin net26 VSS nfet l=minl w=wdef nfin=20 -M0 net26 enable VSS VSS nfet l=minl w=wdef nfin=20 -M3 net30 inv_out VDD VDD pfet l=minl w=wdef nfin=20 -M4 inv_out enable VDD VDD pfet l=minl w=wdef nfin=20 -M2 vout vin net30 VDD pfet l=minl w=wdef nfin=20 -.ends - diff --git a/DesignDatabase/Testcases/UVA/Tristate_buffer/tristate_buffer_1/Verilog Netlist/Tristate_buffer.v b/DesignDatabase/Testcases/UVA/Tristate_buffer/tristate_buffer_1/Verilog Netlist/Tristate_buffer.v deleted file mode 100644 index 077445047d..0000000000 --- a/DesignDatabase/Testcases/UVA/Tristate_buffer/tristate_buffer_1/Verilog Netlist/Tristate_buffer.v +++ /dev/null @@ -1,27 +0,0 @@ -//Verilog block level netlist file for Tristate_buffer -//Generated by UMN for ALIGN project - - -module Tristate_buffer ( VSS, VDD, vout, enable, vin ); -inout VSS, VDD, vout, enable, vin; - -Switch_NMOS_10_1x1 M0 ( .D(net26), .G(enable), .S(VSS) ); -Switch_NMOS_10_1x1 M1 ( .D(vout), .G(vin), .S(net26) ); -Switch_PMOS_10_1x1 M2 ( .D(vout), .G(vin), .S(net30) ); -Switch_PMOS_10_1x1 M3 ( .D(net30), .G(inv_out), .S(VDD) ); -Switch_PMOS_10_1x1 M4 ( .D(inv_out), .G(enable), .S(VDD) ); -Switch_NMOS_10_1x1 M5 ( .D(inv_out), .G(enable), .S(VSS) ); - -endmodule - - -// End HDL models -// Global nets module -`celldefine -module cds_globals; - -supply0 VDD; -supply1 VSS; - -endmodule -`endcelldefine \ No newline at end of file